From 04bf834a3a1f14d18351fe3886a17c15f4f64eda Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 7 Apr 2014 13:54:16 +0200 Subject: [PATCH] internal oscillator is added for calibration --- cbmtof/cbmtof.vhd | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index 4d8e411..4e3f85f 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -108,7 +108,7 @@ architecture cbmtof_arch of cbmtof is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal clk_20_i : std_logic; --clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -323,13 +323,11 @@ begin LOCK => pll_lock ); - -- generates hits for calibration uncorrelated with tdc clk - THE_CALIBRATION_PLL : pll_in125_out20 + -- internal oscillator with frequency of 2.5MHz for tdc calibration + OSCInst0 : OSCF port map ( - CLK => CLK_CM(4), - CLKOP => clk_20_i, - CLKOK => open, --clk_125_i, - LOCK => open); + OSC => osc_int); + --------------------------------------------------------------------------- @@ -859,7 +857,7 @@ begin CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC + HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width -- -- 2.43.0