From 04e37c3e12950865831f615f95e37c205d7496d0 Mon Sep 17 00:00:00 2001 From: hadaq Date: Fri, 3 Apr 2009 08:55:59 +0000 Subject: [PATCH] status 2009-04-03, mp --- optical_link/compile_hub.pl | 121 ++- optical_link/flexi_PCS_channel_synch.vhd | 709 ++++++++----- optical_link/flexi_PCS_synch.vhd | 143 +-- optical_link/hub.lpf | 146 ++- optical_link/hub.vhd | 1200 +++++++++++----------- optical_link/hub_1.xcf | 2 +- optical_link/hub_syn.prj | 134 +-- optical_link/serdes_fpga_ref_clk.txt | 1 + optical_link/trb_hub_interface.vhd | 5 +- 9 files changed, 1436 insertions(+), 1025 deletions(-) diff --git a/optical_link/compile_hub.pl b/optical_link/compile_hub.pl index 9baf39f..d282c54 100755 --- a/optical_link/compile_hub.pl +++ b/optical_link/compile_hub.pl @@ -11,28 +11,72 @@ use FileHandle; -$ENV{LM_LICENSE_FILE}="1709\@hadeb05"; +use Data::Dumper; +use warnings; +use strict; -$PLD_DEVICE="LFSCM3GA25EP1-5FFN1020C"; -$TOPNAME="hub"; +$ENV{LM_LICENSE_FILE}="1710\@cronos.e12.physik.tu-muenchen.de"; +my $synplify_path = '/opt/Synplicity/syn_96L2/synplify_linux/bin/'; + +$ENV{'SYNPLIFY'}="/opt/Synplicity/syn_96L2/synplify_linux/"; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; + + +my $base = "/opt/lattice/ispLEVER7.2/isptools"; + +my $FAMILYNAME="LatticeSCM"; +my $PLD_DEVICE="LFSCM3GA25EP1"; +my $PACKAGE="FFBGA1020"; + +my $TOPNAME="hub"; + +my $t=time; + +my $fh = new FileHandle(">version.vhd"); + +die "could not open file" if (! defined $fh); + +print $fh <close; #set -e #set -o errexit system("env| grep LM_"); -$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +#$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +#$c="/opt/Synplicity/syn_96L2/synplify_linux/bin/synpwrap_pro.sh -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +#execute($c); #$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; #$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj"); -$r=execute($c, "do_not_exit" ); +#$r=execute($c, "do_not_exit" ); +my $c="$synplify_path/synpwrap -Pro -prj $TOPNAME"."_syn.prj"; +my $r=execute($c, "do_not_exit" ); chdir "workdir"; -my $fh = new FileHandle("; $fh -> close; @@ -44,7 +88,7 @@ $fh -> close; foreach (@a) { - if(/\@E:/) + if( /\@E:/ || /\@E\|/ ) { $c="cat $TOPNAME.srr"; system($c); @@ -59,61 +103,70 @@ foreach (@a) #$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/edfin -i hub.edf -jhd hub.jhd -log hub.log -dev orca -lbp \"/opt/lattice/isplever7.0/isptools/ispfpga/data\""); -#$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/lci2prf -oc hub.lct -log hub.log ../hub.lpf"); +#$c=("/opt/lattice/isplever7.0//ispfpga/bin/lin/lci2prf -oc hub.lct -log hub.log ../hub.lpf"); -#$c=("export FOUNDRY=\"/opt/lattice/isplever7.0/isptools/ispfpga\""); +#$c=("export FOUNDRY=\"/opt/lattice/isplever7.0//ispfpga\""); -#$c=("export LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH:/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin\""); +#$c=("export LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH:/opt/lattice/isplever7.0//ispfpga/bin/lin\""); -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/edif2ngd -l LatticeSCM -d LFSCM3GA25EP1 \"hub.edf\" \"hub.ngo\""); -execute($c); +$c= qq|$base/ispfpga/bin/lin/edif2ngd -l "$FAMILYNAME" -d "$PLD_DEVICE" "$TOPNAME.edf" "$TOPNAME.ngo"|; execute($c); -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/edfupdate -t \"hub.tcy\" -w \"hub.ngo\" -m \"hub.ngo\" \"hub.ngx\""); +$c=qq|$base/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; execute($c); -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/ngdbuild -a LatticeSCM -d LFSCM3GA25EP1 -p \"/opt/lattice/isplever7.0/isptools/ispfpga/or5s00/data\" -dt \"hub.ngo\" \"hub.ngd\""); +$c=qq|$base/ispfpga/bin/lin/ngdbuild -a "$FAMILYNAME" -d "$PLD_DEVICE" -p "$base/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; execute($c); -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/map -a LatticeSCM -p LFSCM3GA25EP1 -t FFBGA1020 -s 5 \"hub.ngd\" -o \"hub_map.ncd\" -mp \"hub.mrp\" \"hub.lpf\""); -execute($c); - -#$c=("/home/marek/.isplever_lin1/ispcpld/bin/checkpoint -to \"checkpnt.twr\" -log \"hub.log\" -rpt \"hub.mrp\" -m -f \"hub.cmm\" -f \"hub.cm2\" -arch LatticeSCM \"hub_map.ncd\""); -#execute($c); +my $tpmap = $TOPNAME . "_map" ; -#$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/trce -v 1 -gt -o checkpnt.twr hub_map.ncd hub.prf"); +$c=qq|$base/ispfpga/bin/lin/map -a "$FAMILYNAME" -p "$PLD_DEVICE" -t "$PACKAGE" -s 5 "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); -#$c="/home/marek/.isplever_lin1/ispcpld/bin/checkpoint -to \"checkpnt.twr\" -log \"hub.log\" -rpt \"hub.mrp\" -m -f \"hub.cmm\" -f \"hub.cm2\" -arch LatticeSCM \"hub_map.ncd\""; -system("rm hub.ncd"); +system("rm $TOPNAME.ncd"); #execute($c); -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/multipar -pr \"hub.prf\" -o \"hub_mpar.rpt\" -log \"hub_mpar.log\" -p \"hub.p2t\" -f \"hub.p3t\" \"hub_map.ncd\" \"hub.ncd\""); +$c=qq|$base/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "$TOPNAME| . "_mpar.rpt" . qq|" -log "$TOPNAME| . "_mpar.log" . qq|" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|; execute($c); -#$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/par \"hub_map.ncd\" \"hub.ncd\""); -#execute($c); +# TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$base/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); +$c=qq|$base/ispfpga/bin/lin/trce -c -v 5 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/bitgen -w \"hub.ncd\" -f \"hub.t2b\" \"hub.prf\""); +$c=("$base/ispfpga/bin/lin/bitgen -w \"hub.ncd\" -f \"hub.t2b\" \"hub.prf\""); execute($c); #$c=(". ~/bin/ispvm17"); #execute($c); +$c=q| perl -ne '$in=1 if(/Report Summary/); print if($in==1); $in=0 if(/All preferences were met./)' | . "$TOPNAME.twr.setup"; +execute($c); + chdir ".."; +$c=("cat version.vhd | grep VERSION_NUMBER_TIME"); +execute($c); + +$c=q!cat version.vhd | perl -ne '($r)=grep(/VERSION_NUMBER_TIME/, $_); if($r) {($n)=$r=~/(\d+);/; printf("%x\n",$n);} '!; +execute($c); + #$c=(". ~/bin/ispvm17"); -$c=("ispvm -infile hub_1.xcf -outfiletype -svf"); -execute($c); -$c=("perl -i -ne 'print unless(/!/)' hub_1.svf"); -execute($c); -$c=("impact -batch impact_batch_hub.txt"); -execute($c); -$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); -execute($c); +#$c=("ispvm -infile hub_1.xcf -outfiletype -stp"); +#execute($c); + +#$c=("perl -i -ne 'print unless(/!/)' hub_1.svf"); +#execute($c); +#$c=("impact -batch impact_batch_hub.txt"); +#execute($c); +#$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); +#execute($c); #} #$c=("impact -batch impact_batch_hub.txt"); diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd index 075520e..f6b0b42 100644 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ b/optical_link/flexi_PCS_channel_synch.vhd @@ -1,5 +1,6 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ieee; library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -8,30 +9,40 @@ use work.trb_net_std.all; use work.trb_net16_hub_func.all; entity flexi_PCS_channel_synch is - port ( - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + RESET : in std_logic; + SYSTEM_CLK : in std_logic; + --to and from media + TX_CLK : in std_logic; + RX_CLK : in std_logic; + RXD : in std_logic_vector(15 downto 0); + RX_K : in std_logic_vector(1 downto 0); + RX_RST : out std_logic; + CV : in std_logic_vector(1 downto 0); + TXD : out std_logic_vector(15 downto 0); + TX_K : out std_logic_vector(1 downto 0); + MEDIA_STATUS : in std_logic_vector(15 downto 0); + MEDIA_CONTROL : out std_logic_vector(15 downto 0); + --to and from trbnet + --to media + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector(15 downto 0); + MED_READ_OUT : out std_logic; + --from media + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + --trbnet control and status + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(2 downto 0); - MED_READ_IN : in std_logic + MED_STAT_OP : out std_logic_vector(15 downto 0); + MED_CTRL_OP : in std_logic_vector(15 downto 0); --debug + LINK_DEBUG : out std_logic_vector(31 downto 0) ); - end flexi_PCS_channel_synch; + architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is + component flexi_PCS_fifo_EBR port ( Data : in std_logic_vector(17 downto 0); @@ -45,39 +56,54 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is Empty : out std_logic; Full : out std_logic; AlmostEmpty : out std_logic; - AlmostFull : out std_logic); + AlmostFull : out std_logic + ); end component; - component simpleupcounter_32bit - port ( - QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_16bit + + component ecp2m_link_fifo port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_8bit + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(17 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic + ); + end component; + --keep fifos as small as possible, remember but low prioriority + --disable transmition during synch + component up_down_counter + generic ( + NUMBER_OF_BITS : positive); port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic; + DOWN_IN : in std_logic); + end component; + component edge_to_pulse port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); + CLOCK : in std_logic; + EN_CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE : out std_logic); end component; - type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, NORMAL_OPERATION_1, NORMAL_OPERATION_2); - signal SYNCH_CURRENT, SYNCH_NEXT : SYNCH_MACHINE; - signal fsm_debug_register : std_logic_vector(2 downto 0); + + type SYNC_MACHINE is (FIRST_DUMMY_STATE, START_COUNTER, RESYNC0, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, WAIT_3, NORMAL_OPERATION_1, NORMAL_OPERATION_2); + signal SYNC_CURRENT, SYNC_NEXT : SYNC_MACHINE; + attribute syn_enum_encoding : string; + attribute syn_enum_encoding of SYNC_MACHINE : type is "safe"; + attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential"; + + signal fsm_debug_register : std_logic_vector(3 downto 0); signal resync_counter_up :std_logic; signal resync_counter_clr :std_logic; signal resync_counter : std_logic_vector(31 downto 0); @@ -105,7 +131,7 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is signal fifo_rd_cnt : std_logic_vector(15 downto 0); signal fifo_wr_cnt : std_logic_vector(15 downto 0); signal not_fifo_empty : std_logic; - signal fifo_rd_en_dv : std_logic; + ----------------------------------------------------------------------------- -- fifo to optical link ----------------------------------------------------------------------------- @@ -123,21 +149,100 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is signal tx_k_i : std_logic; signal fifo_opt_empty_synch_synch : std_logic; signal fifo_rd_en_hub : std_logic; + constant SYSTEM : Integer := 1; + signal wait_for_write_up : std_logic; + signal wait_for_write_counter : std_logic_vector(28 downto 0); + signal link_reset_counter : std_logic_vector(2 downto 0); + signal link_reset_counter_clr : std_logic; + signal link_reset_counter_up : std_logic; + signal link_reset_out : std_logic; + signal med_error_out_i : std_logic_vector(2 downto 0); + signal fifo_rst_fsm : std_logic; + signal fsm_debug_register_fsm: std_logic_vector(3 downto 0); + signal rx_rst_fsm : std_logic; + signal resync_counter_up_fsm : std_logic; + signal resync_counter_clr_fsm : std_logic; + signal wait_for_write_up_fsm : std_logic; + signal MED_READ_OUT_fsm : std_logic; + signal diod_counter : std_logic_vector(28 downto 0); + signal cv_counter_reset : std_logic; + signal rx_comma : std_logic_vector(1 downto 0); + signal rx_comma_synch : std_logic_vector(1 downto 0); begin - SEND_ERROR: process (SYSTEM_CLK, RESET,SYNCH_CURRENT) + + --reset from link + RESET_FROM_LINK: process (RX_CLK, RESET) + begin + if rising_edge(RX_CLK) then + if RESET = '1' then + link_reset_counter_up <= '0'; + elsif rxd_synch_i = x"ffff" and link_reset_counter < 5 then + link_reset_counter_up <= '1'; + else + link_reset_counter_up <= '0'; + end if; + end if; + end process RESET_FROM_LINK; + + SET_RESET: process (SYSTEM_CLK, RESET) + begin + if rising_edge(SYSTEM_CLK) then + if RESET = '1' then + link_reset_out <= '0'; + elsif link_reset_counter = 5 then + link_reset_out <= '1'; + else + link_reset_out <= '0'; + end if; + end if; + end process SET_RESET; + + RESET_LINK_ERROR_COUNTER: process (RX_CLK, RESET) + begin + if rising_edge(RX_CLK) then + if RESET = '1' then + link_reset_counter_clr <= '0'; + elsif link_reset_counter = 3 then + link_reset_counter_clr <= link_reset_out or RESET; + elsif link_reset_counter < 3 and rxd_synch_i /= x"ffff" then + link_reset_counter_clr <= '1'; + else + link_reset_counter_clr <= '0'; + end if; + end if; + end process RESET_LINK_ERROR_COUNTER; + + LINK_RESET_COUNTER: up_down_counter + generic map ( + NUMBER_OF_BITS => 3) + port map ( + CLK => RX_CLK, + RESET => link_reset_counter_clr, + COUNT_OUT => link_reset_counter, + UP_IN => link_reset_counter_up, + DOWN_IN => '0'); + + -- STAT_OP(15) <= link_reset_out; + --link + + MED_STAT_OP(2 downto 0) <= med_error_out_i; + SEND_ERROR: process (SYSTEM_CLK, RESET,SYNC_CURRENT) begin if rising_edge(SYSTEM_CLK) then if RESET = '1' then - MED_ERROR_OUT <= ERROR_NC; - elsif SYNCH_CURRENT = NORMAL_OPERATION_1 or SYNCH_CURRENT = NORMAL_OPERATION_2 then - MED_ERROR_OUT <= ERROR_OK; - elsif SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2 then - MED_ERROR_OUT <= ERROR_WAIT; + med_error_out_i <= ERROR_NC; + elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then + med_error_out_i <= ERROR_OK; + elsif SYNC_CURRENT = WAIT_1 or SYNC_CURRENT = WAIT_2 then + med_error_out_i <= ERROR_WAIT; else - MED_ERROR_OUT <= ERROR_NC; + med_error_out_i <= ERROR_NC; end if; end if; end process SEND_ERROR; + MED_STAT_OP(15 downto 10) <= (others => '0'); + MED_STAT_OP(8 downto 3) <= (others => '0'); + PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en) begin if rising_edge(SYSTEM_CLK) then @@ -153,32 +258,37 @@ begin end if; end process PACKET_NUM; MED_PACKET_NUM_OUT <= packet_number; + LINK_STATUS : process (SYSTEM_CLK,RESET) begin if rising_edge(SYSTEM_CLK) then if RESET = '1' then RX_RST <= '0'; - FLEXI_PCS_STATUS(15 downto 0) <= (others => '0'); + LINK_DEBUG(15 downto 0) <= (others => '0'); else RX_RST <= rx_rst_i; - FLEXI_PCS_STATUS(2 downto 0) <= fsm_debug_register; - FLEXI_PCS_STATUS(7 downto 3) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full & DATA_VALID_IN;--fifo_almost_full & + LINK_DEBUG(3 downto 0) <= fsm_debug_register_fsm; + LINK_DEBUG(7 downto 4) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full;--fifo_almost_full & --'0'; - FLEXI_PCS_STATUS(15 downto 8) <= fifo_rd_cnt(7 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); --- FLEXI_PCS_STATUS(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); + LINK_DEBUG(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); -- LINK_DEBUG(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); + LINK_DEBUG(31 downto 16) <= fifo_data_in(7 downto 0) & rx_k_synch_i & resync_counter_clr & RESET & CV & resync_counter(0) & MEDIA_STATUS(0) ; end if; end if; end process LINK_STATUS; + -- LINK_DEBUG(31 downto 16) <= fifo_data_in(15 downto 0); + ----------------------------------------------------------------------------- -- data from hub to link ----------------------------------------------------------------------------- - data_opt_in <= "00" & TXD; - CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR - port map ( + + data_opt_in <= "00" & MED_DATA_IN; + SYSTEM_SCM_MEMa: if SYSTEM=1 generate + CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR + port map ( Data => data_opt_in, WrClock => SYSTEM_CLK, RdClock => TX_CLK, - WrEn => DATA_VALID_IN, + WrEn => MED_DATAREADY_IN, RdEn => fifo_opt_not_empty, Reset => fifo_rst, RPReset => fifo_rst, @@ -188,45 +298,84 @@ begin AlmostEmpty => fifo_opt_almost_empty, AlmostFull => fifo_opt_almost_full ); - DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch) - begin - if rising_edge(TX_CLK) then --falling ??? - if RESET = '1' then - tx_k_i <= '0'; - txd_synch_i <= (others => '0'); - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then - tx_k_i <= '0'; - txd_synch_i <= txd_fifo_out(15 downto 0); - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - else - tx_k_i <= '1'; - txd_synch_i <= x"c5bc"; - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - end if; + end generate SYSTEM_SCM_MEMa; + + SYSTEM_ECP2_MEMa: if SYSTEM=2 generate + CHANNEL_FIFO_TO_OPT: ecp2m_link_fifo + port map ( + Data => data_opt_in, + WrClock => SYSTEM_CLK, + RdClock => TX_CLK, + WrEn => MED_DATAREADY_IN, + RdEn => fifo_opt_not_empty, + Reset => fifo_rst, + RPReset => fifo_rst, + Q => txd_fifo_out, + Empty => fifo_opt_empty, + Full => fifo_opt_full, + AlmostEmpty => fifo_opt_almost_empty, + AlmostFull => fifo_opt_almost_full + ); + end generate SYSTEM_ECP2_MEMa; + + DATA_SEND_TO_LINK: process (TX_CLK, RESET, MED_DATAREADY_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch) + begin + if rising_edge(TX_CLK) then + if RESET = '1' then + tx_k_i <= '0'; + txd_synch_i <= (others => '0'); + fifo_opt_empty_synch <= fifo_opt_empty; + fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; + fifo_opt_not_empty <= not fifo_opt_empty; + elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then + tx_k_i <= '0'; + txd_synch_i <= txd_fifo_out(15 downto 0); + fifo_opt_empty_synch <= fifo_opt_empty; + fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; + fifo_opt_not_empty <= not fifo_opt_empty; + else + tx_k_i <= '1'; + txd_synch_i <= x"c5bc"; + fifo_opt_empty_synch <= fifo_opt_empty; + fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; + fifo_opt_not_empty <= not fifo_opt_empty; end if; - end process DATA_SEND_TO_LINK; - SYNCH_DATA: process (TX_CLK) + end if; + end process DATA_SEND_TO_LINK; + + SYNC_DATA : process (TX_CLK) begin if rising_edge(TX_CLK) then - TXD_SYNCH <= txd_synch_i; + TXD <= txd_synch_i; TX_K(0) <= tx_k_i; TX_K(1) <= '0'; end if; - end process SYNCH_DATA; --- TX_FORCE_DISP(1) <= '0'; + end process SYNC_DATA; + ----------------------------------------------------------------------------- -- from link to hub ----------------------------------------------------------------------------- + SYSTEM_SCM_MEMb: if SYSTEM=1 generate + CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR + port map ( + Data => fifo_data_in, + WrClock => RX_CLK, + RdClock => SYSTEM_CLK, + WrEn => fifo_wr_en, + RdEn => fifo_rd_en, + Reset => fifo_rst, + RPReset => fifo_rst, + Q => fifo_data_out, + Empty => fifo_empty, + Full => fifo_full, + AlmostEmpty => fifo_almost_empty, + AlmostFull => fifo_almost_full + ); + end generate SYSTEM_SCM_MEMb; - CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR - port map ( + SYSTEM_ECP2_MEMb: if SYSTEM=2 generate + CHANNEL_FIFO_TO_FPGA: ecp2m_link_fifo + port map ( Data => fifo_data_in, WrClock => RX_CLK, RdClock => SYSTEM_CLK, @@ -240,6 +389,8 @@ begin AlmostEmpty => fifo_almost_empty, AlmostFull => fifo_almost_full ); + end generate SYSTEM_ECP2_MEMb; + not_fifo_empty <= not fifo_empty; RD_FIFO_PULSE: edge_to_pulse port map ( @@ -247,6 +398,7 @@ begin en_clk => '1', signal_in => not_fifo_empty, pulse => fifo_rd_pulse); + READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i) begin if rising_edge(SYSTEM_CLK) then @@ -265,10 +417,11 @@ begin end if; end if; end process READING_THE_FIFO; - DATA_VALID_OUT <= data_valid_out_i; + + MED_DATAREADY_OUT <= data_valid_out_i; fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse; - RXD_SYNCH <= fifo_data_out(15 downto 0); --- DATA_VALID_OUT <= fifo_data_out(16) and (not fifo_empty); + MED_DATA_OUT <= fifo_data_out(15 downto 0); + VALID_DATA_SEND_TO_API: process (RX_CLK, RESET) begin if rising_edge(RX_CLK) then @@ -277,7 +430,7 @@ begin rxd_synch_synch_i <= rxd_synch_i; rx_k_synch_i <= "00"; rx_k_synch_synch_i <= rx_k_synch_i; - else-- RX_K(0) = '1' then + else rxd_synch_i <= RXD; rxd_synch_synch_i <= rxd_synch_i; rx_k_synch_i <= RX_K; @@ -285,189 +438,267 @@ begin end if; end if; end process VALID_DATA_SEND_TO_API; - SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNCH_CURRENT) + + + + SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNC_CURRENT) begin if rising_edge(RX_CLK) then if RESET = '1' then fifo_data_in <= (others => '0'); - elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then + elsif SYNC_CURRENT = NORMAL_OPERATION_2 then fifo_data_in <= '0' & (not RX_K(0)) & RXD; - elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then - fifo_data_in <= '0' & (not RX_K(1)) & rxd_synch_i(7 downto 0) & RXD(15 downto 8); + fifo_wr_en <= not RX_K(0); + elsif SYNC_CURRENT = NORMAL_OPERATION_1 then + fifo_data_in <= '0' & (not RX_K(1)) & RXD(7 downto 0) & rxd_synch_i(15 downto 8); + fifo_wr_en <= not RX_K(1); else fifo_data_in <= (others => '0'); + fifo_wr_en <= '0'; end if; end if; end process SHIFT_OR_NOT_DATA_IN; --- SYNCH_CLOCK : process (RX_CLK, RESET) - SYNCH_CLOCK : process (SYSTEM_CLK, RESET) + SAVE_COMA: process (RX_CLK, RESET) + begin + if rising_edge(RX_CLK) then + if RESET = '1' then + rx_comma <= "00"; + elsif (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' and cv_i = "00" then + rx_comma <= "01"; + elsif (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' and cv_i = "00" then + rx_comma <= "10"; + elsif cv_i /= "00" then + rx_comma <= "11"; + else + rx_comma <= "00"; + end if; + end if; + end process SAVE_COMA; + + SYNC_CLOCK : process (SYSTEM_CLK, RESET) begin if rising_edge (SYSTEM_CLK) then - if RESET = '1' then - SYNCH_CURRENT <= IDLE; --NORMAL_OPERATION_2;--IDLE; --sim - cv_i <= (others => '0'); + if RESET = '1' then + SYNC_CURRENT <= FIRST_DUMMY_STATE;--no_sim -- +--sim-- SYNC_CURRENT <= NORMAL_OPERATION_2; + cv_i <= (others => '0'); + fifo_rst <= '1'; + fsm_debug_register <= "1111"; + rx_rst_i <= '0'; + resync_counter_up <= '0'; + resync_counter_clr <= '1'; + wait_for_write_up <= '0'; + MED_READ_OUT <= '0'; + rx_comma_synch <= "00"; else - SYNCH_CURRENT <= SYNCH_NEXT; - cv_i <= CV; + SYNC_CURRENT <= SYNC_NEXT; + cv_i <= CV; + fifo_rst <= fifo_rst_fsm; + fsm_debug_register <= fsm_debug_register_fsm; + rx_rst_i <= rx_rst_fsm; + resync_counter_up <= resync_counter_up_fsm; + resync_counter_clr <= resync_counter_clr_fsm; + wait_for_write_up <= wait_for_write_up_fsm; + MED_READ_OUT <= MED_READ_OUT_fsm; + rx_comma_synch <= rx_comma; end if; end if; - end process SYNCH_CLOCK; - SYNCH_FSM : process( SYNCH_CURRENT, rxd_synch_i, resync_counter, cv_i,RX_K, MED_READ_IN ,fifo_rd_pulse, fifo_rd_en_hub,rx_k_synch_i) + end process SYNC_CLOCK; + + SYNC_FSM : process(SYNC_CURRENT) begin - case (SYNCH_CURRENT) is - when IDLE => - fifo_rst <= '1'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "001"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; --- if rxd_synch_i = x"bc50" then --- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;--WAIT_1; - --els - if rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc" then - SYNCH_NEXT <= WAIT_2;--NORMAL_OPERATION_2; --WAIT_2; + fifo_rst_fsm <= '0'; + fsm_debug_register_fsm <= "1111"; + rx_rst_fsm <= '0'; + resync_counter_up_fsm <= '1'; + resync_counter_clr_fsm <= '0'; + wait_for_write_up_fsm <= '0'; + MED_READ_OUT_fsm <= '0'; + SYNC_NEXT <= RESYNC0; + + case (SYNC_CURRENT) is + --check the sfp, pll lock and so on + -- all counters are are only reset in state START_COUNTER + + when FIRST_DUMMY_STATE => + resync_counter_up_fsm <= '0'; + fsm_debug_register_fsm <= "0001"; + SYNC_NEXT <= START_COUNTER; + + when START_COUNTER => + fsm_debug_register_fsm <= "0010"; + resync_counter_up_fsm <= '0'; + resync_counter_clr_fsm <= '1'; + fifo_rst_fsm <= '1'; + SYNC_NEXT <= RESYNC0; + + when RESYNC0 => + fsm_debug_register_fsm <= "0011"; + resync_counter_up_fsm <= '0'; + if MEDIA_STATUS(0) = '1' then + SYNC_NEXT <= START_COUNTER; + elsif rx_comma_synch = "01" or rx_comma_synch = "10" then + SYNC_NEXT <= WAIT_1; else - SYNCH_NEXT <= RESYNC1; + SYNC_NEXT <= RESYNC1; end if; + --SYNC_NEXT <= RESYNC1; + when RESYNC1 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '1'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(8) = '1' then - SYNCH_NEXT <= RESYNC2; + fsm_debug_register_fsm <= "0100"; + rx_rst_fsm <= '1'; + if resync_counter(9) = '1' then + SYNC_NEXT <= RESYNC2; else - SYNCH_NEXT <= RESYNC1; + SYNC_NEXT <= RESYNC1; end if; - when RESYNC2 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '0'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(16) = '1' then --at least 400us - SYNCH_NEXT <= RESYNC3; + + when RESYNC2 => -- just waiting + fsm_debug_register_fsm <= "0101"; + if resync_counter(18) = '1' then --at least 400us + SYNC_NEXT <= RESYNC3; else - SYNCH_NEXT <= RESYNC2; + SYNC_NEXT <= RESYNC2; end if; - - when RESYNC3 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; --- if rxd_synch_i = x"bc50" and rx_k_synch_i(1) = '1' then --- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1; - --els - if (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then - SYNCH_NEXT <= WAIT_2;--NORMAL_OPERATION_2; + + when RESYNC3 => -- check for comma + fsm_debug_register_fsm <= "0110"; + if rx_comma_synch = "01" or rx_comma_synch = "10" then + SYNC_NEXT <= WAIT_2;--no_sim-- +--sim-- SYNC_NEXT <= NORMAL_OPERATION_2; else - SYNCH_NEXT <= IDLE; + SYNC_NEXT <= START_COUNTER; end if; - when WAIT_1 => - fifo_rst <= '0'; - rx_rst_i <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "011"; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(27) = '1' and (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' then - SYNCH_NEXT <= NORMAL_OPERATION_1; - elsif resync_counter(26) = '1' and (rxd_synch_i /= x"bc50" or rx_k_synch_i(1) = '0') then - SYNCH_NEXT <= RESYNC1; + + when WAIT_1 => -- wait for comma + fsm_debug_register_fsm <= "0111"; + if resync_counter(28) = '1' then + SYNC_NEXT <= WAIT_3; + elsif resync_counter(27) = '1' and (rx_comma_synch = "00" or rx_comma_synch = "11") then + SYNC_NEXT <= START_COUNTER; else - SYNCH_NEXT <= WAIT_1; + SYNC_NEXT <= WAIT_1; end if; - when WAIT_2 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - rx_rst_i <= '0'; - fsm_debug_register(2 downto 0) <= "011"; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(27) = '1' and (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then - SYNCH_NEXT <= NORMAL_OPERATION_2; - elsif resync_counter(26) = '1' and (rxd_synch_i(7 downto 0) /= x"bc" or rx_k_synch_i(0) = '0') then - SYNCH_NEXT <= RESYNC1; + + when WAIT_3 => + fsm_debug_register_fsm <= "1001"; + wait_for_write_up_fsm <= '1'; + if wait_for_write_counter(28)='1' and rx_comma_synch = "01" then + SYNC_NEXT <= NORMAL_OPERATION_2; + elsif wait_for_write_counter(28)='1' and rx_comma_synch = "10" then + SYNC_NEXT <= NORMAL_OPERATION_1; else - SYNCH_NEXT <= WAIT_2; + SYNC_NEXT <= WAIT_3; end if; + when NORMAL_OPERATION_1 => - fifo_rst <= '0'; - fifo_wr_en <= not rx_k_synch_i(1); - fsm_debug_register(2 downto 0) <= "110"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - if cv_i(0) = '1' or cv_i(1) = '1' then - SYNCH_NEXT <= IDLE; +--sim-- fifo_rst <=RESET; + fsm_debug_register_fsm <= "1010"; + resync_counter_up_fsm <= '0'; + MED_READ_OUT_fsm <= '1'; + if rx_comma_synch = "11" then + SYNC_NEXT <= START_COUNTER; else - SYNCH_NEXT <= NORMAL_OPERATION_1; + SYNC_NEXT <= NORMAL_OPERATION_1; end if; + when NORMAL_OPERATION_2 => - fifo_rst <='0';--RESET;--'0';sim - fifo_wr_en <= not rx_k_synch_i(0); - fsm_debug_register(2 downto 0) <= "111"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - if cv_i(0) = '1' or cv_i(1) = '1' then - SYNCH_NEXT <= IDLE; - else - SYNCH_NEXT <= NORMAL_OPERATION_2; - end if; +--sim-- fifo_rst <=RESET; + fsm_debug_register_fsm <= "1011"; + resync_counter_up_fsm <= '0'; + MED_READ_OUT_fsm <= '1'; + if rx_comma_synch = "11" then + SYNC_NEXT <= START_COUNTER; + else + SYNC_NEXT <= NORMAL_OPERATION_2; + end if; + + when others => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - fsm_debug_register(2 downto 0) <= "000"; - rx_rst_i <= '0'; - SYNCH_NEXT <= IDLE; + fsm_debug_register_fsm <= "0000"; + SYNC_NEXT <= START_COUNTER; + end case; - end process SYNCH_FSM; + end process SYNC_FSM; - RESYNC_COUNTER_INST : simpleupcounter_32bit + LED_FOR_LINK: process (SYSTEM_CLK) + begin + if rising_edge(SYSTEM_CLK) then + if RESET = '1' then + MED_STAT_OP(9) <= '1'; + elsif fsm_debug_register < 9 then + MED_STAT_OP(9) <= diod_counter(23); + elsif fsm_debug_register = 9 then + MED_STAT_OP(9) <= diod_counter(26); + elsif fsm_debug_register > 9 then + MED_STAT_OP(9) <= '0'; + else + MED_STAT_OP(9) <= '1'; + end if; + end if; + end process LED_FOR_LINK; + + DIOD_COUNTER_INST: up_down_counter + generic map ( + NUMBER_OF_BITS => 29) + port map ( + CLK => SYSTEM_CLK, + RESET => '0', + COUNT_OUT => diod_counter, + UP_IN => '1', + DOWN_IN => '0'); + + WAIT_FOR_SENDING: up_down_counter + generic map ( + NUMBER_OF_BITS => 29) port map ( - QOUT => resync_counter, - UP => resync_counter_up, - CLK => SYSTEM_CLK, - CLR => resync_counter_clr); + CLK => SYSTEM_CLK, + RESET => resync_counter_clr, + COUNT_OUT => wait_for_write_counter, + UP_IN => wait_for_write_up, + DOWN_IN => '0'); + + RESYNC_COUNTER: up_down_counter + generic map ( + NUMBER_OF_BITS => 32) + port map ( + CLK => SYSTEM_CLK, + RESET => resync_counter_clr, + COUNT_OUT => resync_counter, + UP_IN => resync_counter_up, + DOWN_IN => '0'); + cv_or <= cv_i(0) or cv_i(1); - CV_COUNTER_INST: simpleupcounter_16bit + CV_COUNTER: up_down_counter + generic map ( + NUMBER_OF_BITS => 16) port map ( - QOUT => cv_counter, - UP => cv_or, - CLK => RX_CLK, - CLR => RESET); - WR_COUNTER_INST: simpleupcounter_16bit + CLK => RX_CLK, + RESET => RESET, + COUNT_OUT => cv_counter, + UP_IN => cv_or, + DOWN_IN => '0'); + + WRITE_COUNTER: up_down_counter + generic map ( + NUMBER_OF_BITS => 16) port map ( - QOUT => fifo_wr_cnt, - UP => fifo_wr_en, - CLK => SYSTEM_CLK, - CLR => RESET); - fifo_rd_en_dv <= fifo_rd_en and fifo_data_out(16) and fifo_empty; - RD_COUNTER_INST: simpleupcounter_16bit + CLK => SYSTEM_CLK, + RESET => RESET, + COUNT_OUT => fifo_wr_cnt, + UP_IN => fifo_wr_en, + DOWN_IN => '0'); + + READ_COUNTER: up_down_counter + generic map ( + NUMBER_OF_BITS => 16) port map ( - QOUT => fifo_rd_cnt, - UP => DATA_VALID_IN,--fifo_rd_en_dv,--fifo_rd_en, - CLK => SYSTEM_CLK, - CLR => RESET); + CLK => SYSTEM_CLK, + RESET => RESET, + COUNT_OUT => fifo_rd_cnt, + UP_IN => MED_DATAREADY_IN, + DOWN_IN => '0'); + end flexi_PCS_channel_synch; ---reciving idle for 1ms and start e11o until recive e11o and idle ---write to fifo when rx_k is 1 ? --- wait for reset --- wait for pll locked --- send idles --- wait 650ms (counter(27) = 1) --- enable rx --- wait 650ms (counter(27) = 1) --- enable tx --- ready + diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd index cf80c15..5dd12e3 100644 --- a/optical_link/flexi_PCS_synch.vhd +++ b/optical_link/flexi_PCS_synch.vhd @@ -1,5 +1,6 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ieee; library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -8,82 +9,96 @@ use work.trb_net_std.all; entity flexi_PCS_synch is generic ( - HOW_MANY_CHANNELS : positive); + HOW_MANY_CHANNELS : positive); port ( - SYSTEM_CLK : in std_logic; - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0) + RESET : in std_logic; + SYSTEM_CLK : in std_logic; + TX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); + RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); + RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + TXD : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); + TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + MEDIA_STATUS : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MEDIA_CONTROL : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); + MED_STAT_OP : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_CTRL_OP : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + LINK_DEBUG : out std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0) ); end flexi_PCS_synch; + architecture flexi_PCS_synch of flexi_PCS_synch is + component flexi_PCS_channel_synch port ( - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0); + RESET : in std_logic; + SYSTEM_CLK : in std_logic; + TX_CLK : in std_logic; + RX_CLK : in std_logic; + RXD : in std_logic_vector(15 downto 0); + RX_K : in std_logic_vector(1 downto 0); + RX_RST : out std_logic; + CV : in std_logic_vector(1 downto 0); + TXD : out std_logic_vector(15 downto 0); + TX_K : out std_logic_vector(1 downto 0); + MEDIA_STATUS : in std_logic_vector(15 downto 0); + MEDIA_CONTROL : out std_logic_vector(15 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector(15 downto 0); + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(2 downto 0); - MED_READ_IN : in std_logic + MED_STAT_OP : out std_logic_vector(15 downto 0); + MED_CTRL_OP : in std_logic_vector(15 downto 0); + LINK_DEBUG : out std_logic_vector(31 downto 0) ); end component; - signal med_error : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); + begin + CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate begin - MED_READ_OUT <= (others => '1'); - MED_STAT_OP(bit_index*16+15 downto bit_index*16) <= "0000000000000" & med_error((bit_index*3+2) downto bit_index*3); - - SYNCH :flexi_PCS_channel_synch + CHANNEL_GENERATE: flexi_PCS_channel_synch port map ( - SYSTEM_CLK => SYSTEM_CLK, - TX_CLK => CLK(bit_index/4), --4 different channles clk - RX_CLK => RX_CLK(bit_index), - RESET => RESET, - RXD => RXD((bit_index*16+15) downto bit_index*16), - RXD_SYNCH => MED_DATA_OUT((bit_index*16+15) downto bit_index*16), - RX_K => RX_K(bit_index*2+1 downto bit_index*2), - RX_RST => RX_RST(bit_index), - CV => CV((bit_index*2+1) downto bit_index*2), - TXD => MED_DATA_IN((bit_index*16+15) downto bit_index*16), - TXD_SYNCH => TXD_SYNCH((bit_index*16+15) downto bit_index*16), - TX_K => TX_K(bit_index*2+1 downto bit_index*2), - DATA_VALID_IN => MED_DATAREADY_IN(bit_index), - DATA_VALID_OUT => MED_DATAREADY_OUT(bit_index), - FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH), - MED_ERROR_OUT => med_error((bit_index*3+2) downto bit_index*3), - MED_READ_IN => MED_READ_IN(bit_index) - ); + RESET => RESET, + SYSTEM_CLK => SYSTEM_CLK, + TX_CLK => TX_CLK(bit_index/4), --4 different channles clk, + RX_CLK => RX_CLK(bit_index), + RXD => RXD((bit_index*16+15) downto bit_index*16), + RX_K => RX_K(bit_index*2+1 downto bit_index*2), + RX_RST => RX_RST(bit_index), + CV => CV((bit_index*2+1) downto bit_index*2), + TXD => TXD((bit_index*16+15) downto bit_index*16), + TX_K => TX_K(bit_index*2+1 downto bit_index*2), + MEDIA_STATUS => MEDIA_STATUS((bit_index*16+15) downto bit_index*16), + MEDIA_CONTROL => MEDIA_CONTROL((bit_index*16+15) downto bit_index*16), + MED_DATAREADY_IN => MED_DATAREADY_IN(bit_index), + MED_DATA_IN => MED_DATA_IN((bit_index*16+15) downto bit_index*16), + MED_READ_OUT => MED_READ_OUT(bit_index), + MED_DATA_OUT => MED_DATA_OUT((bit_index*16+15) downto bit_index*16), + MED_DATAREADY_OUT => MED_DATAREADY_OUT(bit_index), + MED_READ_IN => MED_READ_IN(bit_index), + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH), + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH), + MED_STAT_OP => MED_STAT_OP((bit_index*16+15) downto bit_index*16), + MED_CTRL_OP => MED_CTRL_OP((bit_index*16+15) downto bit_index*16), + LINK_DEBUG => LINK_DEBUG((bit_index*32+31) downto bit_index*32) + ); + end generate; -end architecture; + +end flexi_PCS_synch; diff --git a/optical_link/hub.lpf b/optical_link/hub.lpf index 011b5ae..ebb3bd4 100644 --- a/optical_link/hub.lpf +++ b/optical_link/hub.lpf @@ -173,21 +173,36 @@ IOBUF PORT "DWAIT" IO_TYPE=LVTTL33 ; #LOCATE COMP "FS_PE_0" SITE "J13" ; #LOCATE COMP "FS_PE_1" SITE "K9" ; #LOCATE COMP "FS_PE_2" SITE "J12" ; -#LOCATE COMP "FS_PE_5" SITE "AM16" ; -#LOCATE COMP "FS_PE_6" SITE "AL16" ; -#LOCATE COMP "FS_PE_7" SITE "AM15" ; -#LOCATE COMP "FS_PE_8" SITE "AL15" ; -#LOCATE COMP "FS_PE_9" SITE "AM14" ; -#LOCATE COMP "FS_PE_10" SITE "AC16" ; + +LOCATE COMP "FS_PE_5" SITE "AM16" ; +LOCATE COMP "FS_PE_6" SITE "AL16" ; +LOCATE COMP "FS_PE_7" SITE "AM15" ; +LOCATE COMP "FS_PE_8" SITE "AL15" ; +LOCATE COMP "FS_PE_9" SITE "AM14" ; +LOCATE COMP "FS_PE_10" SITE "AC16" ; +LOCATE COMP "FS_PE_12" SITE "AK15" ; +LOCATE COMP "FS_PE_13" SITE "AH14" ; +LOCATE COMP "FS_PE_14" SITE "AM13" ; +LOCATE COMP "FS_PE_15" SITE "AH12" ; +LOCATE COMP "FS_PE_16" SITE "AK14" ; +LOCATE COMP "FS_PE_17" SITE "AD15" ; + +IOBUF PORT "FS_PE_5" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_6" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_7" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_8" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_9" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_10" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_12" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_13" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_14" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_15" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_16" IO_TYPE=LVTTL33; +IOBUF PORT "FS_PE_17" IO_TYPE=LVTTL33; LOCATE COMP "FS_PE_11" SITE "AH16" ; IOBUF PORT "FS_PE_11" IO_TYPE=LVTTL33 ; -#LOCATE COMP "FS_PE_12" SITE "AK15" ; -#LOCATE COMP "FS_PE_13" SITE "AH14" ; -#LOCATE COMP "FS_PE_14" SITE "AM13" ; -#LOCATE COMP "FS_PE_15" SITE "AH12" ; -#LOCATE COMP "FS_PE_16" SITE "AK14" ; -#LOCATE COMP "FS_PE_17" SITE "AD15" ; + LOCATE COMP "OPLL" SITE "AL11" ; LOCATE COMP "IPLL" SITE "AL10" ; @@ -229,7 +244,7 @@ LOCATE COMP "LVDS_CLK_200P" SITE "P3" ; #LOCATE COMP "LVDS_CLK_200N" SITE "P4" ; IOBUF PORT "LVDS_CLK_200P" IO_TYPE=LVDS ; #IOBUF PORT "LVDS_CLK_200N" IO_TYPE=LVDS ; -FREQUENCY PORT "LVDS_CLK_200P" 100.000000 MHz ; +FREQUENCY PORT "LVDS_CLK_200P" 110.000000 MHz ; #FREQUENCY PORT "LVDS_CLK_200N" 200.000000 MHz ; IOBUF PORT "LVDS_CLK_200P" DIFFRESISTOR=120 ; @@ -266,11 +281,15 @@ IOBUF PORT "RT_13" IO_TYPE=LVTTL33 ; IOBUF PORT "RT_14" IO_TYPE=LVTTL33 ; IOBUF PORT "RT_15" IO_TYPE=LVTTL33 ; IOBUF PORT "RT_16" IO_TYPE=LVTTL33 ; + + + + #LOCATE COMP "GBIT_INP_N" SITE "C2" ; #LOCATE COMP "GBIT_INP_P" SITE "C1" ; #LOCATE COMP "GBIT_OUT_N" SITE "B3" ; #LOCATE COMP "GBIT_OUT_P" SITE "A3" ; -#LOCATE COMP "GBIT_SFP_LOS" SITE "J15" ; + #LOCATE COMP "GBIT_SFP_MOD_0" SITE "A19" ; #LOCATE COMP "GBIT_SFP_MOD_1" SITE "H18" ; #LOCATE COMP "GBIT_SFP_MOD_2" SITE "H17" ; @@ -279,14 +298,14 @@ IOBUF PORT "RT_16" IO_TYPE=LVTTL33 ; #LOCATE COMP "S1_GBIT_SFP_MOD_0" SITE "AG17" ; #LOCATE COMP "S1_GBIT_TX_FAULT" SITE "AK21" ; #LOCATE COMP "S2_GBIT_TX_DIS" SITE "AF19" ; -#LOCATE COMP "S2_GBIT_SFP_LOS" SITE "AM22" ; + #LOCATE COMP "S2_GBIT_SFP_MOD_0" SITE "AC17" ; -#LOCATE COMP "S3_GBIT_SFP_LOS" SITE "AL21" ; + #LOCATE COMP "S2_GBIT_TX_FAULT" SITE "AM23" ; #LOCATE COMP "S3_GBIT_SFP_MOD_0" SITE "AM17" ; #LOCATE COMP "S3_GBIT_TX_FAULT" SITE "AH26" ; #LOCATE COMP "S3_GBIT_TX_DIS" SITE "AH25" ; -#LOCATE COMP "S1_GBIT_SFP_LOS" SITE "AE19" ; + #LOCATE COMP "S1_GBIT_TX_DIS" SITE "AJ21" ; #LOCATE COMP "S1_GBIT_SFP_MOD_1" SITE "AL18" ; #LOCATE COMP "S3_GBIT_SFP_MOD_1" SITE "AE17" ; @@ -374,31 +393,46 @@ IOBUF PORT "RT_16" IO_TYPE=LVTTL33 ; #IOBUF PORT "SFP12_MOD_2" IO_TYPE=LVTTL33 ; #IOBUF PORT "SFP11_MOD_2" IO_TYPE=LVTTL33 ; +#LOCATE COMP "GBIT_SFP_LOS" SITE "J15" ; +#LOCATE COMP "S2_GBIT_SFP_LOS" SITE "AM22" ; +#LOCATE COMP "S3_GBIT_SFP_LOS" SITE "AL21" ; +#LOCATE COMP "S1_GBIT_SFP_LOS" SITE "AE19" ; + -#LOCATE COMP "SFP_LOS_1" SITE "A18" ; -#LOCATE COMP "SFP_LOS_2" SITE "A15" ; -#LOCATE COMP "SFP_LOS_3" SITE "B15" ; -#LOCATE COMP "SFP_LOS_4" SITE "G16" ; -#LOCATE COMP "SFP_LOS_5" SITE "H16" ; -#LOCATE COMP "SFP_LOS_6" SITE "J16" ; -#LOCATE COMP "SFP_LOS_7" SITE "L13" ; -#LOCATE COMP "SFP_LOS_8" SITE "C14" ; -#LOCATE COMP "SFP_LOS_9" SITE "E15" ; -#LOCATE COMP "SFP_LOS_10" SITE "G14" ; -#LOCATE COMP "SFP_LOS_11" SITE "E14" ; -#LOCATE COMP "SFP_LOS_12" SITE "F13" ; -#IOBUF PORT "SFP_LOS_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_3" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_4" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_5" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_6" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_7" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_8" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_9" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_10" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_11" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_12" IO_TYPE=LVTTL33 ; + +LOCATE COMP "SFP_LOS_1" SITE "A18" ; +LOCATE COMP "SFP_LOS_2" SITE "A15" ; +LOCATE COMP "SFP_LOS_3" SITE "B15" ; +LOCATE COMP "SFP_LOS_4" SITE "G16" ; +LOCATE COMP "SFP_LOS_5" SITE "H16" ; +LOCATE COMP "SFP_LOS_6" SITE "J16" ; +LOCATE COMP "SFP_LOS_7" SITE "L13" ; +LOCATE COMP "SFP_LOS_8" SITE "C14" ; +LOCATE COMP "SFP_LOS_9" SITE "E15" ; +LOCATE COMP "SFP_LOS_10" SITE "G14" ; +LOCATE COMP "SFP_LOS_11" SITE "E14" ; +LOCATE COMP "SFP_LOS_12" SITE "F13" ; +LOCATE COMP "SFP_LOS_13" SITE "J15" ; +LOCATE COMP "SFP_LOS_14" SITE "AE19" ; +LOCATE COMP "SFP_LOS_15" SITE "AM22" ; +LOCATE COMP "SFP_LOS_16" SITE "AL21" ; + +IOBUF PORT "SFP_LOS_1" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_2" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_3" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_4" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_5" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_6" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_7" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_8" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_9" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_10" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_11" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_12" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_13" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_14" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_15" IO_TYPE=LVTTL33 ; +IOBUF PORT "SFP_LOS_16" IO_TYPE=LVTTL33 ; #LOCATE COMP "quad_a/PCSA_INST" SITE "PCS36000" ; @@ -407,7 +441,28 @@ LOCATE COMP "QUAD_GENERATE_1_QUAD/PCSA_INST" SITE "PCS36100" ; LOCATE COMP "QUAD_GENERATE_2_QUAD/PCSA_INST" SITE "PCS3E100" ; LOCATE COMP "QUAD_GENERATE_3_QUAD/PCSA_INST" SITE "PCS3E000" ; #LOCATE COMP "TEST/PCSA_INST" SITE "PCS36000" ; -FREQUENCY PORT "ref_pclk_0/QUAD_GENERATE_0_QUAD" 100.000000MHz; +FREQUENCY NET "ref_pclk_0" 100.000000MHz; +FREQUENCY NET "rx_clk_i_0" 100.000000MHz; +FREQUENCY NET "rx_clk_i_1" 100.000000MHz; +FREQUENCY NET "rx_clk_i_2" 100.000000MHz; +FREQUENCY NET "rx_clk_i_3" 100.000000MHz; +FREQUENCY NET "ref_pclk_1" 100.000000MHz; +FREQUENCY NET "rx_clk_i_4" 100.000000MHz; +FREQUENCY NET "rx_clk_i_5" 100.000000MHz; +FREQUENCY NET "rx_clk_i_6" 100.000000MHz; +FREQUENCY NET "rx_clk_i_7" 100.000000MHz; +FREQUENCY NET "ref_pclk_2" 100.000000MHz; +FREQUENCY NET "rx_clk_i_8" 100.000000MHz; +FREQUENCY NET "rx_clk_i_9" 100.000000MHz; +FREQUENCY NET "rx_clk_i_10" 100.000000MHz; +FREQUENCY NET "rx_clk_i_11" 100.000000MHz; +FREQUENCY NET "ref_pclk_3" 100.000000MHz; +FREQUENCY NET "rx_clk_i_12" 100.000000MHz; +FREQUENCY NET "rx_clk_i_13" 100.000000MHz; +FREQUENCY NET "rx_clk_i_14" 100.000000MHz; +FREQUENCY NET "rx_clk_i_15" 100.000000MHz; + + FREQUENCY PORT "ref_pclk_1/QUAD_GENERATE_1_QUAD" 100.000000MHz; FREQUENCY PORT "ref_pclk_2/QUAD_GENERATE_2_QUAD" 100.000000MHz; FREQUENCY PORT "ref_pclk_3/QUAD_GENERATE_3_QUAD" 100.000000MHz; @@ -415,8 +470,13 @@ FREQUENCY PORT "ref_pclk_3/QUAD_GENERATE_3_QUAD" 100.000000MHz; #FREQUENCY PORT "rx_1_sclk_a/quad_a" 100.000000MHz; #FREQUENCY PORT "rx_2_sclk_a/quad_a" 100.000000MHz; #FREQUENCY PORT "rx_3_sclk_a/quad_a" 100.000000MHz; - #LOCATE COMP "SUPPL_RESET" SITE "B18" ; + + + + + + LOCATE COMP "TX_DIS_1" SITE "G17" ; LOCATE COMP "TX_DIS_2" SITE "A17" ; LOCATE COMP "TX_DIS_3" SITE "A16" ; diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd index f4d6eb1..8c0bc65 100644 --- a/optical_link/hub.vhd +++ b/optical_link/hub.vhd @@ -5,8 +5,10 @@ use ieee.numeric_std.all; library work; use work.all; +use work.version.all; use work.trb_net_std.all; use work.trb_net16_hub_func.all; +use ieee.std_logic_arith.all; -- library sc; -- use sc.components.all; entity hub is @@ -14,234 +16,205 @@ entity hub is HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 4 ); port ( - LVDS_CLK_200P : in std_logic; --- LVDS_CLK_200N : in std_logic; --- SERDES_200N : in std_logic; --- SERDES_200P : in std_logic; --- ADO_LV : in std_logic_vector(61 downto 0); + LVDS_CLK_200P : in std_logic; --addon connector - ADO_TTL : inout std_logic_vector(46 downto 0); - --diode - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; + ADO_TTL : inout std_logic_vector(46 downto 0); + --diodes + DBAD : out std_logic; + DGOOD : out std_logic; + DINT : out std_logic; + DWAIT : out std_logic; + LOK : out std_logic_vector(16 downto 1); + RT : out std_logic_vector(16 downto 1); + --sfp + TX_DIS : out std_logic_vector(16 downto 1); + IPLL : out std_logic; + OPLL : out std_logic; --data to/from optical tranceivers - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); + SFP_INP_N : in std_logic_vector(15 downto 0); + SFP_INP_P : in std_logic_vector(15 downto 0); + SFP_OUT_N : out std_logic_vector(15 downto 0); + SFP_OUT_P : out std_logic_vector(15 downto 0); + --sfp + SFP_LOS : in std_logic_vector(16 downto 1); --tempsens - FS_PE_11 : inout std_logic--; + FS_PE_11 : inout std_logic; --etrax_interface - -- FS_PE : inout std_logic_vector(17 downto 5) - --------------------------------------------------------------------------- - -- sim --- --------------------------------------------------------------------------- --- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); --- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); --- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); --- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) + FS_PE : inout std_logic_vector(9 downto 8)--sim--; +--sim-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); +--sim-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); +--sim-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); +--sim-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) ); end hub; +--add all sfp connections to measure opt. power temp. sens and if there is SFP + architecture hub of hub is - component trb_hub_interface - port ( - CLK : in std_logic; - RESET : in std_logic; - STROBE : in std_logic; - INTERNAL_DATA_IN : in std_logic_vector(7 downto 0); - INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0); - INTERNAL_ADDRESS : in std_logic_vector(15 downto 0); - INTERNAL_MODE : in std_logic; - VALID_DATA_SENT : out std_logic; - hub_register_00 : in std_logic_vector(7 downto 0); - hub_register_01 : in std_logic_vector(7 downto 0); - hub_register_02 : in std_logic_vector(7 downto 0); - hub_register_03 : in std_logic_vector(7 downto 0); - hub_register_04 : in std_logic_vector(7 downto 0); - hub_register_05 : in std_logic_vector(7 downto 0); - hub_register_06 : in std_logic_vector(7 downto 0); - hub_register_07 : in std_logic_vector(7 downto 0); - hub_register_08 : in std_logic_vector(7 downto 0); - hub_register_09 : in std_logic_vector(7 downto 0); - hub_register_0a : out std_logic_vector(7 downto 0); - hub_register_0b : out std_logic_vector(7 downto 0); - hub_register_0c : out std_logic_vector(7 downto 0); - hub_register_0d : out std_logic_vector(7 downto 0); - hub_register_0e : out std_logic_vector(7 downto 0); - hub_register_0f : out std_logic_vector(7 downto 0); - hub_register_10 : in std_logic_vector(7 downto 0); - hub_register_11 : in std_logic_vector(7 downto 0); - hub_register_12 : in std_logic_vector(7 downto 0); - hub_register_13 : in std_logic_vector(7 downto 0); - hub_register_14 : in std_logic_vector(7 downto 0); - hub_register_15 : in std_logic_vector(7 downto 0); - hub_register_16 : in std_logic_vector(7 downto 0) + + component serdes_fpga_ref_clk + port( + rxrefclk : in std_logic; + refclk : in std_logic; + hdinp_0 : in std_logic; + hdinn_0 : in std_logic; + tclk_0 : in std_logic; + rclk_0 : in std_logic; + tx_rst_0 : in std_logic; + rx_rst_0 : in std_logic; + txd_0 : in std_logic_vector(15 downto 0); + tx_k_0 : in std_logic_vector(1 downto 0); + tx_force_disp_0 : in std_logic_vector(1 downto 0); + tx_disp_sel_0 : in std_logic_vector(1 downto 0); + tx_crc_init_0 : in std_logic_vector(1 downto 0); + word_align_en_0 : in std_logic; + mca_align_en_0 : in std_logic; + felb_0 : in std_logic; + lsm_en_0 : in std_logic; + hdinp_1 : in std_logic; + hdinn_1 : in std_logic; + tclk_1 : in std_logic; + rclk_1 : in std_logic; + tx_rst_1 : in std_logic; + rx_rst_1 : in std_logic; + txd_1 : in std_logic_vector(15 downto 0); + tx_k_1 : in std_logic_vector(1 downto 0); + tx_force_disp_1 : in std_logic_vector(1 downto 0); + tx_disp_sel_1 : in std_logic_vector(1 downto 0); + tx_crc_init_1 : in std_logic_vector(1 downto 0); + word_align_en_1 : in std_logic; + mca_align_en_1 : in std_logic; + felb_1 : in std_logic; + lsm_en_1 : in std_logic; + hdinp_2 : in std_logic; + hdinn_2 : in std_logic; + tclk_2 : in std_logic; + rclk_2 : in std_logic; + tx_rst_2 : in std_logic; + rx_rst_2 : in std_logic; + txd_2 : in std_logic_vector(15 downto 0); + tx_k_2 : in std_logic_vector(1 downto 0); + tx_force_disp_2 : in std_logic_vector(1 downto 0); + tx_disp_sel_2 : in std_logic_vector(1 downto 0); + tx_crc_init_2 : in std_logic_vector(1 downto 0); + word_align_en_2 : in std_logic; + mca_align_en_2 : in std_logic; + felb_2 : in std_logic; + lsm_en_2 : in std_logic; + hdinp_3 : in std_logic; + hdinn_3 : in std_logic; + tclk_3 : in std_logic; + rclk_3 : in std_logic; + tx_rst_3 : in std_logic; + rx_rst_3 : in std_logic; + txd_3 : in std_logic_vector(15 downto 0); + tx_k_3 : in std_logic_vector(1 downto 0); + tx_force_disp_3 : in std_logic_vector(1 downto 0); + tx_disp_sel_3 : in std_logic_vector(1 downto 0); + tx_crc_init_3 : in std_logic_vector(1 downto 0); + word_align_en_3 : in std_logic; + mca_align_en_3 : in std_logic; + felb_3 : in std_logic; + lsm_en_3 : in std_logic; + mca_resync_01 : in std_logic; + mca_resync_23 : in std_logic; + quad_rst : in std_logic; + serdes_rst : in std_logic; + rxa_pclk : out std_logic; + rxb_pclk : out std_logic; + hdoutp_0 : out std_logic; + hdoutn_0 : out std_logic; + ref_0_sclk : out std_logic; + rx_0_sclk : out std_logic; + rxd_0 : out std_logic_vector(15 downto 0); + rx_k_0 : out std_logic_vector(1 downto 0); + rx_disp_err_detect_0 : out std_logic_vector(1 downto 0); + rx_cv_detect_0 : out std_logic_vector(1 downto 0); + rx_crc_eop_0 : out std_logic_vector(1 downto 0); + lsm_status_0 : out std_logic; + hdoutp_1 : out std_logic; + hdoutn_1 : out std_logic; + ref_1_sclk : out std_logic; + rx_1_sclk : out std_logic; + rxd_1 : out std_logic_vector(15 downto 0); + rx_k_1 : out std_logic_vector(1 downto 0); + rx_disp_err_detect_1 : out std_logic_vector(1 downto 0); + rx_cv_detect_1 : out std_logic_vector(1 downto 0); + rx_crc_eop_1 : out std_logic_vector(1 downto 0); + lsm_status_1 : out std_logic; + hdoutp_2 : out std_logic; + hdoutn_2 : out std_logic; + ref_2_sclk : out std_logic; + rx_2_sclk : out std_logic; + rxd_2 : out std_logic_vector(15 downto 0); + rx_k_2 : out std_logic_vector(1 downto 0); + rx_disp_err_detect_2 : out std_logic_vector(1 downto 0); + rx_cv_detect_2 : out std_logic_vector(1 downto 0); + rx_crc_eop_2 : out std_logic_vector(1 downto 0); + lsm_status_2 : out std_logic; + hdoutp_3 : out std_logic; + hdoutn_3 : out std_logic; + ref_3_sclk : out std_logic; + rx_3_sclk : out std_logic; + rxd_3 : out std_logic_vector(15 downto 0); + rx_k_3 : out std_logic_vector(1 downto 0); + rx_disp_err_detect_3 : out std_logic_vector(1 downto 0); + rx_cv_detect_3 : out std_logic_vector(1 downto 0); + rx_crc_eop_3 : out std_logic_vector(1 downto 0); + lsm_status_3 : out std_logic; + mca_aligned_01 : out std_logic; + mca_inskew_01 : out std_logic; + mca_outskew_01 : out std_logic; + mca_aligned_23 : out std_logic; + mca_inskew_23 : out std_logic; + mca_outskew_23 : out std_logic; + ref_pclk : out std_logic ); end component; - component serdes_fpga_ref_clk--serdes, flexi PCS - port( --- refclkp : in std_logic; --- refclkn : in std_logic; - rxrefclk : in std_logic; - refclk : in std_logic; - hdinp_0 : in std_logic; - hdinn_0 : in std_logic; - tclk_0 : in std_logic; - rclk_0 : in std_logic; - tx_rst_0 : in std_logic; - rx_rst_0 : in std_logic; - txd_0 : in std_logic_vector(15 downto 0); - tx_k_0 : in std_logic_vector(1 downto 0); - tx_force_disp_0 : in std_logic_vector(1 downto 0); - tx_disp_sel_0 : in std_logic_vector(1 downto 0); - tx_crc_init_0 : in std_logic_vector(1 downto 0); - word_align_en_0 : in std_logic; - mca_align_en_0 : in std_logic; - felb_0 : in std_logic; - lsm_en_0 : in std_logic; - hdinp_1 : in std_logic; - hdinn_1 : in std_logic; - tclk_1 : in std_logic; - rclk_1 : in std_logic; - tx_rst_1 : in std_logic; - rx_rst_1 : in std_logic; - txd_1 : in std_logic_vector(15 downto 0); - tx_k_1 : in std_logic_vector(1 downto 0); - tx_force_disp_1 : in std_logic_vector(1 downto 0); - tx_disp_sel_1 : in std_logic_vector(1 downto 0); - tx_crc_init_1 : in std_logic_vector(1 downto 0); - word_align_en_1 : in std_logic; - mca_align_en_1 : in std_logic; - felb_1 : in std_logic; - lsm_en_1 : in std_logic; - hdinp_2 : in std_logic; - hdinn_2 : in std_logic; - tclk_2 : in std_logic; - rclk_2 : in std_logic; - tx_rst_2 : in std_logic; - rx_rst_2 : in std_logic; - txd_2 : in std_logic_vector(15 downto 0); - tx_k_2 : in std_logic_vector(1 downto 0); - tx_force_disp_2 : in std_logic_vector(1 downto 0); - tx_disp_sel_2 : in std_logic_vector(1 downto 0); - tx_crc_init_2 : in std_logic_vector(1 downto 0); - word_align_en_2 : in std_logic; - mca_align_en_2 : in std_logic; - felb_2 : in std_logic; - lsm_en_2 : in std_logic; - hdinp_3 : in std_logic; - hdinn_3 : in std_logic; - tclk_3 : in std_logic; - rclk_3 : in std_logic; - tx_rst_3 : in std_logic; - rx_rst_3 : in std_logic; - txd_3 : in std_logic_vector(15 downto 0); - tx_k_3 : in std_logic_vector(1 downto 0); - tx_force_disp_3 : in std_logic_vector(1 downto 0); - tx_disp_sel_3 : in std_logic_vector(1 downto 0); - tx_crc_init_3 : in std_logic_vector(1 downto 0); - word_align_en_3 : in std_logic; - mca_align_en_3 : in std_logic; - felb_3 : in std_logic; - lsm_en_3 : in std_logic; - mca_resync_01 : in std_logic; - mca_resync_23 : in std_logic; - quad_rst : in std_logic; - serdes_rst : in std_logic; - rxa_pclk : out std_logic; - rxb_pclk : out std_logic; - hdoutp_0 : out std_logic; - hdoutn_0 : out std_logic; - ref_0_sclk : out std_logic; - rx_0_sclk : out std_logic; - rxd_0 : out std_logic_vector(15 downto 0); - rx_k_0 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_0 : out std_logic_vector(1 downto 0); - rx_cv_detect_0 : out std_logic_vector(1 downto 0); - rx_crc_eop_0 : out std_logic_vector(1 downto 0); - lsm_status_0 : out std_logic; - hdoutp_1 : out std_logic; - hdoutn_1 : out std_logic; - ref_1_sclk : out std_logic; - rx_1_sclk : out std_logic; - rxd_1 : out std_logic_vector(15 downto 0); - rx_k_1 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_1 : out std_logic_vector(1 downto 0); - rx_cv_detect_1 : out std_logic_vector(1 downto 0); - rx_crc_eop_1 : out std_logic_vector(1 downto 0); - lsm_status_1 : out std_logic; - hdoutp_2 : out std_logic; - hdoutn_2 : out std_logic; - ref_2_sclk : out std_logic; - rx_2_sclk : OUT std_logic; - rxd_2 : OUT std_logic_vector(15 downto 0); - rx_k_2 : OUT std_logic_vector(1 downto 0); - rx_disp_err_detect_2 : OUT std_logic_vector(1 downto 0); - rx_cv_detect_2 : OUT std_logic_vector(1 downto 0); - rx_crc_eop_2 : OUT std_logic_vector(1 downto 0); - lsm_status_2 : OUT std_logic; - hdoutp_3 : OUT std_logic; - hdoutn_3 : OUT std_logic; - ref_3_sclk : OUT std_logic; - rx_3_sclk : OUT std_logic; - rxd_3 : OUT std_logic_vector(15 downto 0); - rx_k_3 : OUT std_logic_vector(1 downto 0); - rx_disp_err_detect_3 : out std_logic_vector(1 downto 0); - rx_cv_detect_3 : out std_logic_vector(1 downto 0); - rx_crc_eop_3 : out std_logic_vector(1 downto 0); - lsm_status_3 : out std_logic; - mca_aligned_01 : out std_logic; - mca_inskew_01 : out std_logic; - mca_outskew_01 : out std_logic; - mca_aligned_23 : out std_logic; - mca_inskew_23 : out std_logic; - mca_outskew_23 : out std_logic; - ref_pclk : out std_logic - ); - end component; - component flexi_PCS_synch - generic ( - HOW_MANY_CHANNELS : positive); - port ( - SYSTEM_CLK : in std_logic; - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0) - ); + + component up_down_counter + generic ( + NUMBER_OF_BITS : positive); + port ( + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic; + DOWN_IN : in std_logic); end component; - component pll_ref + + component flexi_PCS_synch + generic ( + HOW_MANY_CHANNELS : positive); port ( - clk : in std_logic; - clkop : out std_logic; - clkos : out std_logic; - lock : out std_logic); + RESET : in std_logic; + SYSTEM_CLK : in std_logic; + TX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); + RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); + RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + TXD : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); + TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + MEDIA_STATUS : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MEDIA_CONTROL : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); + MED_STAT_OP : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_CTRL_OP : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + LINK_DEBUG : out std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0) + ); end component; + component trb_net16_hub_base is generic ( + --don't change --hub control HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; @@ -317,67 +290,77 @@ architecture hub of hub is ); end component; - component simpleupcounter_16bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_32bit - port ( - QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; component edge_to_pulse port ( clock : in std_logic; en_clk : in std_logic; - signal_in : in std_logic; + signal_in : in std_logic; pulse : out std_logic); end component; - component DCS --- synthesis translate_off - --sim + + component etrax_interfacev2 generic ( - DCSMODE : string := "LOW_LOW"); --- synthesis translate_on + RW_SYSTEM : positive); port ( - CLK0 : in std_logic; - CLK1 : in std_logic; - SEL : in std_logic; - DCSOUT : out std_logic); + CLK : in std_logic; + RESET : in std_logic; + DATA_BUS : in std_logic_vector(31 downto 0); + ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0); + ETRAX_DATA_BUS_B_17 : in std_logic; + ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); + ETRAX_DATA_BUS_E : inout std_logic_vector(10 downto 9); + DATA_VALID : in std_logic; + ETRAX_BUS_BUSY : in std_logic; + ETRAX_IS_READY_TO_READ : out std_logic; + TDC_TCK : out std_logic; + TDC_TDI : out std_logic; + TDC_TMS : out std_logic; + TDC_TRST : out std_logic; + TDC_TDO : in std_logic; + TDC_RESET : out std_logic; + EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + EXTERNAL_ACK : out std_logic; + EXTERNAL_VALID : in std_logic; + EXTERNAL_MODE : out std_logic_vector(15 downto 0); + FPGA_REGISTER_00 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); + FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); + FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); +-- EXTERNAL_RESET : out std_logic; + LVL2_VALID : in std_logic); end component; - component hub_etrax_interface + + component simple_hub + generic ( + HOW_MANY_CHANNELS : positive); port ( - CLK : in std_logic; - RESET : in std_logic; - ETRAX_DATA_BUS : inout std_logic_vector(17 downto 5); - EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - EXTERNAL_ACK : out std_logic; - EXTERNAL_VALID : in std_logic; - EXTERNAL_MODE : out std_logic_vector(7 downto 0); - FPGA_REGISTER_00 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); - EXTERNAL_RESET : out std_logic); + CLK : in std_logic; + RESET : in std_logic; + DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + DATA_IN_VALID : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + SEND_DATA : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + ENABLE_CHANNELS : in std_logic_vector(15 downto 0); + READ_DATA : out std_logic_vector(HOW_MANY_CHANNELS -1 downto 0); + HUB_DEBUG : out std_logic_vector(31 downto 0) + ); end component; + + +-- constant HOW_MANY_CHANNELS : integer := 16; ----------------------------------------------------------------------------- -- FLEXI_PCS ----------------------------------------------------------------------------- @@ -391,47 +374,50 @@ architecture hub of hub is signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal flexi_pcs_synch_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + signal link_debug_i : std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0); signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); ----------------------------------------------------------------------------- -- hub trb interface ----------------------------------------------------------------------------- - signal hub_register_00_i : std_logic_vector(7 downto 0); - signal hub_register_01_i : std_logic_vector(7 downto 0); - signal hub_register_02_i : std_logic_vector(7 downto 0); - signal hub_register_03_i : std_logic_vector(7 downto 0); - signal hub_register_04_i : std_logic_vector(7 downto 0); - signal hub_register_05_i : std_logic_vector(7 downto 0); - signal hub_register_06_i : std_logic_vector(7 downto 0); - signal hub_register_07_i : std_logic_vector(7 downto 0); - signal hub_register_08_i : std_logic_vector(7 downto 0); - signal hub_register_09_i : std_logic_vector(7 downto 0); - signal hub_register_0a_i : std_logic_vector(7 downto 0); - signal hub_register_0b_i : std_logic_vector(7 downto 0); - signal hub_register_0c_i : std_logic_vector(7 downto 0); - signal hub_register_0d_i : std_logic_vector(7 downto 0):=x"06"; - signal hub_register_0e_i : std_logic_vector(7 downto 0):=x"00"; - signal hub_register_0f_i : std_logic_vector(7 downto 0); - signal hub_register_10_i : std_logic_vector(7 downto 0); - signal hub_register_11_i : std_logic_vector(7 downto 0); - signal hub_register_12_i : std_logic_vector(7 downto 0); - signal hub_register_13_i : std_logic_vector(7 downto 0); - signal hub_register_14_i : std_logic_vector(7 downto 0); - signal hub_register_15_i : std_logic_vector(7 downto 0); - signal hub_register_16_i : std_logic_vector(7 downto 0); + signal hub_register_00_i : std_logic_vector(31 downto 0); + signal hub_register_01_i : std_logic_vector(31 downto 0); + signal hub_register_02_i : std_logic_vector(31 downto 0); + signal hub_register_03_i : std_logic_vector(31 downto 0); + signal hub_register_04_i : std_logic_vector(31 downto 0); + signal hub_register_05_i : std_logic_vector(31 downto 0); + signal hub_register_06_i : std_logic_vector(31 downto 0); + signal hub_register_07_i : std_logic_vector(31 downto 0); + signal hub_register_08_i : std_logic_vector(31 downto 0); + signal hub_register_09_i : std_logic_vector(31 downto 0); + signal hub_register_0a_i : std_logic_vector(31 downto 0); + signal hub_register_0b_i : std_logic_vector(31 downto 0); + signal hub_register_0c_i : std_logic_vector(31 downto 0); + signal hub_register_0d_i : std_logic_vector(31 downto 0); + signal hub_register_0e_i : std_logic_vector(31 downto 0); + signal hub_register_0f_i : std_logic_vector(31 downto 0); + signal hub_register_10_i : std_logic_vector(31 downto 0); + signal hub_register_11_i : std_logic_vector(31 downto 0); + signal hub_register_12_i : std_logic_vector(31 downto 0); + signal hub_register_13_i : std_logic_vector(31 downto 0); + signal hub_register_14_i : std_logic_vector(31 downto 0); + signal hub_register_15_i : std_logic_vector(31 downto 0); + signal hub_register_16_i : std_logic_vector(31 downto 0); signal ADO_TTL_12 : std_logic; ----------------------------------------------------------------------------- -- flexi_PCS to hub interface ----------------------------------------------------------------------------- signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + signal med_dataready_in_i_test : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); --test - signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_DATA_WIDTH-1 downto 0); - signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_DATA_WIDTH-1 downto 0); + signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + signal med_data_out_i_test : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + + signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); @@ -439,7 +425,6 @@ architecture hub of hub is signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0); signal hub_stat_gen_i : std_logic_vector(31 downto 0); - signal HUB_STAT_DEBUG, HUB_CTRL_DEBUG : std_logic_vector(31 downto 0); ----------------------------------------------------------------------------- -- other @@ -450,8 +435,10 @@ architecture hub of hub is signal serdes_ref_clk : std_logic; signal serdes_ref_lock : std_logic; signal serdes_ref_clks : std_logic; - signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH -1 downto 0); + signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0); signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0); + signal word_counter_for_api_00 : std_logic_vector(1 downto 0); + signal word_counter_for_api_01 : std_logic_vector(1 downto 0); signal global_reset_i : std_logic; signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0"; signal registered_signals : std_logic_vector(7 downto 0); @@ -474,14 +461,15 @@ architecture hub of hub is signal all_lvl1_ready_delay2 : std_logic; signal all_lvl2_ready_delay1 : std_logic; signal all_lvl2_ready_delay2 : std_logic; + signal media_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); -- etrax interface - signal external_address_i : std_logic_vector(31 downto 0); - signal external_data_out_i : std_logic_vector(31 downto 0); - signal external_data_in_i : std_logic_vector(31 downto 0); - signal external_ack_i : std_logic; - signal external_valid_i : std_logic; - signal external_mode_i : std_logic_vector(7 downto 0); - signal data_valid_i : std_logic; +-- signal external_address_i : std_logic_vector(31 downto 0); +-- signal external_data_out_i : std_logic_vector(31 downto 0); +-- signal external_data_in_i : std_logic_vector(31 downto 0); +-- signal external_ack_i : std_logic; +-- signal external_valid_i : std_logic; +-- signal external_mode_i : std_logic_vector(7 downto 0); +-- signal data_valid_i : std_logic; signal debug_register_00_i : std_logic_vector(7 downto 0); signal test2 : std_logic_vector(1 downto 0); signal med_read_counter : std_logic_vector(3 downto 0); @@ -491,8 +479,44 @@ architecture hub of hub is signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - + constant trb_net_enable : integer := 1; + --etrax interface + signal external_address_i : std_logic_vector(31 downto 0); + signal external_data_out_i : std_logic_vector(31 downto 0); + signal external_data_in_i : std_logic_vector(31 downto 0); + signal external_ack_i : std_logic; + signal external_valid_i : std_logic; + signal external_mode_i : std_logic_vector(15 downto 0); + signal fpga_register_00_i : std_logic_vector(31 downto 0); + signal fpga_register_01_i : std_logic_vector(31 downto 0); + signal fpga_register_02_i : std_logic_vector(31 downto 0); + signal fpga_register_03_i : std_logic_vector(31 downto 0); + signal fpga_register_04_i : std_logic_vector(31 downto 0); + signal fpga_register_05_i : std_logic_vector(31 downto 0); + signal fpga_register_06_i : std_logic_vector(31 downto 0):=x"00000003"; + signal fpga_register_07_i : std_logic_vector(31 downto 0); + signal fpga_register_08_i : std_logic_vector(31 downto 0); + signal fpga_register_09_i : std_logic_vector(31 downto 0); + signal fpga_register_0a_i : std_logic_vector(31 downto 0); + signal fpga_register_0b_i : std_logic_vector(31 downto 0); + signal fpga_register_0c_i : std_logic_vector(31 downto 0); + signal fpga_register_0d_i : std_logic_vector(31 downto 0); + signal fpga_register_0e_i : std_logic_vector(31 downto 0); + signal free_counter : std_logic_vector(16 downto 0); + --simple hub + signal hub_debug_i : std_logic_vector(31 downto 0); + + --test + constant OPT_TEST_MODE : integer := 0; + + --trbnet + signal hub_stat_debug_i : std_logic_vector(63 downto 0); + signal hub_ctrl_debug_i : std_logic_vector(63 downto 0); + signal sfp_los_synch : std_logic_vector(16 downto 1); + signal wait_counter : std_logic_vector(31 downto 0); + signal wait_counter_up : std_logic; begin + GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt) begin if rising_edge(LVDS_CLK_200P) then @@ -508,56 +532,12 @@ begin end if; end if; end process GLOBAL_RESET; - REF_PLL: pll_ref - port map ( - clk => LVDS_CLK_200P, - clkop => serdes_ref_clk, - clkos => serdes_ref_clks, - lock => serdes_ref_lock); - TEST: edge_to_pulse - port map ( - clock => ref_pclk(0), - en_clk => '1', - signal_in => hub_register_0a_i(0), - pulse => pulse_test); - test_signal(1) <= pulse_test; - test_signal(0) <= pulse_test; - REF_CLK_SELECT: DCS - -- synthesis translate_off - --sim - generic map ( - DCSMODE => DCSMODE) - -- synthesis translate_on - port map ( - CLK0 => LVDS_CLK_200P, - CLK1 => '0', - SEL => switch_rx_clk,--hub_register_0a_i(0),--'0',--switch_rx_clk, - DCSOUT => flexi_pcs_ref_clk); - SWITCH_CLOCK: process (LVDS_CLK_200P, global_reset_i) - begin -- process SWITCH_CLOCK - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' or lock_pattern /= used_channels_locked then -- asynchronous reset (active low) - switch_rx_clk <= '0'; - lock_pattern <= (others => '1'); - elsif lock_pattern = used_channels_locked then - switch_rx_clk <= '1'; - lock_pattern <= (others => '1'); - end if; - end if; - end process SWITCH_CLOCK; --- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate --- begin --- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16); --- end generate LOK_STATUS_DIOD_EN; - - --lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1); + QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate begin QUAD : serdes_fpga_ref_clk port map ( --- refclkp => SERDES_200P, --- refclkn => SERDES_200N, - rxrefclk => flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, + rxrefclk => LVDS_CLK_200P,--flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, hdinp_0 => SFP_INP_P(bit_index*4+0), hdinn_0 => SFP_INP_N(bit_index*4+0), @@ -675,233 +655,277 @@ begin ); end generate QUAD_GENERATE; -- word_align_en <= not rx_rst_i; - --sim --- rx_k_sim(0) <= not OPT_DATA_VALID_IN(0); --- rx_k_sim(1) <= '0'; --- rx_k_sim(2) <= not OPT_DATA_VALID_IN(1); --- rx_k_sim(3) <= '0'; --- rx_k_sim(4) <= not OPT_DATA_VALID_IN(2); --- rx_k_sim(5) <= '0'; +--sim-- SIMULATION_CONNECTION: for i in 0 to HOW_MANY_CHANNELS-1 generate +--sim-- rx_k_sim(i*2) <= not OPT_DATA_VALID_IN(i); +--sim-- rx_k_sim(i*2+1) <= '0'; +--sim-- OPT_DATA_VALID_OUT(i) <= not tx_k_sim(i*2); +--sim-- rx_clk_sim <= (others => LVDS_CLK_200P); +--sim-- ref_pclk_sim <= (others => LVDS_CLK_200P); +--sim-- cv_sim <= (others => '0'); +--sim-- end generate SIMULATION_CONNECTION; + FLEXI_PCS_INT : flexi_PCS_synch + generic map ( + HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) + port map ( + RESET => global_reset_i, + SYSTEM_CLK => LVDS_CLK_200P, + TX_CLK => ref_pclk, --no_sim-- +--sim-- TX_CLK => ref_pclk_sim, + RX_CLK => rx_clk_i, --no_sim-- +--sim-- RX_CLK => rx_clk_sim, + RXD => rxd_i, --no_sim-- +--sim-- RXD => OPT_DATA_IN, + RX_K => rx_k_i, --no_sim-- +--sim-- RX_K => rx_k_sim, + RX_RST => rx_rst_i, + CV => cv_i, --no_sim-- +--sim-- CV => cv_sim, + TXD => txd_synch_i, --no_sim-- +--sim-- TXD => OPT_DATA_OUT, + TX_K => tx_k_i, --no_sim-- +--sim-- TX_K => tx_k_sim, + MEDIA_STATUS => media_status_i, + MEDIA_CONTROL => open, + MED_DATAREADY_IN => med_dataready_in_i, + MED_DATA_IN => med_data_in_i, + MED_READ_OUT => med_read_out_i, + MED_DATA_OUT => med_data_out_i, + MED_DATAREADY_OUT => med_dataready_out_i, + MED_READ_IN => med_read_in_i, + MED_PACKET_NUM_IN => med_packet_num_in_i, + MED_PACKET_NUM_OUT => med_packet_num_out_i, + MED_STAT_OP => med_stat_op_i, + MED_CTRL_OP => med_ctrl_op_i, + LINK_DEBUG => link_debug_i + ); + + ADO_TTL(15 downto 0) <= link_debug_i(7 downto 4) & med_dataready_out_i(0) & med_packet_num_out_i(2 downto 0) & med_data_out_i(7 downto 0);--link_debug_i(15 downto 0); + ADO_TTL(34 downto 19) <= link_debug_i(23 downto 22) & LVDS_CLK_200P & med_read_out_i(0) & med_dataready_in_i(0) & med_packet_num_in_i(2 downto 0) & med_data_in_i(7 downto 0);--link_debug_i(31 downto 16); --- OPT_DATA_VALID_OUT(0) <= not tx_k_sim(0); --- OPT_DATA_VALID_OUT(1) <= not tx_k_sim(2); --- OPT_DATA_VALID_OUT(2) <= not tx_k_sim(4); --- cv_sim <= (others => '0'); --- rx_clk_sim <= (others => LVDS_CLK_200P); --- ref_pclk_sim <= (others => LVDS_CLK_200P); - --end sim - FLEXI_PCS_INT : flexi_PCS_synch + + SIMPLE_HUB_GEN : if trb_net_enable = 0 and OPT_TEST_MODE = 0 generate + + SIMPLE_HUB_INST : simple_hub generic map ( - HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) + HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) port map ( - SYSTEM_CLK => LVDS_CLK_200P, - CLK => ref_pclk,--,ref_pclk_sim,--ref_pclk,--,sim - RX_CLK => rx_clk_i,--rx_clk_sim,--rx_clk_i,--sim - RESET => global_reset_i, - RXD => rxd_i,--OPT_DATA_IN,--rxd_i,--sim - MED_DATA_OUT => med_data_out_i, - RX_K => rx_k_i,--rx_k_sim,--rx_k_i,--sim - RX_RST => rx_rst_i, - CV => cv_i,--cv_sim,--cv_i,--sim - MED_DATA_IN => med_data_in_i, - TXD_SYNCH => txd_synch_i,--OPT_DATA_OUT,--txd_synch_i,--sim - TX_K => tx_k_i, --tx_k_sim,--tx_k_i, --sim - FLEXI_PCS_SYNCH_STATUS => flexi_pcs_synch_status_i, - MED_DATAREADY_IN => med_dataready_in_i,--data_valid_in_i,--med_dataready_in_i, - MED_DATAREADY_OUT => med_dataready_out_i, - MED_PACKET_NUM_IN => med_packet_num_in_i, - MED_PACKET_NUM_OUT => med_packet_num_out_i, - MED_READ_IN => med_read_in_i, - MED_READ_OUT => med_read_out_i, - MED_STAT_OP => med_stat_op_i, - MED_CTRL_OP => med_ctrl_op_i + CLK => LVDS_CLK_200P, + RESET => global_reset_i, +-- DATA_IN => med_data_out_i, + DATA_IN => med_data_out_i_test, + DATA_OUT => med_data_in_i, + DATA_IN_VALID => med_dataready_out_i, +-- SEND_DATA => med_dataready_in_i, + SEND_DATA => med_dataready_in_i_test, + ENABLE_CHANNELS => fpga_register_06_i(15 downto 0), + READ_DATA => med_read_in_i, + HUB_DEBUG => hub_debug_i ); - ADO_TTL(34 downto 19) <= flexi_pcs_synch_status_i(2 downto 0) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0); --- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0); - ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0); --- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0); --- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d; --- med_read_in_i <= (others => '1'); --test - - - HUB_API: trb_net16_hub_base - generic map( - MII_NUMBER => HOW_MANY_CHANNELS - ) - port map ( - CLK => LVDS_CLK_200P, - RESET => global_reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_in_i, - MED_DATA_OUT => med_data_in_i, - MED_PACKET_NUM_OUT => med_packet_num_in_i, - MED_READ_IN => med_read_out_i, - MED_DATAREADY_IN => med_dataready_out_i, - MED_DATA_IN => med_data_out_i, - MED_PACKET_NUM_IN => med_packet_num_out_i, - MED_READ_OUT => med_read_in_i, - MED_STAT_OP => med_stat_op_i, - MED_CTRL_OP => med_ctrl_op_i, - INT_INIT_DATAREADY_OUT => open, - INT_INIT_DATA_OUT => open, - INT_INIT_PACKET_NUM_OUT => open, - INT_INIT_READ_IN => (others => '1'), - INT_INIT_DATAREADY_IN => (others => '0'), - INT_INIT_DATA_IN => (others => '0'), - INT_INIT_PACKET_NUM_IN => (others => '0'), - INT_INIT_READ_OUT => open, - INT_REPLY_DATAREADY_OUT => open, - INT_REPLY_DATA_OUT => open, - INT_REPLY_PACKET_NUM_OUT => open, - INT_REPLY_READ_IN => (others => '1'), - INT_REPLY_DATAREADY_IN => (others => '0'), - INT_REPLY_DATA_IN => (others => '0'), - INT_REPLY_PACKET_NUM_IN => (others => '0'), - INT_REPLY_READ_OUT => open, - ONEWIRE => FS_PE_11, - HUB_STAT_CHANNEL => hub_stat_channel_i, - HUB_STAT_GEN => hub_stat_gen_i, - MPLEX_CTRL => mplex_ctrl_i, - MPLEX_STAT => open, - REGIO_EXT_REG_DATA_IN => (others => '0'), - REGIO_EXT_REG_DATA_OUT=> open, - REGIO_EXT_REG_WRITE_IN=> '0', - REGIO_EXT_REG_ADDR_IN => (others => '0'), - STAT_DEBUG => HUB_STAT_DEBUG, - CTRL_DEBUG => HUB_CTRL_DEBUG - ); - - - TRB_HUB_INT : trb_hub_interface - port map ( - CLK => LVDS_CLK_200P, - RESET => open, --ADO_TTL(0), - STROBE => open, --ADO_TTL(9), - internal_data_in => open, --ADO_TTL(18 downto 11), - internal_data_out => open, --ADO_TTL(42 downto 35), - internal_address => open, --ADO_TTL(34 downto 19), - internal_mode => open, --ADO_TTL(10), - VALID_DATA_SENT => open, --ADO_TTL(8), - HUB_REGISTER_00 => hub_register_00_i, - HUB_REGISTER_01 => hub_register_01_i, - HUB_REGISTER_02 => hub_register_02_i, - HUB_REGISTER_03 => hub_register_03_i, - HUB_REGISTER_04 => hub_register_04_i, - HUB_REGISTER_05 => hub_register_05_i, - HUB_REGISTER_06 => hub_register_06_i, - HUB_REGISTER_07 => hub_register_07_i, - HUB_REGISTER_08 => hub_register_08_i, - HUB_REGISTER_09 => hub_register_09_i, - HUB_REGISTER_0a => hub_register_0a_i, - HUB_REGISTER_0b => hub_register_0b_i, - HUB_REGISTER_0c => hub_register_0c_i, - HUB_REGISTER_0d => hub_register_0d_i, - HUB_REGISTER_0e => hub_register_0e_i, - HUB_REGISTER_0f => hub_register_0f_i, - HUB_REGISTER_10 => hub_register_10_i, - HUB_REGISTER_11 => hub_register_11_i, - HUB_REGISTER_12 => hub_register_12_i, - HUB_REGISTER_13 => hub_register_13_i, - HUB_REGISTER_14 => hub_register_14_i, - HUB_REGISTER_15 => hub_register_15_i, - HUB_REGISTER_16 => hub_register_16_i - ); + end generate SIMPLE_HUB_GEN; + + FREE_COUNTER_INST: up_down_counter + generic map ( + NUMBER_OF_BITS => 17) + port map ( + CLK => LVDS_CLK_200P, + RESET => '0', + COUNT_OUT => free_counter, + UP_IN => '1', + DOWN_IN => '0'); + + WAIT_COUNTER_INST: up_down_counter + generic map ( + NUMBER_OF_BITS => 32) + port map ( + CLK => LVDS_CLK_200P, + RESET => '0', + COUNT_OUT => wait_counter, + UP_IN => wait_counter_up, + DOWN_IN => '0'); - process (LVDS_CLK_200P, global_reset_i, med_dataready_out_i) - begin + wait_counter_up <= '1' when wait_counter(31) = '0' else '0'; + + ENABLE_OPT_TEST : if OPT_TEST_MODE = 1 generate + + SEND_COUNTER: process (LVDS_CLK_200P, global_reset_i) + begin if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then -- asynchronous reset (active low) - registered_signals(0) <= '0'; - elsif med_dataready_out_i(0) = '1' then - registered_signals(0) <= '1'; - else - registered_signals(0) <= registered_signals(0); - end if; - end if; - end process; - process (rx_clk_i(0), global_reset_i, rx_k_i(0)) - begin - if rising_edge(rx_clk_i(0)) then - if global_reset_i = '1' then -- asynchronous reset (active low) - registered_signals(1) <= '0'; - elsif rx_k_i(1 downto 0) = "00" and flexi_pcs_synch_status_i(3 downto 0) = x"6" then - registered_signals(1) <= '1'; - else - registered_signals(1) <= registered_signals(1); - end if; + if global_reset_i = '1' then + med_dataready_in_i <= (others => '0'); + med_data_in_i <= (others => '0'); +-- elsif med_stat_op_i(9)='1' or med_stat_op_i(24)='1' or med_stat_op_i(40)='1' or med_stat_op_i(56)='1' then + -- elsif link_debug_i(3 downto 0) = x"a" and link_debug_i(35 downto 32) > 10 then + elsif wait_counter(31) = '1' then + + med_dataready_in_i <= free_counter(16) & free_counter(16) &free_counter(16) &free_counter(16); + med_data_in_i <= free_counter(15 downto 0) & free_counter(15 downto 0) & free_counter(15 downto 0) & free_counter(15 downto 0); + else + med_dataready_in_i <= (others => '0'); + med_data_in_i <= (others => '0'); end if; - end process; - process (rx_clk_i(0), global_reset_i,rx_k_i(1)) - begin - if rising_edge(rx_clk_i(0)) then - if global_reset_i = '1' then -- asynchronous reset (active low) - registered_signals(2) <= '0'; - elsif rx_k_i(1 downto 0) = "00" and flexi_pcs_synch_status_i(3 downto 0) > x"7" then - registered_signals(2) <= '1'; - else - registered_signals(2) <= registered_signals(2); - end if; - end if; - end process; - registered_signals(4 downto 3) <= rx_k_i(1) & rx_k_i(0); + end if; + end process SEND_COUNTER; + med_read_in_i <= (others => '1'); +-- med_data_in_i <= med_data_out_i; +-- med_dataready_in_i <= med_dataready_out_i; + end generate ENABLE_OPT_TEST; + ENABLE_TRB_NET: if trb_net_enable = 1 generate + + HUB_API: trb_net16_hub_base + generic map( + MII_NUMBER => HOW_MANY_CHANNELS + ) + port map ( + CLK => LVDS_CLK_200P, + RESET => global_reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_in_i, + MED_DATA_OUT => med_data_in_i, + MED_PACKET_NUM_OUT => med_packet_num_in_i, + MED_READ_IN => med_read_out_i, + MED_DATAREADY_IN => med_dataready_out_i, + MED_DATA_IN => med_data_out_i, + MED_PACKET_NUM_IN => med_packet_num_out_i, + MED_READ_OUT => med_read_in_i, + MED_STAT_OP => med_stat_op_i, + MED_CTRL_OP => med_ctrl_op_i, + INT_INIT_DATAREADY_OUT => open, + INT_INIT_DATA_OUT => open, + INT_INIT_PACKET_NUM_OUT => open, + INT_INIT_READ_IN => (others => '1'), + INT_INIT_DATAREADY_IN => (others => '0'), + INT_INIT_DATA_IN => (others => '0'), + INT_INIT_PACKET_NUM_IN => (others => '0'), + INT_INIT_READ_OUT => open, + INT_REPLY_DATAREADY_OUT => open, + INT_REPLY_DATA_OUT => open, + INT_REPLY_PACKET_NUM_OUT => open, + INT_REPLY_READ_IN => (others => '1'), + INT_REPLY_DATAREADY_IN => (others => '0'), + INT_REPLY_DATA_IN => (others => '0'), + INT_REPLY_PACKET_NUM_IN => (others => '0'), + INT_REPLY_READ_OUT => open, + ONEWIRE => FS_PE_11, + HUB_STAT_CHANNEL => hub_stat_channel_i, + HUB_STAT_GEN => hub_stat_gen_i, + MPLEX_CTRL => mplex_ctrl_i, + MPLEX_STAT => open, + REGIO_EXT_REG_DATA_IN => (others => '0'), + REGIO_EXT_REG_DATA_OUT => open, + REGIO_EXT_REG_WRITE_IN => '0', + REGIO_EXT_REG_ADDR_IN => (others => '0'), + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + end generate ENABLE_TRB_NET; + + ETRAX_RW_DATA_INTERFACE : etrax_interfacev2 + generic map ( + RW_SYSTEM => 2) + port map ( + CLK => LVDS_CLK_200P, + RESET => global_reset_i, + DATA_BUS => (others => '0'), + ETRAX_DATA_BUS_B => open,--(others => '0'), + ETRAX_DATA_BUS_B_17 => '0', + ETRAX_DATA_BUS_C => open,--(others => '0'), + ETRAX_DATA_BUS_E => FS_PE(9 downto 8), + DATA_VALID => '0', + ETRAX_BUS_BUSY => '0', + ETRAX_IS_READY_TO_READ => open, + TDC_TCK => open, + TDC_TDI => open, + TDC_TMS => open, + TDC_TRST => open, + TDC_TDO => '0', + TDC_RESET => open, + EXTERNAL_ADDRESS => open, + EXTERNAL_DATA_OUT => open, + EXTERNAL_DATA_IN => x"ddbbccaa",--external_data_in_i, + EXTERNAL_ACK => external_ack_i, + EXTERNAL_VALID => '0',--external_valid_i, + EXTERNAL_MODE => external_mode_i, + FPGA_REGISTER_00 => fpga_register_00_i, + FPGA_REGISTER_01 => fpga_register_01_i, + FPGA_REGISTER_02 => fpga_register_02_i, + FPGA_REGISTER_03 => fpga_register_03_i, + FPGA_REGISTER_04 => fpga_register_04_i, + FPGA_REGISTER_05 => fpga_register_05_i, + FPGA_REGISTER_06 => fpga_register_06_i, + FPGA_REGISTER_07 => fpga_register_07_i, + FPGA_REGISTER_08 => fpga_register_08_i, + FPGA_REGISTER_09 => fpga_register_09_i, + FPGA_REGISTER_0A => fpga_register_0A_i, + FPGA_REGISTER_0B => fpga_register_0B_i, + FPGA_REGISTER_0C => fpga_register_0C_i, + FPGA_REGISTER_0D => fpga_register_0D_i, + FPGA_REGISTER_0E => fpga_register_0E_i, + -- EXTERNAL_RESET => open, + LVL2_VALID => '0'); + fpga_register_00_i <= x"0000"& lok_i; + fpga_register_01_i <= hub_debug_i; + fpga_register_02_i <= link_debug_i(31 downto 0); + fpga_register_03_i <= link_debug_i(63 downto 32); + fpga_register_04_i <= rxd_i(31 downto 0); + fpga_register_0A_i <= rxd_i(63 downto 32); +-- fpga_register_02_i <= link_debug_i(95 downto 64); +-- fpga_register_03_i <= link_debug_i(127 downto 96); +-- fpga_register_04_i <= rxd_i(95 downto 64); +-- fpga_register_0A_i <= rxd_i(127 downto 96); + fpga_register_0B_i <= conv_std_logic_vector(VERSION_NUMBER_TIME,32); + fpga_register_0C_i <= link_debug_i(95 downto 64); + fpga_register_0D_i <= link_debug_i(127 downto 96); +-- -- fpga_register_08_i <= rxd_i(63 downto 32); +-- fpga_register_0a_i(15 downto 0) <= cv_i(7 downto 0) & rx_k_i(3 downto 0) & "0000"; + --- hub_register_00_i(7 downto 0) <= flexi_pcs_synch_status_i(7 downto 0); --- hub_register_01_i(7 downto 0) <= hub_stat_gen_i(15 downto 8); - hub_register_02_i(7 downto 0) <= (others => '0');--saved_lvl1_ready(7 downto 0);--rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8); - hub_register_03_i(7 downto 0) <= (others => '0');--saved_lvl1_ready(15 downto 8);--rxd_i(15 downto 8); --cv_counter_ch1; - hub_register_04_i(7 downto 0) <= (others => '0');--saved_lvl2_ready(7 downto 0);--hub_stat_gen_i(7 downto 0); - -- hub_register_04_i<= rxd_synch_i(39 downto 32); - hub_register_05_i(7 downto 0) <= (others => '0');--saved_lvl2_ready(15 downto 8);--rxd_i(31 downto 24); - hub_register_10_i(7 downto 0) <= med_data_out_i(31 downto 24);--rxd_i(7+8*16 downto 0+8*16); --; --rxd_1_a(15 downto 8); - -- hub_register_11_i <= rxd_i(23+8*16 downto 16+8*16); --cv_counter_ch1; - -- hub_register_12_i <= rxd_i(39+8*16 downto 32+8*16); - -- hub_register_13_i <= rxd_i(63+8*16 downto 56+8*16); - -- hub_register_14_i <= flexi_pcs_synch_status_i(23+8*16 downto 16+8*16); - -- hub_register_15_i <= flexi_pcs_synch_status_i(39+8*16 downto 32+8*16); - -- hub_register_16_i <= flexi_pcs_synch_status_i(63+8*16 downto 56+8*16); + COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i ) + begin + if rising_edge(LVDS_CLK_200P) then + if global_reset_i = '1' then + fpga_register_05_i <= (others => '0'); + elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then + fpga_register_05_i <= fpga_register_05_i + 1; + end if; + end if; + end process COUNT_LVL1_START; - hub_register_06_i(7 downto 0) <= tx_k_i(1 downto 0) & med_error_out_i(5 downto 0); - hub_register_07_i(7 downto 0) <= hub_stat_gen_i(31 downto 24);--flexi_pcs_synch_status_i(39 downto 32); - hub_register_08_i(7 downto 0) <= hub_stat_gen_i(23 downto 16);--flexi_pcs_synch_status_i(55 downto 48); - hub_register_09_i(7 downto 0) <= med_data_out_i(23 downto 16);--x"0" & data_valid_out_i(3 downto 0); - hub_register_0e_and_0d <= hub_register_0e_i & hub_register_0d_i; --- txd_i(15 downto 0) <= hub_register_0e_and_0d; --- txd_i(31 downto 16) <= hub_register_0e_and_0d; --- txd_i(47 downto 32) <= hub_register_0e_and_0d; --- txd_i(63 downto 48) <= hub_register_0e_and_0d; - hub_register_11_i(7 downto 0) <= hub_stat_channel_i(7 downto 0);--flexi_pcs_synch_status_i(55 downto 48); - hub_register_12_i(7 downto 0) <= hub_stat_channel_i(15 downto 8);--flexi_pcs_synch_status_i(55 downto 48); - hub_register_13_i(7 downto 0) <= med_dataready_out_i(0)& med_dataready_in_i(0) & med_dataready_out_i(0)®istered_signals(4 downto 0); - hub_register_14_i(7 downto 0) <= flexi_pcs_synch_status_i (15 downto 8); - hub_register_15_i(7 downto 0) <= x"0" & med_packet_num_out_i(3 downto 0); - -- hub_register_13_i <= hub_stat_channel_i(23 downto 16);--flexi_pcs_synch_status_i(55 downto 48); - -- hub_register_14_i <= hub_stat_channel_i(31 downto 24);--flexi_pcs_synch_status_i(55 downto 48); - -- txd_i(255 downto 64) <= hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & - -- hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & - -- hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d; - data_valid_in_i(0) <= hub_register_0a_i(0); - data_valid_in_i(1) <= hub_register_0a_i(1); --- data_valid_in_i(2) <= hub_register_0a_i(2); --- data_valid_in_i(3) <= hub_register_0a_i(3); --- data_valid_in_i(4) <= hub_register_0a_i(0); --- data_valid_in_i(5) <= hub_register_0a_i(1); --- data_valid_in_i(6) <= hub_register_0a_i(2); --- data_valid_in_i(7) <= hub_register_0a_i(3); --- data_valid_in_i(8) <= hub_register_0a_i(0); --- data_valid_in_i(9) <= hub_register_0a_i(1); --- data_valid_in_i(10) <= hub_register_0a_i(2); --- data_valid_in_i(11) <= hub_register_0a_i(3); --- data_valid_in_i(12) <= hub_register_0a_i(0); --- data_valid_in_i(13) <= hub_register_0a_i(1); --- data_valid_in_i(14) <= hub_register_0a_i(2); --- data_valid_in_i(15) <= hub_register_0a_i(3); +-- COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i ) +-- begin +-- if rising_edge(LVDS_CLK_200P) then +-- if global_reset_i = '1' then +-- fpga_register_08_i <= (others => '0'); +-- elsif med_data_ready_in_i(1) = '1' and med_data_in_i(31 downto 28) = x"1" then +-- fpga_register_08_i <= fpga_register_08_i + 1; +-- end if; +-- end if; +-- end process COUNT_LVL1_SEND; --- data_valid_in_i(15 downto 4) <= hub_register_0a_i(7 downto 0) & hub_register_0a_i(7 downto 4); + COUNT_LVL1_SEND_a: process (LVDS_CLK_200P, global_reset_i ) + begin + if rising_edge(LVDS_CLK_200P) then + if global_reset_i = '1' then + fpga_register_09_i <= (others => '0'); + elsif med_dataready_in_i(1) = '1' then + fpga_register_09_i <= fpga_register_08_i + 1; + end if; + end if; + end process COUNT_LVL1_SEND_a; - -- RT(16 downto 1) <= (others => '0'); + COUNT_LVL1_END: process (LVDS_CLK_200P, global_reset_i ) + begin + if rising_edge(LVDS_CLK_200P) then + if global_reset_i = '1' then + fpga_register_07_i <= (others => '0'); + elsif med_dataready_out_i(1) = '1' and med_data_out_i(31 downto 28) = x"1" then + fpga_register_07_i <= fpga_register_07_i + 1; + end if; + end if; + end process COUNT_LVL1_END; TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate begin @@ -912,26 +936,41 @@ begin begin WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate TX_DIS(16-not_connected) <= '1'; - end generate; + end generate WHEN_NOT_ALL_EN; end generate; --------------------------------------------------------------------------- -- setting LED --------------------------------------------------------------------------- + + --correct this for channels 11-8 - mirrored due to schematics -- also + --adressing of sfps !!! + SYNCH_EXT_SIGNAL: process (LVDS_CLK_200P) + begin + if rising_edge(LVDS_CLK_200P) then + if global_reset_i = '1' then + sfp_los_synch <= (others => '0'); + else + sfp_los_synch <= SFP_LOS; + end if; + end if; + end process SYNCH_EXT_SIGNAL; LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate begin - lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16); + -- lok_i(synch_fsm_state+1) <= not link_debug_i(2+synch_fsm_state*31); + lok_i(synch_fsm_state+1) <= med_stat_op_i(9 + synch_fsm_state*16); + media_status_i(synch_fsm_state*16) <= '0';--SFP_LOS(synch_fsm_state); end generate LOK_STATUS_DIOD_EN; - - LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate - begin - hub_register_00_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16); - end generate LOK_STATUS_REGISTER_0; - - LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate - begin - hub_register_01_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16+8*16); - end generate LOK_STATUS_REGISTER_1; + +-- LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate +-- begin +-- hub_register_00_i(synch_fsm_state) <= link_debug_i(2+synch_fsm_state*31); +-- end generate LOK_STATUS_REGISTER_0; + +-- LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate +-- begin +-- hub_register_01_i(synch_fsm_state) <= link_debug_i(2+synch_fsm_state*31+8*16); +-- end generate LOK_STATUS_REGISTER_1; LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate begin @@ -939,16 +978,17 @@ begin lok_i(16-not_connected) <= '1'; end generate WHEN_NOT_ALL_EN; end generate LOK_STATUS_DIOD_DIS; + LOK <= lok_i; IPLL <= '0'; OPLL <= '0'; - DBAD <= ADO_TTL(11); + DBAD <= '1'; DGOOD <= '1'; DINT <= '0'; DWAIT <= global_reset_i; CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i) - begin + begin if rising_edge(LVDS_CLK_200P) then -- rising clock edge if global_reset_i = '1' then -- asynchronous reset (active low) cv_counter <= (others => '0'); @@ -958,7 +998,7 @@ begin end if; end process CV_COUNTERaaa; CV_COUNTERaab: process (ref_pclk(0), global_reset_i) - begin + begin if rising_edge(ref_pclk(0)) then -- rising clock edge if global_reset_i = '1' then -- asynchronous reset (active low) cv_countera <= (others => '0'); @@ -969,11 +1009,10 @@ begin end process CV_COUNTERaab; RT(8) <= cv_counter(23); RT(9) <= med_read_in_i(0); - RT(16 downto 10) <= flexi_pcs_synch_status_i(7 downto 1); + RT(16 downto 10) <= link_debug_i(7 downto 1); RT(2) <= flexi_pcs_ref_clk;--cv_counter(0); - RT(1) <= not switch_rx_clk;--ref_pclk(0); - + RT(3) <= LVDS_CLK_200P; RT(4) <= rx_k_i(0); @@ -982,6 +1021,5 @@ begin RT(6) <= med_data_out_i(0);--serdes_ref_clks; RT(7) <= med_data_out_i(1);--serdes_ref_lock; - -end architecture; +end hub; diff --git a/optical_link/hub_1.xcf b/optical_link/hub_1.xcf index b73bed2..350e53a 100644 --- a/optical_link/hub_1.xcf +++ b/optical_link/hub_1.xcf @@ -43,7 +43,7 @@ /home/marek/trbnet/optical_link/workdir/hub.bit /home/marek/.isplever_lin1/ispvmsystem/Database/xpga/sc/lfsc3ga25e.msk - 8/15/2007 14:18:24 + 3/31/2009 22:28:11 Fast Program