From 055f7f877353692b41e3690faa80877ba6d8cb24 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Wed, 23 Apr 2014 22:26:22 +0200 Subject: [PATCH] nxyter update, beamtime May ready? --- nxyter/compile_munich20.sh | 7 + nxyter/compile_munich21.sh | 2 + nxyter/source/adc_spi_master.vhd | 33 +- nxyter/source/nx_data_delay.vhd | 103 +-- nxyter/source/nx_data_receiver.vhd | 909 +++++++++++++------------ nxyter/source/nx_data_validate.vhd | 237 ++++--- nxyter/source/nx_fpga_timestamp.vhd | 80 +-- nxyter/source/nx_status.vhd | 20 +- nxyter/source/nx_trigger_generator.vhd | 234 ++----- nxyter/source/nx_trigger_handler.vhd | 126 +++- nxyter/source/nxyter_components.vhd | 38 +- nxyter/source/nxyter_fee_board.vhd | 62 +- nxyter/source/registers.txt | 9 +- nxyter/trb3_periph.p2t | 2 +- nxyter/trb3_periph.prj | 1 + nxyter/trb3_periph_constraints.lpf | 48 +- nxyter/trb3_periph_nx1.vhd | 4 +- 17 files changed, 976 insertions(+), 939 deletions(-) diff --git a/nxyter/compile_munich20.sh b/nxyter/compile_munich20.sh index bed8cfa..7994aa3 100755 --- a/nxyter/compile_munich20.sh +++ b/nxyter/compile_munich20.sh @@ -3,3 +3,10 @@ . /usr/local/opt/lattice_diamond/diamond/2.0/bin/lin/diamond_env exec ./compile_munich20.pl + +grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup +grep 'Error:' ./workdir/trb3_periph.twr.hold +grep 'potential circuit loops' ./workdir/* + +echo "Script DONE!" + diff --git a/nxyter/compile_munich21.sh b/nxyter/compile_munich21.sh index 39fac4a..99940f1 100755 --- a/nxyter/compile_munich21.sh +++ b/nxyter/compile_munich21.sh @@ -6,5 +6,7 @@ #grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup" grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup +grep 'Error:' ./workdir/trb3_periph.twr.hold +grep 'potential circuit loops' ./workdir/* echo "Script DONE!" diff --git a/nxyter/source/adc_spi_master.vhd b/nxyter/source/adc_spi_master.vhd index df4c26b..0d773dc 100644 --- a/nxyter/source/adc_spi_master.vhd +++ b/nxyter/source/adc_spi_master.vhd @@ -111,7 +111,25 @@ architecture Behavioral of adc_spi_master is signal spi_register_value_read : std_logic_vector(7 downto 0); begin + ----------------------------------------------------------------------------- + -- Debug Line + ----------------------------------------------------------------------------- + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= sclk_o; + DEBUG_OUT(2) <= SDIO_INOUT; + DEBUG_OUT(3) <= csb_o; + DEBUG_OUT(4) <= spi_busy; + DEBUG_OUT(5) <= wait_timer_done; + DEBUG_OUT(6) <= sendbyte_seq_start; + DEBUG_OUT(7) <= sendbyte_done; + DEBUG_OUT(8) <= sclk_sendbyte; + DEBUG_OUT(9) <= sdio_sendbyte; + DEBUG_OUT(10) <= sclk_readbyte; + DEBUG_OUT(11) <= takeover_sdio; + DEBUG_OUT(15 downto 12) <= (others => '0'); + ----------------------------------------------------------------------------- + -- Timer timer_static_1: timer_static generic map ( @@ -153,21 +171,6 @@ begin SCLK_OUT => sclk_readbyte ); - -- Debug Line - - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= sclk_o; - DEBUG_OUT(2) <= SDIO_INOUT; - DEBUG_OUT(3) <= csb_o; - DEBUG_OUT(4) <= spi_busy; - DEBUG_OUT(5) <= wait_timer_done; - DEBUG_OUT(6) <= sendbyte_seq_start; - DEBUG_OUT(7) <= sendbyte_done; - DEBUG_OUT(8) <= sclk_sendbyte; - DEBUG_OUT(9) <= sdio_sendbyte; - DEBUG_OUT(10) <= sclk_readbyte; - DEBUG_OUT(11) <= takeover_sdio; - -- Sync SPI SDIO Line sdio_i <= SDIO_INOUT; diff --git a/nxyter/source/nx_data_delay.vhd b/nxyter/source/nx_data_delay.vhd index 1bfad5a..637924e 100644 --- a/nxyter/source/nx_data_delay.vhd +++ b/nxyter/source/nx_data_delay.vhd @@ -14,12 +14,10 @@ entity nx_data_delay is RESET_IN : in std_logic; -- Signals - NX_FRAME_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); + DATA_IN : in std_logic_vector(43 downto 0); DATA_CLK_IN : in std_logic; - NX_FRAME_OUT : out std_logic_vector(31 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_OUT : out std_logic_vector(43 downto 0); DATA_CLK_OUT : out std_logic; FIFO_DELAY_IN : in std_logic_vector(7 downto 0); @@ -39,23 +37,27 @@ entity nx_data_delay is end entity; architecture Behavioral of nx_data_delay is + -- Input FFs + signal data_in_f : std_logic_vector(43 downto 0); + signal data_clk_in_f : std_logic; -- FIFO Write Handler - signal fifo_data_in : std_logic_vector(43 downto 0); signal fifo_full : std_logic; signal fifo_write_enable : std_logic; signal fifo_reset : std_logic; + signal fifo_reset_p : std_logic; + signal fifo_reset_l : std_logic; + -- FIFO READ - signal fifo_data_out : std_logic_vector(43 downto 0); + signal fifo_data_o : std_logic_vector(43 downto 0); signal fifo_read_enable : std_logic; signal fifo_empty : std_logic; signal fifo_almost_empty : std_logic; signal fifo_read_enable_t : std_logic; signal fifo_read_enable_tt : std_logic; - signal nx_frame_o : std_logic_vector(31 downto 0); - signal adc_data_o : std_logic_vector(11 downto 0); + signal data_o : std_logic_vector(43 downto 0); signal data_clk_o : std_logic; -- Fifo Delay @@ -80,48 +82,61 @@ begin PROC_DEBUG_MULTIPLEXER: process(debug_r) begin if (debug_r = '0') then - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= DATA_CLK_IN; - DEBUG_OUT(2) <= fifo_reset; - DEBUG_OUT(3) <= fifo_full; - DEBUG_OUT(4) <= fifo_write_enable; - DEBUG_OUT(5) <= fifo_empty; - DEBUG_OUT(6) <= fifo_almost_empty; - DEBUG_OUT(7) <= fifo_read_enable; - DEBUG_OUT(8) <= fifo_read_enable_t; - DEBUG_OUT(9) <= fifo_read_enable_tt; - DEBUG_OUT(10) <= data_clk_o; - --DEBUG_OUT(15 downto 11) <= NX_FRAME_OUT(14 downto 10); + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= DATA_CLK_IN; + DEBUG_OUT(2) <= fifo_reset; + DEBUG_OUT(3) <= fifo_full; + DEBUG_OUT(4) <= fifo_write_enable; + DEBUG_OUT(5) <= fifo_empty; + DEBUG_OUT(6) <= fifo_almost_empty; + DEBUG_OUT(7) <= fifo_read_enable; + DEBUG_OUT(8) <= fifo_read_enable_t; + DEBUG_OUT(9) <= fifo_read_enable_tt; + DEBUG_OUT(10) <= data_clk_o; + DEBUG_OUT(15 downto 11) <= (others => '0'); else - DEBUG_OUT <= debug_fifo; + DEBUG_OUT <= debug_fifo; end if; end process PROC_DEBUG_MULTIPLEXER; ----------------------------------------------------------------------------- -- FIFO Delay Handler ----------------------------------------------------------------------------- - + + data_in_f <= DATA_IN when rising_edge(CLK_IN); + data_clk_in_f <= DATA_CLK_IN when rising_edge(CLK_IN); + fifo_44_data_delay_my_1: fifo_44_data_delay_my port map ( - Data => fifo_data_in, + Data => data_in_f, Clock => CLK_IN, WrEn => fifo_write_enable, - RdEn => fifo_read_enable, --LOOP?? + RdEn => fifo_read_enable, Reset => fifo_reset, AmEmptyThresh => fifo_delay, - Q => fifo_data_out, --fifo_data_out_0, - Empty => fifo_empty, -- fifo_empty_0, - Full => fifo_full, --fifo_full_0, - AlmostEmpty => fifo_almost_empty, -- fifo_almost_empty_0, + Q => fifo_data_o, + Empty => fifo_empty, + Full => fifo_full, + AlmostEmpty => fifo_almost_empty, DEBUG_OUT => debug_fifo ); fifo_read_enable <= not fifo_almost_empty; - fifo_reset <= RESET_IN or fifo_reset_r or fifo_delay_reset; - fifo_data_in(31 downto 0) <= NX_FRAME_IN; - fifo_data_in(43 downto 32) <= ADC_DATA_IN; - fifo_write_enable <= DATA_CLK_IN and not fifo_full; - + fifo_reset <= RESET_IN or fifo_reset_l; + fifo_write_enable <= data_clk_in_f and not fifo_full; + + fifo_reset_p <= fifo_reset_r or fifo_delay_reset; + pulse_to_level_FIFO_RESET: pulse_to_level + generic map ( + NUM_CYCLES => 3 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + PULSE_IN => fifo_reset_p, + LEVEL_OUT => fifo_reset_l + ); + -- FIFO Read Handler PROC_FIFO_READ: process(CLK_IN) begin @@ -130,8 +145,7 @@ begin fifo_read_enable_t <= '0'; fifo_read_enable_tt <= '0'; - nx_frame_o <= (others => '0'); - adc_data_o <= (others => '0'); + data_o <= (others => '0'); data_clk_o <= '0'; else -- Read enable @@ -139,12 +153,10 @@ begin fifo_read_enable_tt <= fifo_read_enable_t; if (fifo_read_enable_tt = '1') then - nx_frame_o <= fifo_data_out(31 downto 0); - adc_data_o <= fifo_data_out(43 downto 32); + data_o <= fifo_data_o; data_clk_o <= '1'; else - nx_frame_o <= x"ffff_ffff"; - adc_data_o <= x"fff"; + data_o <= x"fff_ffff_ffff"; data_clk_o <= '0'; end if; end if; @@ -240,13 +252,12 @@ begin end process PROC_FIFO_REGISTERS; -- Output Signals - NX_FRAME_OUT <= nx_frame_o; - ADC_DATA_OUT <= adc_data_o; - DATA_CLK_OUT <= data_clk_o; + DATA_OUT <= data_o; + DATA_CLK_OUT <= data_clk_o; - SLV_DATA_OUT <= slv_data_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; + SLV_DATA_OUT <= slv_data_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index c080334..34d1c81 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -8,6 +8,9 @@ use work.trb_net_components.all; use work.nxyter_components.all; entity nx_data_receiver is + generic ( + DEBUG_ENABLE : boolean := false + ); port( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -30,8 +33,7 @@ entity nx_data_receiver is ADC_SCLK_LOCK_OUT : out std_logic; -- Outputs - NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_OUT : out std_logic_vector(43 downto 0); DATA_CLK_OUT : out std_logic; -- Slave bus @@ -56,56 +58,41 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- NX_TIMESTAMP_IN Process + signal nx_timestamp_delay_f : unsigned(2 downto 0); + signal nx_timestamp_delay : unsigned(2 downto 0); + signal nx_shift_register_delay : std_logic_vector(5 downto 0); signal nx_frame_word_ff : std_logic_vector(7 downto 0); signal nx_frame_word_f : std_logic_vector(7 downto 0); + signal nx_frame_word_s : std_logic_vector(7 downto 0); + signal nx_frame_word_t : std_logic_vector(31 downto 0); signal nx_frame_clk_t : std_logic; - signal nx_frame_word_coded : std_logic_vector(31 downto 0); - signal nx_frame_clk_coded : std_logic; -- Frame Sync Process signal frame_byte_pos : unsigned(1 downto 0); - - -- RS Sync FlipFlop - signal nx_frame_synced : std_logic; - signal rs_sync_set : std_logic; - signal rs_sync_reset : std_logic; - - -- Gray Decoder signal nx_frame_word : std_logic_vector(31 downto 0); signal nx_frame_clk : std_logic; signal nx_frame_clk_c100 : std_logic; - -- NX Timestamp Delay - constant S1_PIPE_LEN : integer := 5; - type delay_array_s1 is array(0 to S1_PIPE_LEN) - of std_logic_vector(31 downto 0); - signal nx_timestamp_delayed_s1 : delay_array_s1; - signal nx_timestamp_delayed_s1_clk : std_logic; - - constant S2_PIPE_LEN : integer := 4; - type delay_array_s2 is array(0 to S2_PIPE_LEN) - of std_logic_vector(31 downto 0); - signal nx_timestamp_delayed_s2 : delay_array_s2; - signal nx_timestamp_delay : unsigned(2 downto 0); + -- RS Sync FlipFlop + signal nx_frame_synced : std_logic; + signal rs_sync_set : std_logic; + signal rs_sync_reset : std_logic; + -- NX Timestamp Frame Delay type delay_array_b is array(0 to 3) of std_logic_vector(31 downto 0); signal nx_frame_word_delayed_t : delay_array_b; signal nx_frame_clk_delayed_t : std_logic_vector(3 downto 0); signal nx_timestamp_delayed : std_logic_vector(31 downto 0); signal nx_timestamp_delayed_clk : std_logic; - + + signal nx_frame_word_delay_f : unsigned(1 downto 0); signal nx_frame_word_delay : unsigned(1 downto 0); signal adc_data_clk_last : std_logic_vector(3 downto 0); signal frame_word_delay_change : std_logic; signal frame_word_delay_set : std_logic; - - -- NX Clock Active - signal nx_clk_active_ff_0 : std_logic; - signal nx_clk_active_ff_1 : std_logic; - signal nx_clk_active_ff_2 : std_logic; - + -- ADC Ckl Generator signal adc_clk_skip : std_logic; signal adc_sampling_clk : std_logic; @@ -155,8 +142,7 @@ architecture Behavioral of nx_data_receiver is signal merge_error_ctr : unsigned(11 downto 0); -- Data Output Handler - signal nx_timestamp_o : std_logic_vector(31 downto 0); - signal adc_data_o : std_logic_vector(11 downto 0); + signal data_o : std_logic_vector(43 downto 0); signal data_clk_o : std_logic; -- Check Nxyter Data Clock via Johnson Counter @@ -195,12 +181,23 @@ architecture Behavioral of nx_data_receiver is signal parity_rate_error : std_logic; signal reset_for_offline : std_logic; + -- Events per Second Errors + signal adc_dt_error_cur : std_logic; + signal adc_dt_error : std_logic; + signal timestamp_dt_error_cur : std_logic; + signal timestamp_dt_error : std_logic; + -- Data Stream DeltaT Error Counters - signal new_adc_delta_t_ctr : unsigned(3 downto 0); - signal new_timestamp_delta_t_ctr : unsigned(3 downto 0); + signal new_adc_dt_ctr : unsigned(3 downto 0); + signal new_timestamp_dt_ctr : unsigned(3 downto 0); signal new_adc_dt_error_ctr : unsigned(11 downto 0); signal new_timestamp_dt_error_ctr : unsigned(11 downto 0); + signal adc_dt_error_p : std_logic; + signal adc_dt_error_c100 : std_logic; + signal timestamp_dt_error_p : std_logic; + signal timestamp_dt_error_c100 : std_logic; + ----------------------------------------------------------------------------- -- CLK Domain Transfer ----------------------------------------------------------------------------- @@ -228,16 +225,18 @@ architecture Behavioral of nx_data_receiver is signal reset_parity_error_ctr : std_logic; signal debug_mode : std_logic_vector(2 downto 0); signal reset_handler_start_r : std_logic; - signal reset_handler_counter_clear : std_logic; signal adc_bit_shift : unsigned(3 downto 0); signal johnson_counter_sync_r : unsigned(1 downto 0); signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0); - signal pll_adc_sample_clk_finedelb_r : std_logic_vector(3 downto 0); + signal pll_adc_sample_clk_finedelb_r : unsigned(3 downto 0); signal nx_timestamp_delay_r : unsigned(2 downto 0); signal nx_frame_word_delay_r : unsigned(1 downto 0); signal fifo_full_r : std_logic; signal fifo_empty_r : std_logic; - + signal new_adc_dt_error_ctr_r : unsigned(11 downto 0); + signal new_timestamp_dt_error_ctr_r : unsigned(11 downto 0); + signal adc_notlock_ctr_r : unsigned(7 downto 0); + ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- @@ -249,7 +248,7 @@ architecture Behavioral of nx_data_receiver is signal rs_timeout_timer_done : std_logic; signal rs_timeout_timer_reset : std_logic; signal nx_timestamp_reset_o : std_logic; - signal fifo_reset : std_logic; + signal fifo_reset_handler : std_logic; type R_STATES is (R_IDLE, R_SET_ALL_RESETS, @@ -263,7 +262,7 @@ architecture Behavioral of nx_data_receiver is signal frame_rates_reset : std_logic; signal sampling_clk_reset : std_logic; - signal adc_reset : std_logic; + signal adc_reset_handler : std_logic; signal adc_reset_p : std_logic; signal output_handler_reset : std_logic; @@ -287,123 +286,163 @@ architecture Behavioral of nx_data_receiver is signal RESET_NX_TIMESTAMP_CLK_IN : std_logic; signal debug_state : std_logic_vector(3 downto 0); - + signal debug_frame_on : std_logic; + begin - - PROC_DEBUG_MULT: process(debug_mode, - adc_data, - adc_data_clk, - adc_clk_ok, - adc_clk_ok_last, - adc_clk_skip, - adc_reset_sync, - adc_reset_sync_s, - ADC_RESET_AD9228, - nx_frame_clk, - adc_reset_ctr, - fifo_write_enable, - fifo_empty, - fifo_read_enable, - nx_timestamp_delayed_clk, - adc_data_s_clk, - data_clk_o, - nx_frame_synced, - rs_sync_reset - ) - begin - case debug_mode is - when "000" => - -- Default - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= TRIGGER_IN; - DEBUG_OUT(2) <= data_frame_clk; - DEBUG_OUT(3) <= fifo_reset; - DEBUG_OUT(4) <= fifo_full; - DEBUG_OUT(5) <= fifo_write_enable; - DEBUG_OUT(6) <= fifo_empty; - DEBUG_OUT(7) <= fifo_read_enable; - DEBUG_OUT(8) <= fifo_data_clk; - DEBUG_OUT(9) <= nx_frame_clk; - DEBUG_OUT(10) <= nx_timestamp_delayed_clk; - DEBUG_OUT(11) <= adc_data_s_clk; - DEBUG_OUT(12) <= data_clk_o; - DEBUG_OUT(13) <= parity_error_c100; - DEBUG_OUT(14) <= merge_timeout_error; - DEBUG_OUT(15) <= nx_frame_synced; - - when "001" => - -- Reset Handler - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= nx_frame_clk; - DEBUG_OUT(2) <= adc_clk_skip; - DEBUG_OUT(3) <= adc_clk_ok; - DEBUG_OUT(4) <= adc_reset_sync; - DEBUG_OUT(5) <= adc_reset; - DEBUG_OUT(6) <= ADC_RESET_AD9228; - DEBUG_OUT(7) <= pll_adc_not_lock; - DEBUG_OUT(8) <= reset_for_offline; - DEBUG_OUT(9) <= fifo_reset; - DEBUG_OUT(10) <= reset_handler_busy; - DEBUG_OUT(11) <= sampling_clk_reset; - DEBUG_OUT(15 downto 12) <= debug_state; - - when "010" => - -- AD9228 Handler Debug output - DEBUG_OUT <= ADC_DEBUG; - - when "011" => - -- Test Channel - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(3 downto 1) <= debug_state(2 downto 0); - DEBUG_OUT(4) <= reset_handler_busy; - DEBUG_OUT(5) <= nx_frame_rate_offline; - DEBUG_OUT(6) <= nx_frame_rate_error; - DEBUG_OUT(7) <= pll_adc_not_lock; - DEBUG_OUT(8) <= error_adc0; - DEBUG_OUT(9) <= adc_frame_rate_error; - DEBUG_OUT(10) <= fifo_reset; - DEBUG_OUT(11) <= sampling_clk_reset; - DEBUG_OUT(12) <= adc_reset; - DEBUG_OUT(13) <= output_handler_reset; - DEBUG_OUT(14) <= frame_rate_error; - DEBUG_OUT(15) <= reset_timeout_flag; - - when "100" => - -- AD9228 Handler Debug output - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= '0'; - DEBUG_OUT(2) <= nx_frame_clk; - DEBUG_OUT(3) <= '0'; - DEBUG_OUT(4) <= nx_timestamp_delayed_clk; - DEBUG_OUT(5) <= '0'; - DEBUG_OUT(6) <= adc_data_clk; - DEBUG_OUT(7) <= '0'; - DEBUG_OUT(8) <= fifo_write_enable; - DEBUG_OUT(9) <= '0'; - DEBUG_OUT(10) <= data_frame_clk; - DEBUG_OUT(15 downto 11) <= (others => '0'); - - when "101" => - -- AD9228 Handler Debug output - DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; - DEBUG_OUT(1) <= '0'; - DEBUG_OUT(2) <= nx_frame_clk; - DEBUG_OUT(3) <= '0'; - DEBUG_OUT(4) <= nx_timestamp_delayed_clk; - DEBUG_OUT(5) <= merge_timeout_error; - DEBUG_OUT(6) <= adc_data_s_clk; - DEBUG_OUT(7) <= data_frame_clk; - DEBUG_OUT(9 downto 8) <= nx_frame_word_delay; - DEBUG_OUT(10) <= frame_word_delay_change; - DEBUG_OUT(11) <= frame_word_delay_set; - DEBUG_OUT(15 downto 12) <= adc_data_clk_last; - - when others => - DEBUG_OUT <= (others => '0'); - end case; - - end process PROC_DEBUG_MULT; + DFALSE: if (DEBUG_ENABLE = false) generate + DEBUG_OUT <= (others => '0'); + end generate DFALSE; + + DTRUE: if (DEBUG_ENABLE = true) generate + PROC_DEBUG_MULT: process(debug_mode, + adc_data, + adc_data_clk, + adc_clk_ok, + adc_clk_ok_last, + adc_clk_skip, + adc_reset_sync, + adc_reset_sync_s, + ADC_RESET_AD9228, + nx_frame_clk, + adc_reset_ctr, + fifo_write_enable, + fifo_empty, + fifo_read_enable, + nx_timestamp_delayed_clk, + adc_data_s_clk, + data_clk_o, + nx_frame_synced, + rs_sync_reset + ) + begin + case debug_mode is + when "001" => + -- Reset Handler + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= nx_frame_clk; + DEBUG_OUT(2) <= adc_clk_skip; + DEBUG_OUT(3) <= adc_clk_ok; + DEBUG_OUT(4) <= adc_reset_sync; + DEBUG_OUT(5) <= adc_reset_handler; + DEBUG_OUT(6) <= ADC_RESET_AD9228; + DEBUG_OUT(7) <= pll_adc_not_lock; + DEBUG_OUT(8) <= reset_for_offline; + DEBUG_OUT(9) <= fifo_reset_handler; + DEBUG_OUT(10) <= reset_handler_busy; + DEBUG_OUT(11) <= sampling_clk_reset; + DEBUG_OUT(15 downto 12) <= debug_state; + + when "010" => + -- AD9228 Handler Debug output + DEBUG_OUT <= ADC_DEBUG; + + when "011" => + -- Test Channel + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(3 downto 1) <= debug_state(2 downto 0); + DEBUG_OUT(4) <= reset_handler_busy; + DEBUG_OUT(5) <= nx_frame_rate_offline; + DEBUG_OUT(6) <= nx_frame_rate_error; + DEBUG_OUT(7) <= pll_adc_not_lock; + DEBUG_OUT(8) <= error_adc0; + DEBUG_OUT(9) <= adc_frame_rate_error; + DEBUG_OUT(10) <= fifo_reset_handler; + DEBUG_OUT(11) <= sampling_clk_reset; + DEBUG_OUT(12) <= adc_reset_handler; + DEBUG_OUT(13) <= output_handler_reset; + DEBUG_OUT(14) <= frame_rate_error; + DEBUG_OUT(15) <= reset_timeout_flag; + + when "100" => + -- AD9228 Handler Debug output + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= '0'; + DEBUG_OUT(2) <= nx_frame_clk; + DEBUG_OUT(3) <= '0'; + DEBUG_OUT(4) <= nx_timestamp_delayed_clk; + DEBUG_OUT(5) <= '0'; + DEBUG_OUT(6) <= adc_data_clk; + DEBUG_OUT(7) <= '0'; + DEBUG_OUT(8) <= fifo_write_enable; + DEBUG_OUT(9) <= '0'; + DEBUG_OUT(10) <= data_frame_clk; + DEBUG_OUT(11) <= '0'; + DEBUG_OUT(12) <= nx_frame_synced; + DEBUG_OUT(13) <= '0'; + DEBUG_OUT(14) <= frame_word_delay_change; + DEBUG_OUT(15) <= data_clk_o; + + when "101" => + -- AD9228 Handler Debug output + DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(1) <= '0'; + DEBUG_OUT(2) <= nx_frame_clk; + DEBUG_OUT(3) <= '0'; + DEBUG_OUT(4) <= nx_timestamp_delayed_clk; + DEBUG_OUT(5) <= merge_timeout_error; + DEBUG_OUT(6) <= adc_data_s_clk; + DEBUG_OUT(7) <= data_frame_clk; + DEBUG_OUT(9 downto 8) <= nx_frame_word_delay; + DEBUG_OUT(10) <= frame_word_delay_change; + DEBUG_OUT(11) <= frame_word_delay_set; + DEBUG_OUT(15 downto 12) <= adc_data_clk_last; + + when "110" => + DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(1) <= '0'; + DEBUG_OUT(2) <= '0'; + DEBUG_OUT(3) <= '0'; + DEBUG_OUT(4) <= '0'; + DEBUG_OUT(5) <= debug_frame_on; + DEBUG_OUT(6) <= '0'; + DEBUG_OUT(7) <= '0'; + DEBUG_OUT(8) <= '0'; + DEBUG_OUT(9) <= '0'; + DEBUG_OUT(10) <= adc_sampling_clk; + DEBUG_OUT(11) <= '0'; + DEBUG_OUT(12) <= '0'; + DEBUG_OUT(13) <= '0'; + DEBUG_OUT(14) <= '0'; + DEBUG_OUT(15) <= ADC_SAMPLE_CLK_OUT; + + when others => + -- Default + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= TRIGGER_IN; + DEBUG_OUT(2) <= data_frame_clk; + DEBUG_OUT(3) <= fifo_reset_handler; + DEBUG_OUT(4) <= fifo_full; + DEBUG_OUT(5) <= fifo_write_enable; + DEBUG_OUT(6) <= fifo_empty; + DEBUG_OUT(7) <= fifo_read_enable; + DEBUG_OUT(8) <= fifo_data_clk; + DEBUG_OUT(9) <= nx_frame_clk; + DEBUG_OUT(10) <= nx_timestamp_delayed_clk; + DEBUG_OUT(11) <= adc_data_s_clk; + DEBUG_OUT(12) <= data_clk_o; + DEBUG_OUT(13) <= parity_error_c100; + DEBUG_OUT(14) <= merge_timeout_error; + DEBUG_OUT(15) <= nx_frame_synced; + + end case; + + end process PROC_DEBUG_MULT; + + PROC_SAMPLE_CLOCK: process(NX_TIMESTAMP_CLK_IN) + begin + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (NX_TIMESTAMP_IN = x"06" and + nx_frame_word_ff = x"7f") then + debug_frame_on <= '1'; + else + debug_frame_on <= '0'; + end if; + end if; + end process PROC_SAMPLE_CLOCK; + + end generate DTRUE; + ----------------------------------------------------------------------------- -- Reset Domain Transfer ----------------------------------------------------------------------------- @@ -418,15 +457,19 @@ begin -- PLL Handler ----------------------------------------------------------------------------- - pll_adc_sampling_clk_reset <= sampling_clk_reset when rising_edge(CLK_IN); - - pll_adc_sample_clk_finedelb <= - pll_adc_sample_clk_finedelb_r when rising_edge(CLK_IN); - - -- Shift dphase to show 0 as optimal value in standard setup - pll_adc_sample_clk_dphase <= - std_logic_vector(pll_adc_sample_clk_dphase_r - 2) when rising_edge(CLK_IN); - + PROC_PLL_PHASE_SETUP: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + -- Shift dphase to show 0 as optimal value in standard setup + pll_adc_sample_clk_dphase <= + std_logic_vector(13 + pll_adc_sample_clk_dphase_r); + pll_adc_sample_clk_finedelb <= + std_logic_vector(8 + pll_adc_sample_clk_finedelb_r); + + pll_adc_sampling_clk_reset <= sampling_clk_reset; + end if; + end process PROC_PLL_PHASE_SETUP; + pll_adc_sampling_clk_2: pll_adc_sampling_clk port map ( CLK => adc_sampling_clk, @@ -522,8 +565,8 @@ begin timer_static_RESET_TIMEOUT: timer_static generic map ( - CTR_WIDTH => 30, - CTR_END => 1000000000 -- 10s + CTR_WIDTH => 32, + CTR_END => 2000000000 -- 10s ) port map ( CLK_IN => CLK_IN, @@ -552,58 +595,33 @@ begin SIGNAL_OUT => adc_clk_ok_c100 ); - PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) - begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if(RESET_NX_TIMESTAMP_CLK_IN = '1' ) then - nx_clk_active_ff_0 <= '0'; - nx_clk_active_ff_1 <= '0'; - nx_clk_active_ff_2 <= '0'; - else - nx_clk_active_ff_0 <= not nx_clk_active_ff_2; - nx_clk_active_ff_1 <= nx_clk_active_ff_0; - nx_clk_active_ff_2 <= nx_clk_active_ff_1; - end if; - end if; - end process PROC_NX_CLK_ACT; - -- ADC Sampling Clock Generator using a Johnson Counter PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - johnson_ff_0 <= '0'; - johnson_ff_1 <= '0'; - else - if (adc_clk_skip = '0') then - johnson_ff_0 <= not johnson_ff_1; - johnson_ff_1 <= johnson_ff_0; - adc_sampling_clk <= not johnson_ff_1; - end if; + if (adc_clk_skip = '0') then + johnson_ff_0 <= not johnson_ff_1; + johnson_ff_1 <= johnson_ff_0; end if; + adc_sampling_clk <= not johnson_ff_1; end if; - adc_sampling_clk <= johnson_ff_0; end process PROC_ADC_SAMPLING_CLK_GENERATOR; -- Adjust johnson_counter_sync to show optimal value at 0 - johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r + 3); + PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN) variable adc_clk_state : std_logic_vector(1 downto 0); begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - adc_clk_skip <= '0'; - adc_clk_ok <= '0'; - else - adc_clk_state := johnson_ff_1 & johnson_ff_0; - adc_clk_skip <= '0'; - if (nx_frame_clk_coded = '1') then - if (adc_clk_state /= johnson_counter_sync) then - adc_clk_skip <= '1'; - adc_clk_ok <= '0'; - else - adc_clk_ok <= '1'; - end if; + johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r); + adc_clk_state := johnson_ff_1 & johnson_ff_0; + adc_clk_skip <= '0'; + if (nx_frame_clk = '1') then + if (adc_clk_state /= johnson_counter_sync) then + adc_clk_skip <= '1'; + adc_clk_ok <= '0'; + else + adc_clk_ok <= '1'; end if; end if; end if; @@ -641,42 +659,85 @@ begin ----------------------------------------------------------------------------- -- NX Timestamp Handler ----------------------------------------------------------------------------- - - -- Merge TS Data 8bit to 32Bit Timestamp Frame - PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) + + -- First use two FFs for NX_TIMESTAMP_IN + PROC_INPUT_FF: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then + nx_frame_word_ff <= NX_TIMESTAMP_IN; + nx_frame_word_f <= nx_frame_word_ff; + end if; + end process PROC_INPUT_FF; + + -- Second delay NX_TIMESTAMP_IN relatively to ADC Clock + dynamic_shift_register8x64_1: dynamic_shift_register8x64 + port map ( + Din => nx_frame_word_f, + Addr => nx_shift_register_delay, + Clock => NX_TIMESTAMP_CLK_IN, + ClockEn => '1', + Reset => RESET_NX_TIMESTAMP_CLK_IN, + Q => nx_frame_word_s + ); + + -- Timestamp Input Delay relative to ADC + PROC_NX_SHIFT_REGISTER_DELAY: process(NX_TIMESTAMP_CLK_IN) + begin + if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + nx_timestamp_delay_f <= nx_timestamp_delay_r; if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then - nx_frame_word_f <= (others => '0'); - nx_frame_clk_t <= '0'; - nx_frame_word_coded <= (others => '0'); - nx_frame_clk_coded <= '0'; + nx_timestamp_delay <= "010"; + nx_shift_register_delay <= "011011"; -- 27 else - nx_frame_word_ff <= NX_TIMESTAMP_IN; - nx_frame_word_f <= nx_frame_word_ff; - - case frame_byte_pos is - when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_f; - nx_frame_clk_t <= '0'; - - when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_f; - nx_frame_clk_t <= '0'; - - when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_f; - nx_frame_clk_t <= '0'; - - when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_f; - nx_frame_clk_t <= '1'; + nx_timestamp_delay <= nx_timestamp_delay_f; + + case nx_timestamp_delay is + when "000" => + nx_shift_register_delay <= "011011"; -- 27 + + when "001" => + nx_shift_register_delay <= "011111"; -- 31 + + when "010" => + nx_shift_register_delay <= "100011"; -- 35 + + when "011" => + nx_shift_register_delay <= "100111"; -- 39 + + when "100" => + nx_shift_register_delay <= "101011"; -- 43 + + when others => null; end case; + end if; + end if; + end process PROC_NX_SHIFT_REGISTER_DELAY; - -- Output Frame - if (nx_frame_clk_t = '1') then - nx_frame_word_coded <= nx_frame_word_t; - nx_frame_clk_coded <= '1'; - else - nx_frame_word_coded <= x"0000_0001"; - nx_frame_clk_coded <= '0'; - end if; + -- Merge TS Data 8bit to 32Bit Timestamp Frame + PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) + begin + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then + case frame_byte_pos is + when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_s; + nx_frame_clk_t <= '0'; + + when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_s; + nx_frame_clk_t <= '0'; + + when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_s; + nx_frame_clk_t <= '0'; + + when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_s; + nx_frame_clk_t <= '1'; + end case; + + -- Output Frame + if (nx_frame_clk_t = '1') then + nx_frame_word <= nx_frame_word_t; + nx_frame_clk <= '1'; + else + nx_frame_word <= x"0000_0001"; + nx_frame_clk <= '0'; end if; end if; end process PROC_8_TO_32_BIT; @@ -736,75 +797,31 @@ begin end if; end process PROC_RS_FRAME_SYNCED; - ----------------------------------------------------------------------------- - -- Gray Decode Timestamp Frame (Timestamp and Channel Id) - ----------------------------------------------------------------------------- - - gray_decoder_TIMESTAMP: gray_decoder -- Decode nx_timestamp - generic map ( - WIDTH => 14 - ) - port map ( - CLK_IN => NX_TIMESTAMP_CLK_IN, - RESET_IN => RESET_NX_TIMESTAMP_CLK_IN, - GRAY_IN(13 downto 7) => not nx_frame_word_coded(30 downto 24), - GRAY_IN( 6 downto 0) => not nx_frame_word_coded(22 downto 16), - BINARY_OUT(13 downto 7) => nx_frame_word(30 downto 24), - BINARY_OUT(6 downto 0) => nx_frame_word(22 downto 16) - ); - - gray_decoder_CHANNEL_ID: gray_decoder -- Decode Channel_ID - generic map ( - WIDTH => 7 - ) - port map ( - CLK_IN => NX_TIMESTAMP_CLK_IN, - RESET_IN => RESET_NX_TIMESTAMP_CLK_IN, - GRAY_IN => nx_frame_word_coded(14 downto 8), - BINARY_OUT => nx_frame_word(14 downto 8) - ); - - -- Leave other bits and frame clk untouched, i.e. delay by one clk - PROC_GRAY_DECODE: process(NX_TIMESTAMP_CLK_IN) - begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - nx_frame_word(31) <= nx_frame_word_coded(31); - nx_frame_word(23) <= nx_frame_word_coded(23); - nx_frame_word(15) <= nx_frame_word_coded(15); - nx_frame_word(7 downto 1) <= nx_frame_word_coded(7 downto 1); - nx_frame_clk <= nx_frame_clk_coded; - end if; - end process PROC_GRAY_DECODE; - - -- Replace Parity Bit by Parity Error Bit + -- Check Parity Bit PROC_PARITY_CHECKER: process(NX_TIMESTAMP_CLK_IN) variable parity_bits : std_logic_vector(22 downto 0); variable parity : std_logic; begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - parity_error <= '0'; - nx_frame_word(0) <= '0'; + parity_error <= '0'; else - parity_error <= '0'; - nx_frame_word(0) <= '1'; - - if (nx_frame_clk_coded = '1') then + if (nx_frame_clk = '1') then -- Timestamp Bit #6 is excluded (funny nxyter-bug) - parity_bits := nx_frame_word_coded(31) & - nx_frame_word_coded(30 downto 24) & - nx_frame_word_coded(21 downto 16) & - nx_frame_word_coded(14 downto 8) & - nx_frame_word_coded( 2 downto 1); - parity := xor_all(parity_bits); - - if (parity /= nx_frame_word_coded(0)) then - parity_error <= '1'; - nx_frame_word(0) <= '1'; + parity_bits := nx_frame_word(31) & + nx_frame_word(30 downto 24) & + nx_frame_word(21 downto 16) & + nx_frame_word(14 downto 8) & + nx_frame_word( 2 downto 1); + parity := xor_all(parity_bits); + + if (parity /= nx_frame_word(0)) then + parity_error <= '1'; else - parity_error <= '0'; - nx_frame_word(0) <= '0'; + parity_error <= '0'; end if; + else + parity_error <= '0'; end if; end if; end if; @@ -816,55 +833,33 @@ begin PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then - nx_frame_word_delayed_t(0) <= nx_frame_word; - nx_frame_clk_delayed_t(0) <= nx_frame_clk; + nx_frame_word_delayed_t(0) <= nx_frame_word; + nx_frame_clk_delayed_t(0) <= nx_frame_clk; -- Delay Pipeline NX Clock for X in 1 to 3 loop nx_frame_word_delayed_t(X) <= nx_frame_word_delayed_t(X - 1); nx_frame_clk_delayed_t(X) <= nx_frame_clk_delayed_t(X - 1); end loop; + + -- Output + nx_timestamp_delayed_clk <= + nx_frame_clk_delayed_t(to_integer(nx_frame_word_delay)); + nx_timestamp_delayed <= + nx_frame_word_delayed_t(to_integer(nx_frame_word_delay)); end if; end process PROC_NX_TIMESTAMP_FRAME_DELAY; - PROC_NX_TIMESTAMP_DELAY: process(NX_TIMESTAMP_CLK_IN) - begin - if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then - nx_timestamp_delay <= nx_timestamp_delay_r; - - if (nx_frame_clk_delayed_t(to_integer(nx_frame_word_delay)) = '1') then - - nx_timestamp_delayed_s1(0) <= nx_frame_word_delayed_t(3); - -- First Stage Delay S1_PIPE_LEN steps - for I in 1 to S1_PIPE_LEN loop - nx_timestamp_delayed_s1(I) <= nx_timestamp_delayed_s1(I - 1); - end loop; - - -- Second Stage Delay 0...S2_PIPE_LEN steps - nx_timestamp_delayed_s2(0) <= nx_timestamp_delayed_s1(S1_PIPE_LEN); - for X in 1 to S2_PIPE_LEN loop - nx_timestamp_delayed_s2(X) <= nx_timestamp_delayed_s2(X - 1); - end loop; - - nx_timestamp_delayed <= - nx_timestamp_delayed_s2(to_integer(nx_timestamp_delay)); - nx_timestamp_delayed_clk <= '1'; - else - nx_timestamp_delayed <= x"deadaffe"; - nx_timestamp_delayed_clk <= '0'; - end if; - end if; - end process PROC_NX_TIMESTAMP_DELAY; - PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then + nx_frame_word_delay <= nx_frame_word_delay_f; adc_data_clk_last(0) <= adc_data_s_clk; -- Register Info - nx_frame_word_delay_r <= nx_frame_word_delay; + nx_frame_word_delay_r <= nx_frame_word_delay; if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - nx_frame_word_delay <= "10"; + nx_frame_word_delay_f <= "10"; adc_data_clk_last(3 downto 1) <= (others => '0'); frame_word_delay_change <= '0'; frame_word_delay_set <= '0'; @@ -877,15 +872,15 @@ begin if (nx_timestamp_delayed_clk = '1') then case adc_data_clk_last is when "0100" => - nx_frame_word_delay <= nx_frame_word_delay + 1; + nx_frame_word_delay_f <= nx_frame_word_delay_f + 1; frame_word_delay_change <= '1'; when "0010" => - nx_frame_word_delay <= nx_frame_word_delay + 2; + nx_frame_word_delay_f <= nx_frame_word_delay_f + 2; frame_word_delay_change <= '1'; when "0001" => - nx_frame_word_delay <= nx_frame_word_delay + 3; + nx_frame_word_delay_f <= nx_frame_word_delay_f + 3; frame_word_delay_change <= '1'; when others => @@ -905,7 +900,7 @@ begin -- ADC Input Handler ----------------------------------------------------------------------------- - ADC_RESET_AD9228 <= RESET_NX_TIMESTAMP_CLK_IN or reset_handler_start_r; --adc_reset; + ADC_RESET_AD9228 <= RESET_NX_TIMESTAMP_CLK_IN or adc_reset_handler; adc_ad9228_1: adc_ad9228 port map ( CLK_IN => NX_TIMESTAMP_CLK_IN, @@ -955,25 +950,20 @@ begin variable adcval : unsigned(11 downto 0) := (others => '0'); begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - adc_data_s <= (others => '0'); - adc_data_s_clk <= '0'; + if (adc_bit_shift(3) = '1') then + adcval := unsigned(adc_data) rol + to_integer(adc_bit_shift(2 downto 0)); else - if (adc_bit_shift(3) = '1') then - adcval := unsigned(adc_data) rol - to_integer(adc_bit_shift(2 downto 0)); - else - adcval := unsigned(adc_data) ror - to_integer(adc_bit_shift(2 downto 0)); - end if; + adcval := unsigned(adc_data) ror + to_integer(adc_bit_shift(2 downto 0)); + end if; - if (adc_data_clk = '1') then - adc_data_s <= std_logic_vector(adcval); - adc_data_s_clk <= '1'; - else - adc_data_s <= x"aff"; - adc_data_s_clk <= '0'; - end if; + if (adc_data_clk = '1') then + adc_data_s <= std_logic_vector(adcval); + adc_data_s_clk <= '1'; + else + adc_data_s <= x"aff"; + adc_data_s_clk <= '0'; end if; end if; end process PROC_ADC_DATA_BIT_SHIFT; @@ -985,9 +975,7 @@ begin PROC_DATA_MERGE_HANDLER: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1' ) then --r output_handler_reset = '1') then - data_frame <= (others => '0'); - data_frame_clk <= '0'; + if (RESET_NX_TIMESTAMP_CLK_IN = '1' or output_handler_reset = '1') then merge_timeout_ctr <= (others => '0'); merge_timeout_error <= '0'; merge_error_ctr <= (others => '0'); @@ -1031,7 +1019,7 @@ begin Empty => fifo_empty, Full => fifo_full ); - fifo_reset_i <= RESET_IN or fifo_reset; + fifo_reset_i <= RESET_IN or fifo_reset_handler; fifo_write_enable <= not fifo_full and data_frame_clk; fifo_read_enable <= not fifo_empty; @@ -1054,18 +1042,15 @@ begin begin if (rising_edge(CLK_IN) ) then if(RESET_IN = '1') then - nx_timestamp_o <= (others => '0'); - adc_data_o <= (others => '0'); + data_o <= (others => '0'); data_clk_o <= '0'; else if (fifo_data_clk = '1') then - nx_timestamp_o <= fifo_data(31 downto 0); - adc_data_o <= fifo_data(43 downto 32); - data_clk_o <= '1'; + data_o <= fifo_data; + data_clk_o <= '1'; else - nx_timestamp_o <= (others => '0'); - adc_data_o <= (others => '0'); - data_clk_o <= '0'; + data_o <= (others => '0'); + data_clk_o <= '0'; end if; end if; end if; @@ -1183,7 +1168,7 @@ begin end if; end if; end process PROC_RATE_COUNTER; - + -- Check Rates for errors PROC_RATE_ERRORS: process(CLK_IN) begin @@ -1243,33 +1228,91 @@ begin end if; end process PROC_RATE_ERRORS; + ----------------------------------------------------------------------------- + pulse_dtrans_ADC_DT_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + PULSE_A_IN => adc_dt_error_p, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_dt_error_c100 + ); + + pulse_dtrans_TIMESTAMP_DT_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + PULSE_A_IN => timestamp_dt_error_p, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => timestamp_dt_error_c100 + ); + + PROC_EVENT_ERRORS_PER_SECOND: process(CLK_IN) + begin + if (rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or frame_rates_reset = '1') then + adc_dt_error_cur <= '0'; + adc_dt_error <= '0'; + timestamp_dt_error_cur <= '0'; + timestamp_dt_error <= '0'; + else + if (rate_timer_ctr < x"5f5e100") then + if (adc_dt_error_c100 = '1') then + adc_dt_error_cur <= '1'; + end if; + if (timestamp_dt_error_c100 = '1') then + timestamp_dt_error_cur <= '1'; + end if; + else + adc_dt_error <= adc_dt_error_cur; + timestamp_dt_error <= timestamp_dt_error_cur; + adc_dt_error_cur <= '0'; + timestamp_dt_error_cur <= '0'; + end if; + end if; + end if; + end process PROC_EVENT_ERRORS_PER_SECOND; + PROC_DATA_STREAM_DELTA_T: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - new_adc_delta_t_ctr <= (others => '0'); - new_timestamp_delta_t_ctr <= (others => '0'); + new_adc_dt_ctr <= (others => '0'); + new_timestamp_dt_ctr <= (others => '0'); new_adc_dt_error_ctr <= (others => '0'); new_timestamp_dt_error_ctr <= (others => '0'); else + adc_dt_error_p <= '0'; + timestamp_dt_error_p <= '0'; + -- ADC if (adc_data_clk = '1') then - if (new_adc_delta_t_ctr /= x"3" ) then + if (new_adc_dt_ctr /= x"3" ) then new_adc_dt_error_ctr <= new_adc_dt_error_ctr + 1; + adc_dt_error_p <= '1'; end if; - new_adc_delta_t_ctr <= (others => '0'); + new_adc_dt_ctr <= (others => '0'); else - new_adc_delta_t_ctr <= new_adc_delta_t_ctr + 1; + new_adc_dt_ctr <= new_adc_dt_ctr + 1; end if; -- TimeStamp if (nx_frame_clk = '1') then - if (new_timestamp_delta_t_ctr /= x"3") then + if (new_timestamp_dt_ctr /= x"3") then new_timestamp_dt_error_ctr <= new_timestamp_dt_error_ctr + 1; + timestamp_dt_error_p <= '1'; end if; - new_timestamp_delta_t_ctr <= (others => '0'); + new_timestamp_dt_ctr <= (others => '0'); else - new_timestamp_delta_t_ctr <= new_timestamp_delta_t_ctr + 1; + new_timestamp_dt_ctr <= new_timestamp_dt_ctr + 1; end if; end if; @@ -1285,10 +1328,10 @@ begin if (rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then frame_rates_reset <= '0'; - fifo_reset <= '0'; + fifo_reset_handler <= '0'; sampling_clk_reset <= '0'; adc_reset_p <= '0'; - adc_reset <= '0'; + adc_reset_handler <= '0'; output_handler_reset <= '0'; rs_wait_timer_start <= '0'; @@ -1302,10 +1345,10 @@ begin R_STATE <= R_IDLE; else frame_rates_reset <= '0'; - fifo_reset <= '0'; + fifo_reset_handler <= '0'; sampling_clk_reset <= '0'; adc_reset_p <= '0'; - adc_reset <= '0'; + adc_reset_handler <= '0'; output_handler_reset <= '0'; rs_wait_timer_start <= '0'; @@ -1314,16 +1357,17 @@ begin reset_handler_busy <= '1'; nx_timestamp_reset_o <= '0'; - debug_state <= x"0"; - - if (reset_handler_counter_clear = '1') then - reset_handler_counter <= (others => '0'); - end if; + debug_state <= x"0"; - if (rs_timeout_timer_done = '1') then - -- Reset Timeout + if (reset_handler_start_r = '1') then + -- Reset by register always wins, start it + rs_timeout_timer_reset <= '1'; + R_STATE <= R_SET_ALL_RESETS; + elsif (rs_timeout_timer_done = '1') then + -- Reset Timeout, retry RESET + rs_timeout_timer_reset <= '1'; reset_timeout_flag <= '1'; - R_STATE <= R_IDLE; + R_STATE <= R_SET_ALL_RESETS; else case R_STATE is @@ -1331,43 +1375,40 @@ begin if (reset_for_offline = '1' or pll_adc_not_lock = '1' or adc_reset_sync = '1' or - reset_handler_start_r = '1' or startup_reset = '1' ) then - if (reset_handler_counter_clear = '0') then - reset_handler_counter <= reset_handler_counter + 1; - end if; R_STATE <= R_SET_ALL_RESETS; else + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; reset_handler_busy <= '0'; R_STATE <= R_IDLE; end if; - + when R_SET_ALL_RESETS => frame_rates_reset <= '1'; - fifo_reset <= '1'; + fifo_reset_handler <= '1'; sampling_clk_reset <= '1'; adc_reset_p <= '1'; - adc_reset <= '1'; + adc_reset_handler <= '1'; output_handler_reset <= '1'; - nx_timestamp_reset_o <= '1'; - rs_wait_timer_start <= '1'; -- wait 1mue to settle R_STATE <= R_WAIT_1; debug_state <= x"1"; + reset_handler_counter <= reset_handler_counter + 1; when R_WAIT_1 => if (rs_wait_timer_done = '0') then - fifo_reset <= '1'; + fifo_reset_handler <= '1'; sampling_clk_reset <= '1'; - adc_reset <= '1'; + adc_reset_handler <= '1'; output_handler_reset <= '1'; R_STATE <= R_WAIT_1; else -- Release NX Fifo Reset + Start Timeout Handler sampling_clk_reset <= '1'; - adc_reset <= '1'; + adc_reset_handler <= '1'; output_handler_reset <= '1'; rs_timeout_timer_start <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; @@ -1378,12 +1419,12 @@ begin if (nx_frame_rate_offline = '0' and nx_frame_rate_error = '0') then -- Release PLL Reset - adc_reset <= '1'; + adc_reset_handler <= '1'; output_handler_reset <= '1'; R_STATE <= R_PLL_WAIT_LOCK; else sampling_clk_reset <= '1'; - adc_reset <= '1'; + adc_reset_handler <= '1'; output_handler_reset <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; @@ -1391,7 +1432,7 @@ begin when R_PLL_WAIT_LOCK => if (pll_adc_not_lock = '1') then - adc_reset <= '1'; + adc_reset_handler <= '1'; output_handler_reset <= '1'; R_STATE <= R_PLL_WAIT_LOCK; else @@ -1417,12 +1458,12 @@ begin startup_reset <= '0'; reset_timeout_flag <= '0'; rs_timeout_timer_reset <= '1'; + nx_timestamp_reset_o <= '1'; R_STATE <= R_IDLE; else R_STATE <= R_WAIT_DATA_HANDLER_OK; end if; debug_state <= x"6"; - end case; end if; end if; @@ -1439,33 +1480,24 @@ begin error_status_bits <= (others => '0'); error_o <= '0'; else - if (error_adc0 = '1' or - pll_adc_not_lock = '1' or - nx_frame_rate_offline = '1' or - nx_frame_rate_error = '1' or - adc_clk_ok_c100 = '0' or - parity_error_c100 = '1' or - reg_nx_frame_synced = '0' or - adc_frame_rate_error = '1' or - parity_rate_error = '1' - ) then - error_o <= '1'; + error_status_bits(0) <= nx_frame_rate_offline; + error_status_bits(1) <= frame_rate_error; + error_status_bits(2) <= nx_frame_rate_error; + error_status_bits(3) <= adc_frame_rate_error; + error_status_bits(4) <= parity_rate_error; + error_status_bits(5) <= not reg_nx_frame_synced; + error_status_bits(6) <= error_adc0; + error_status_bits(7) <= pll_adc_not_lock; + error_status_bits(8) <= not adc_clk_ok_c100; + error_status_bits(9) <= timestamp_dt_error; + error_status_bits(10) <= adc_dt_error; + error_status_bits(11) <= reset_handler_busy; + + if (error_status_bits = x"000") then + error_o <= '0'; else - error_o <= '0'; + error_o <= '1'; end if; - - error_status_bits(0) <= nx_frame_rate_offline; - error_status_bits(1) <= frame_rate_error; - error_status_bits(2) <= nx_frame_rate_error; - error_status_bits(3) <= adc_frame_rate_error; - error_status_bits(4) <= parity_rate_error; - error_status_bits(5) <= not reg_nx_frame_synced; - error_status_bits(6) <= error_adc0; - error_status_bits(7) <= pll_adc_not_lock; - error_status_bits(8) <= not adc_clk_ok_c100; - error_status_bits(9) <= '0'; - error_status_bits(10) <= '0'; - error_status_bits(11) <= '0'; end if; end if; end process PROC_ERROR_STATUS; @@ -1487,16 +1519,17 @@ begin reset_parity_error_ctr <= '0'; debug_mode <= (others => '0'); johnson_counter_sync_r <= "00"; - pll_adc_sample_clk_dphase_r <= x"0"; + pll_adc_sample_clk_dphase_r <= x"d"; pll_adc_sample_clk_finedelb_r <= (others => '0'); pll_adc_not_lock_ctr_clear <= '0'; nx_timestamp_delay_r <= "010"; reset_handler_start_r <= '0'; - reset_handler_counter_clear <= '0'; adc_bit_shift <= x"0"; adc_debug_type <= (others => '0'); fifo_full_r <= '0'; fifo_empty_r <= '0'; + new_adc_dt_error_ctr_r <= (others => '0'); + new_timestamp_dt_error_ctr_r <= (others => '0'); else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -1506,15 +1539,17 @@ begin reset_parity_error_ctr <= '0'; pll_adc_not_lock_ctr_clear <= '0'; reset_handler_start_r <= '0'; - reset_handler_counter_clear <= '0'; fifo_full_r <= fifo_full; fifo_empty_r <= fifo_empty; + new_adc_dt_error_ctr_r <= new_adc_dt_error_ctr; + new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr; + adc_notlock_ctr_r <= adc_notlock_ctr; if (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => slv_data_out_o(11 downto 0) <= error_status_bits; - slv_data_out_o(31 downto 8) <= (others => '0'); + slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"0001" => @@ -1555,7 +1590,7 @@ begin when x"0008" => slv_data_out_o(7 downto 0) <= - std_logic_vector(adc_notlock_ctr); + std_logic_vector(adc_notlock_ctr_r); slv_data_out_o(31 downto 8) <= (others => '0'); slv_ack_o <= '1'; @@ -1625,22 +1660,21 @@ begin slv_ack_o <= '1'; when x"0013" => - slv_data_out_o <= (others => '0');--nx_timestamp_t; + slv_data_out_o <= (others => '0'); slv_ack_o <= '1'; when x"0014" => - slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr; + slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr_r; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"0015" => - slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr; + slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr_r; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"001c" => - slv_data_out_o(11 downto 0) <= adc_data_o; - slv_data_out_o(31 downto 12) <= (others => '0'); + slv_data_out_o <= (others => '0'); slv_ack_o <= '1'; when x"001e" => @@ -1664,7 +1698,6 @@ begin slv_ack_o <= '1'; when x"0002" => - reset_handler_counter_clear <= '1'; slv_ack_o <= '1'; when x"000a" => @@ -1691,13 +1724,16 @@ begin slv_ack_o <= '1'; when x"000f" => - johnson_counter_sync_r <= SLV_DATA_IN(1 downto 0); + johnson_counter_sync_r + <= unsigned(SLV_DATA_IN(1 downto 0)) + 1; reset_handler_start_r <= '1'; slv_ack_o <= '1'; when x"0010" => - nx_timestamp_delay_r <= - unsigned(SLV_DATA_IN(2 downto 0)); + if (unsigned(SLV_DATA_IN(2 downto 0)) < 5) then + nx_timestamp_delay_r <= + unsigned(SLV_DATA_IN(2 downto 0)); + end if; slv_ack_o <= '1'; when x"0012" => @@ -1725,8 +1761,7 @@ begin -- Output Signals NX_TIMESTAMP_RESET_OUT <= nx_timestamp_reset_o; - NX_TIMESTAMP_OUT <= nx_timestamp_o; - ADC_DATA_OUT <= adc_data_o; + DATA_OUT <= data_o; DATA_CLK_OUT <= data_clk_o; ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock; ERROR_OUT <= error_o; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index 419b7eb..476da03 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -12,8 +12,7 @@ entity nx_data_validate is RESET_IN : in std_logic; -- Inputs - NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); + DATA_IN : in std_logic_vector(43 downto 0); DATA_CLK_IN : in std_logic; -- Outputs @@ -64,7 +63,8 @@ architecture Behavioral of nx_data_validate is signal nx_token_return_o : std_logic; signal nx_nomore_data_o : std_logic; - + + signal parity_error_ctr : unsigned(15 downto 0); signal invalid_frame_ctr : unsigned(15 downto 0); signal overflow_ctr : unsigned(15 downto 0); signal pileup_ctr : unsigned(15 downto 0); @@ -94,14 +94,11 @@ architecture Behavioral of nx_data_validate is signal adc_data_last : std_logic_vector(11 downto 0); -- Token Return Average - signal adc_tr_data_p : std_logic_vector(11 downto 0); - signal adc_tr_data_c : std_logic_vector(11 downto 0); + signal nx_token_return_pipe : std_logic_vector(4 downto 0); + signal adc_tr_value : std_logic_vector(11 downto 0); + signal adc_tr_data_p : unsigned(11 downto 0); + signal adc_tr_data_c : unsigned(11 downto 0); signal adc_tr_data_clk : std_logic; - signal adc_tr_average_divisor : unsigned(7 downto 0); - signal adc_tr_average_ctr : unsigned(15 downto 0); - signal adc_tr_average_sum : unsigned(31 downto 0); - signal adc_tr_average : unsigned(11 downto 0); - signal adc_tr_mean : unsigned(11 downto 0); signal adc_tr_limit : unsigned(11 downto 0); signal adc_tr_error_ctr : unsigned(11 downto 0); signal adc_tr_error : std_logic; @@ -126,7 +123,13 @@ architecture Behavioral of nx_data_validate is signal nx_overflow_rate : unsigned(27 downto 0); signal adc_tr_error_rate : unsigned(27 downto 0); signal invalid_adc : std_logic; - + signal adc_tr_value_r : std_logic_vector(11 downto 0); + + signal adc_tr_debug_p : std_logic; + signal adc_tr_debug_c : std_logic; + + signal lower_limit_r : std_logic_vector(11 downto 0); + begin -- Debug Line @@ -134,20 +137,45 @@ begin DEBUG_OUT(1) <= DATA_CLK_IN; DEBUG_OUT(2) <= nx_token_return_o; DEBUG_OUT(3) <= nx_nomore_data_o; - - --DEBUG_OUT(15 downto 4) <= adc_data; - DEBUG_OUT(4) <= data_clk_o; DEBUG_OUT(5) <= new_timestamp; DEBUG_OUT(6) <= self_trigger_o; DEBUG_OUT(7) <= invalid_adc; DEBUG_OUT(8) <= adc_tr_data_clk; DEBUG_OUT(9) <= adc_tr_error; - DEBUG_OUT(15 downto 10) <= channel_o(5 downto 0); + DEBUG_OUT(11 downto 10) <= adc_tr_error_status; + DEBUG_OUT(12) <= adc_tr_debug_p; + DEBUG_OUT(13) <= adc_tr_debug_c; + DEBUG_OUT(14) <= '0'; + DEBUG_OUT(15) <= parity_error; + ----------------------------------------------------------------------------- -- Data Separation ----------------------------------------------------------------------------- + + gray_decoder_TIMESTAMP: gray_decoder -- Decode nx_timestamp + generic map ( + WIDTH => 14 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + GRAY_IN(13 downto 7) => not DATA_IN(30 downto 24), + GRAY_IN( 6 downto 0) => not DATA_IN(22 downto 16), + BINARY_OUT => nx_timestamp + ); + + gray_decoder_CHANNEL_ID: gray_decoder -- Decode Channel_ID + generic map ( + WIDTH => 7 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + GRAY_IN => DATA_IN(14 downto 8), + BINARY_OUT => nx_channel_id + ); -- Separate Timestamp-, Status-, Parity- and Frame-bits PROC_TIMESTAMP_BITS: process (CLK_IN) @@ -155,31 +183,21 @@ begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then valid_frame_bits <= (others => '0'); - nx_timestamp <= (others => '0'); - nx_channel_id <= (others => '0'); status_bits <= (others => '0'); - parity_error <= '0'; new_timestamp <= '0'; adc_data <= (others => '0'); else if (DATA_CLK_IN = '1') then - valid_frame_bits(3) <= NX_TIMESTAMP_IN(31); - valid_frame_bits(2) <= NX_TIMESTAMP_IN(23); - valid_frame_bits(1) <= NX_TIMESTAMP_IN(15); - valid_frame_bits(0) <= NX_TIMESTAMP_IN(7); - nx_timestamp(13 downto 7) <= NX_TIMESTAMP_IN(30 downto 24); - nx_timestamp(6 downto 0) <= NX_TIMESTAMP_IN(22 downto 16); - nx_channel_id <= NX_TIMESTAMP_IN(14 downto 8); - status_bits <= NX_TIMESTAMP_IN(2 downto 1); - parity_error <= NX_TIMESTAMP_IN(0); - adc_data <= ADC_DATA_IN; + valid_frame_bits(3) <= DATA_IN(31); + valid_frame_bits(2) <= DATA_IN(23); + valid_frame_bits(1) <= DATA_IN(15); + valid_frame_bits(0) <= DATA_IN(7); + status_bits <= DATA_IN(2 downto 1); + adc_data <= DATA_IN(43 downto 32); new_timestamp <= '1'; else valid_frame_bits <= (others => '0'); - nx_timestamp <= (others => '0'); - nx_channel_id <= (others => '0'); status_bits <= (others => '0'); - parity_error <= '0'; adc_data <= (others => '0'); new_timestamp <= '0'; end if; @@ -187,6 +205,36 @@ begin end if; end process PROC_TIMESTAMP_BITS; + -- Check Parity Bit + PROC_PARITY_CHECKER: process(CLK_IN) + variable parity_bits : std_logic_vector(22 downto 0); + variable parity : std_logic; + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + parity_error <= '0'; + else + if (DATA_CLK_IN = '1') then + -- Timestamp Bit #6 is excluded (funny nxyter-bug) + parity_bits := DATA_IN(31) & + DATA_IN(30 downto 24) & + DATA_IN(21 downto 16) & + DATA_IN(14 downto 8) & + DATA_IN( 2 downto 1); + parity := xor_all(parity_bits); + + if (parity /= DATA_IN(0)) then + parity_error <= '1'; + else + parity_error <= '0'; + end if; + else + parity_error <= '0'; + end if; + end if; + end if; + end process PROC_PARITY_CHECKER; + ----------------------------------------------------------------------------- -- Filter only valid events ----------------------------------------------------------------------------- @@ -206,6 +254,7 @@ begin frame_rate_inc <= '0'; pileup_rate_inc <= '0'; overflow_rate_inc <= '0'; + parity_error_ctr <= (others => '0'); invalid_frame_ctr <= (others => '0'); overflow_ctr <= (others => '0'); pileup_ctr <= (others => '0'); @@ -228,7 +277,11 @@ begin adc_tr_data_clk <= '0'; if (new_timestamp = '1') then + adc_data_last <= adc_data; + if (parity_error = '1') then + parity_error_ctr <= parity_error_ctr + 1; + end if; case valid_frame_bits is @@ -254,7 +307,7 @@ begin if (adc_tr_debug_mode = '0') then adc_data_o <= adc_data; else - adc_data_o <= adc_tr_data_p; + adc_data_o <= std_logic_vector(adc_tr_data_p); end if; data_clk_o <= '1'; @@ -268,13 +321,13 @@ begin if (nx_token_return_o = '1') then -- First Data Word after empty Frame - adc_tr_data_p <= adc_data_last; - adc_tr_data_c <= adc_data; + adc_tr_data_p <= unsigned(adc_data_last); + adc_tr_data_c <= unsigned(adc_data); adc_tr_data_clk <= '1'; end if; - - -- Token return and nomore_data + when "0000" => + -- Token return and nomore_data nx_token_return_o <= '1'; nx_nomore_data_o <= nx_token_return_o; @@ -289,7 +342,18 @@ begin end case; frame_rate_inc <= '1'; - + + -- Token Return Pipeline + nx_token_return_pipe(0) <= nx_token_return_o; + for I in 1 to 4 loop + nx_token_return_pipe(I) <= nx_token_return_pipe(I - 1); + end loop; + + -- Store ADC Value after 5 consecutive empty Frames + if (nx_token_return_pipe = "11111") then + adc_tr_value <= adc_data_last; + end if; + else nx_token_return_o <= nx_token_return_o; nx_nomore_data_o <= nx_nomore_data_o; @@ -390,59 +454,55 @@ begin end process PROC_ADC_AVERAGE; PROC_ADC_TOKEN_RETURN: process(CLK_IN) - variable lower_limit : unsigned(11 downto 0); - variable upper_limit : unsigned(11 downto 0); - + variable lower_limit : unsigned(11 downto 0); begin if (rising_edge(CLK_IN) ) then if (RESET_IN = '1') then - adc_tr_average_ctr <= (others => '0'); - adc_tr_average_sum <= (others => '0'); - adc_tr_average <= (others => '0'); - adc_tr_error_ctr <= (others => '0'); adc_tr_error <= '0'; + adc_tr_debug_p <= '0'; + adc_tr_debug_c <= '0'; + adc_tr_error_status <= "00"; else - upper_limit := adc_tr_mean + adc_tr_limit; - lower_limit := adc_tr_mean - adc_tr_limit; - adc_tr_error <= '0'; + lower_limit := unsigned(adc_tr_value) - adc_tr_limit; + adc_tr_error <= '0'; + + lower_limit_r <= lower_limit; if (adc_tr_data_clk = '1') then - if (unsigned(adc_tr_data_p) <= upper_limit and - unsigned(adc_tr_data_p) >= lower_limit) then - -- Empty token value is O.K., check next one - if (unsigned(adc_tr_data_c) > lower_limit) then - -- Following Value is not low enough, increase bit shift by one - adc_tr_error_ctr <= adc_tr_error_ctr + 1; - adc_tr_error_status <= "10"; - adc_tr_error <= '1'; - else - adc_tr_error_status <= "00"; - end if; + + if (adc_tr_data_p < x"92e") then -- 2350 + adc_tr_debug_p <= '1'; else - -- Empty token value is not low enough, decrease bit shift by one - adc_tr_error_ctr <= adc_tr_error_ctr + 1; - adc_tr_error_status <= "01"; - adc_tr_error <= '1'; + adc_tr_debug_p <= '0'; end if; - end if; - - if (adc_tr_average_ctr srl to_integer(adc_average_divisor) > 0) then - adc_tr_average <= - (adc_tr_average_sum srl - to_integer(adc_average_divisor))(11 downto 0); - if (adc_tr_data_clk = '1') then - adc_tr_average_sum(11 downto 0) <= unsigned(adc_tr_data_p); - adc_tr_average_sum(31 downto 12) <= (others => '0'); - adc_tr_average_ctr <= x"0001"; + + if (adc_tr_data_c < x"92e") then + adc_tr_debug_c <= '1'; else - adc_tr_average_sum <= (others => '0'); - adc_tr_average_ctr <= (others => '0'); + adc_tr_debug_c <= '0'; + end if; + + if (adc_tr_data_p > lower_limit and + adc_tr_data_c < lower_limit) then + adc_tr_error_status <= "00"; + adc_tr_error <= '0'; + + elsif (adc_tr_data_p > lower_limit and + adc_tr_data_c > lower_limit) then + adc_tr_error_status <= "01"; + adc_tr_error <= '1'; + + elsif (adc_tr_data_p < lower_limit and + adc_tr_data_c < lower_limit) then + adc_tr_error_status <= "10"; + adc_tr_error <= '1'; + + elsif (adc_tr_data_p < lower_limit and + adc_tr_data_c > lower_limit) then + adc_tr_error_status <= "11"; + adc_tr_error <= '1'; end if; - elsif (adc_tr_data_clk = '1') then - adc_tr_average_sum <= - adc_tr_average_sum + unsigned(adc_tr_data_p); - adc_tr_average_ctr <= adc_tr_average_ctr + 1; end if; end if; @@ -473,6 +533,7 @@ begin PROC_FIFO_REGISTERS: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then + adc_tr_value_r <= adc_tr_value; if( RESET_IN = '1' ) then slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -481,8 +542,6 @@ begin clear_counters <= '0'; adc_average_divisor <= x"3"; - adc_tr_average_divisor <= x"00"; - adc_tr_mean <= x"8f2"; -- 2290 adc_tr_limit <= x"014"; -- 20 adc_tr_debug_mode <= '0'; else @@ -490,7 +549,7 @@ begin slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; clear_counters <= '0'; - + if (SLV_READ_IN = '1') then case SLV_ADDR_IN is @@ -531,7 +590,7 @@ begin when x"0006" => slv_data_out_o(1 downto 0) <= adc_tr_error_status; - slv_data_out_o(31 downto 8) <= (others => '0'); + slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; when x"0007" => @@ -541,15 +600,14 @@ begin slv_ack_o <= '1'; when x"0008" => - slv_data_out_o(11 downto 0) - <= std_logic_vector(adc_tr_average); + slv_data_out_o(11 downto 0) <= adc_tr_value_r; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"0009" => - slv_data_out_o(11 downto 0) - <= std_logic_vector(adc_tr_mean); - slv_data_out_o(31 downto 12) <= (others => '0'); + slv_data_out_o(15 downto 0) + <= std_logic_vector(parity_error_ctr); + slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; when x"000a" => @@ -603,11 +661,6 @@ begin adc_average_divisor <= SLV_DATA_IN(3 downto 0); slv_ack_o <= '1'; - when x"0009" => - adc_tr_mean - <= unsigned(SLV_DATA_IN(11 downto 0)); - slv_ack_o <= '1'; - when x"000a" => adc_tr_limit <= unsigned(SLV_DATA_IN(11 downto 0)); diff --git a/nxyter/source/nx_fpga_timestamp.vhd b/nxyter/source/nx_fpga_timestamp.vhd index b9ab20e..5db6dbd 100644 --- a/nxyter/source/nx_fpga_timestamp.vhd +++ b/nxyter/source/nx_fpga_timestamp.vhd @@ -11,10 +11,10 @@ entity nx_fpga_timestamp is RESET_IN : in std_logic; NX_MAIN_CLK_IN : in std_logic; - TIMESTAMP_RESET_IN : in std_logic; + TIMESTAMP_RESET_1_IN : in std_logic; + TIMESTAMP_RESET_2_IN : in std_logic; TIMESTAMP_RESET_OUT : out std_logic; TRIGGER_IN : in std_logic; -- must be in NX_MAIN_CLK_DOMAIN - TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); TIMESTAMP_TRIGGER_OUT : out std_logic; @@ -34,25 +34,29 @@ end entity; architecture Behavioral of nx_fpga_timestamp is - signal timestamp_reset : std_logic; + signal timestamp_reset_1_ff : std_logic; + signal timestamp_reset_1_f : std_logic; + signal timestamp_reset_1 : std_logic; + signal timestamp_reset_2_ff : std_logic; + signal timestamp_reset_2_f : std_logic; + signal timestamp_reset_2 : std_logic; signal timestamp_ctr : unsigned(11 downto 0); - signal timestamp_current_o : unsigned(11 downto 0); signal timestamp_hold_o : std_logic_vector(11 downto 0); signal timestamp_trigger_o : std_logic; - signal timestamp_reset_o : std_logic; + signal timestamp_sync_o : std_logic; -- Reset signal RESET_NX_MAIN_CLK_IN : std_logic; begin - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= TIMESTAMP_RESET_IN; - DEBUG_OUT(2) <= TIMESTAMP_RESET_OUT; - DEBUG_OUT(3) <= TRIGGER_IN; - - DEBUG_OUT(15 downto 4) <= timestamp_hold_o(11 downto 0); + DEBUG_OUT(0) <= NX_MAIN_CLK_IN; + DEBUG_OUT(1) <= TIMESTAMP_RESET_1_IN; + DEBUG_OUT(2) <= TIMESTAMP_RESET_2_IN; + DEBUG_OUT(3) <= TIMESTAMP_RESET_OUT; + DEBUG_OUT(4) <= TRIGGER_IN; + DEBUG_OUT(15 downto 5) <= timestamp_hold_o(10 downto 0); ----------------------------------------------------------------------------- -- Reset Domain Transfer @@ -67,52 +71,52 @@ begin ----------------------------------------------------------------------------- -- NX Clock Domain ----------------------------------------------------------------------------- - - signal_async_to_pulse_TIMESTAMP_SYNC_IN: signal_async_to_pulse - generic map ( - NUM_FF => 3 - ) - port map ( - CLK_IN => NX_MAIN_CLK_IN, - RESET_IN => RESET_NX_MAIN_CLK_IN, - PULSE_A_IN => TIMESTAMP_RESET_IN, - PULSE_OUT => timestamp_reset - ); - + -- Timestamp Process + Trigger PROC_TIMESTAMP_CTR: process (NX_MAIN_CLK_IN) begin if (rising_edge(NX_MAIN_CLK_IN)) then + timestamp_reset_1_ff <= TIMESTAMP_RESET_1_IN; + timestamp_reset_2_ff <= TIMESTAMP_RESET_2_IN; + if (RESET_NX_MAIN_CLK_IN = '1') then - timestamp_ctr <= (others => '0'); - timestamp_hold_o <= (others => '0'); - timestamp_reset_o <= '0'; + timestamp_reset_1_f <= '0'; + timestamp_reset_2_f <= '0'; + timestamp_reset_1 <= '0'; + timestamp_reset_2 <= '0'; + + timestamp_ctr <= (others => '0'); + timestamp_hold_o <= (others => '0'); + timestamp_sync_o <= '0'; else - timestamp_trigger_o <= '1'; - timestamp_reset_o <= '0'; + timestamp_reset_1_f <= timestamp_reset_1_ff; + timestamp_reset_1 <= timestamp_reset_1_f; + timestamp_reset_2_f <= timestamp_reset_2_ff; + timestamp_reset_2 <= timestamp_reset_2_f; + timestamp_trigger_o <= '1'; + timestamp_sync_o <= '0'; - if (timestamp_reset = '1') then - timestamp_ctr <= (others => '0'); - timestamp_reset_o <= '1'; + if ((timestamp_reset_1 = '0' and timestamp_reset_1_f = '1') or + (timestamp_reset_2 = '0' and timestamp_reset_2_f = '1'))then + timestamp_ctr <= (others => '0'); + timestamp_sync_o <= '1'; else if (TRIGGER_IN = '1') then - timestamp_hold_o <= std_logic_vector(timestamp_ctr); - timestamp_trigger_o <= '1'; + timestamp_hold_o <= std_logic_vector(timestamp_ctr); + timestamp_trigger_o <= '1'; end if; - timestamp_ctr <= timestamp_ctr + 1; + -- Increase TS Counter + timestamp_ctr <= timestamp_ctr + 1; end if; end if; end if; end process PROC_TIMESTAMP_CTR; - timestamp_current_o <= timestamp_ctr; - ----------------------------------------------------------------------------- -- Output Signals ----------------------------------------------------------------------------- - TIMESTAMP_RESET_OUT <= timestamp_reset_o; - TIMESTAMP_CURRENT_OUT <= timestamp_current_o; + TIMESTAMP_RESET_OUT <= timestamp_sync_o; TIMESTAMP_HOLD_OUT <= timestamp_hold_o; TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o; diff --git a/nxyter/source/nx_status.vhd b/nxyter/source/nx_status.vhd index a61a62c..3ec8d8b 100644 --- a/nxyter/source/nx_status.vhd +++ b/nxyter/source/nx_status.vhd @@ -21,7 +21,7 @@ entity nx_status is I2C_REG_RESET_OUT : out std_logic; NX_TS_RESET_OUT : out std_logic; NX_ONLINE_OUT : out std_logic; - + -- Error ERROR_ALL_IN : in std_logic_vector(7 downto 0); @@ -53,7 +53,7 @@ architecture Behavioral of nx_status is signal online_trigger : std_logic; signal online_last : std_logic; - -- I2C Reset + -- Reset Handler signal i2c_sm_reset_start : std_logic; signal i2c_reg_reset_start : std_logic; signal nx_ts_reset_start : std_logic; @@ -104,7 +104,8 @@ architecture Behavioral of nx_status is signal slv_no_more_data_o : std_logic; signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - + signal nx_ts_reset_start_r : std_logic; + begin DEBUG_OUT(0) <= CLK_IN; @@ -212,6 +213,7 @@ begin PROC_I2C_SM_RESET: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then + nx_ts_reset_start <= nx_ts_reset_start_r; if( RESET_IN = '1' ) then wait_timer_start <= '0'; i2c_sm_reset_o <= '0'; @@ -226,12 +228,12 @@ begin case STATE is when S_IDLE => - if (i2c_sm_reset_start = '1') then + if (nx_ts_reset_start = '1') then + STATE <= S_NX_TS_RESET; + elsif (i2c_sm_reset_start = '1') then STATE <= S_I2C_SM_RESET; elsif (i2c_reg_reset_start = '1') then STATE <= S_I2C_REG_RESET; - elsif (nx_ts_reset_start = '1') then - STATE <= S_NX_TS_RESET; else STATE <= S_IDLE; end if; @@ -376,7 +378,7 @@ begin slv_ack_o <= '0'; i2c_sm_reset_start <= '0'; i2c_reg_reset_start <= '0'; - nx_ts_reset_start <= '0'; + nx_ts_reset_start_r <= '0'; offline_force <= '0'; nx_data_clk_dphase_o <= x"7"; nx_data_clk_finedelb_o <= x"0"; @@ -388,7 +390,7 @@ begin slv_data_out_o <= (others => '0'); i2c_sm_reset_start <= '0'; i2c_reg_reset_start <= '0'; - nx_ts_reset_start <= '0'; + nx_ts_reset_start_r <= '0'; clear_notlock_counters <= '0'; pll_reset_o <= '0'; @@ -403,7 +405,7 @@ begin slv_ack_o <= '1'; when x"0002" => - nx_ts_reset_start <= '1'; + nx_ts_reset_start_r <= '1'; slv_ack_o <= '1'; when x"0003" => diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 00789a0..a2547ea 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -13,13 +13,9 @@ entity nx_trigger_generator is TRIGGER_BUSY_IN : in std_logic; - TRIGGER_IN : in std_logic; -- must be in NX_MAIN_CLK_DOMAIN TRIGGER_OUT : out std_logic; - TS_RESET_OUT : out std_logic; - TESTPULSE_OUT : out std_logic; - TIMESTAMP_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); + DATA_IN : in std_logic_vector(43 downto 0); DATA_CLK_IN : in std_logic; SELF_TRIGGER_OUT : out std_logic; @@ -39,27 +35,6 @@ entity nx_trigger_generator is end entity; architecture Behavioral of nx_trigger_generator is - signal start_cycle : std_logic; - signal trigger_cycle_ctr : unsigned(7 downto 0); - signal wait_timer_start : std_logic; - signal wait_timer_init : unsigned(11 downto 0); - signal wait_timer_done : std_logic; - signal trigger_o : std_logic; - signal ts_reset_o : std_logic; - signal testpulse_o : std_logic; - signal testpulse_o_b : std_logic; - signal testpulse_p : std_logic; - signal extern_trigger : std_logic; - - type STATES is (S_IDLE, - S_WAIT_TESTPULSE_END - ); - signal STATE : STATES; - - -- Rate Calculation - signal testpulse : std_logic; - signal testpulse_rate_t : unsigned(27 downto 0); - signal rate_timer : unsigned(27 downto 0); -- Self Trigger @@ -79,29 +54,23 @@ architecture Behavioral of nx_trigger_generator is signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal reg_trigger_period : unsigned(15 downto 0); - signal reg_testpulse_length : unsigned(11 downto 0); - signal reg_trigger_num_cycles : unsigned(7 downto 0); - signal reg_ts_reset_on : std_logic; - signal testpulse_rate : unsigned(27 downto 0); - -- Reset - signal RESET_NX_MAIN_CLK_IN : std_logic; + signal RESET_NX_MAIN_CLK_IN : std_logic; + + signal new_data_frame_debug : std_logic; begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= DATA_CLK_IN; - DEBUG_OUT(2) <= start_cycle; - DEBUG_OUT(3) <= ts_reset_o; - DEBUG_OUT(4) <= testpulse_o_b; - DEBUG_OUT(5) <= testpulse; - DEBUG_OUT(6) <= self_trigger; - DEBUG_OUT(7) <= self_trigger_o; - DEBUG_OUT(8) <= self_trigger_busy; - DEBUG_OUT(9) <= TRIGGER_BUSY_IN; - DEBUG_OUT(15 downto 10) <= (others => '0'); - + DEBUG_OUT(1) <= NX_MAIN_CLK_IN; + DEBUG_OUT(2) <= self_trigger; + DEBUG_OUT(3) <= self_trigger_o; + DEBUG_OUT(4) <= self_trigger_busy; + DEBUG_OUT(5) <= TRIGGER_BUSY_IN; + DEBUG_OUT(6) <= DATA_CLK_IN; + DEBUG_OUT(7) <= new_data_frame_debug; + DEBUG_OUT(15 downto 8 ) <= (others => '0'); + ----------------------------------------------------------------------------- -- Reset Domain Transfer ----------------------------------------------------------------------------- @@ -111,114 +80,10 @@ begin SIGNAL_A_IN => RESET_IN, SIGNAL_OUT => RESET_NX_MAIN_CLK_IN ); - - ----------------------------------------------------------------------------- - -- Timer - timer_1: timer - generic map ( - CTR_WIDTH => 12 - ) - port map ( - CLK_IN => NX_MAIN_CLK_IN, - RESET_IN => RESET_NX_MAIN_CLK_IN, - TIMER_START_IN => wait_timer_start, - TIMER_END_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - wait_timer_init <= reg_testpulse_length - 1; - ----------------------------------------------------------------------------- -- Generate Trigger ----------------------------------------------------------------------------- - - PROC_TESTPULSE_OUT: process(NX_MAIN_CLK_IN) - begin - if( rising_edge(NX_MAIN_CLK_IN) ) then - if (RESET_NX_MAIN_CLK_IN = '1') then - trigger_o <= '0'; - testpulse_o <= '0'; - testpulse_p <= '0'; - ts_reset_o <= '0'; - wait_timer_start <= '0'; - trigger_cycle_ctr <= (others => '0'); - extern_trigger <= '0'; - STATE <= S_IDLE; - else - trigger_o <= '0'; - testpulse_o <= '0'; - testpulse_p <= '0'; - ts_reset_o <= '0'; - wait_timer_start <= '0'; - - case STATE is - when S_IDLE => - if (TRIGGER_IN = '1') then - extern_trigger <= '1'; - testpulse_o <= '1'; - testpulse_p <= '1'; - if (reg_testpulse_length > 0) then - wait_timer_start <= '1'; - STATE <= S_WAIT_TESTPULSE_END; - else - STATE <= S_IDLE; - end if; - else - extern_trigger <= '0'; - STATE <= S_IDLE; - end if; - - when S_WAIT_TESTPULSE_END => - if (WAIT_TIMER_DONE = '0') then - testpulse_o <= '1'; - STATE <= S_WAIT_TESTPULSE_END; - else - STATE <= S_IDLE; - end if; - - end case; - end if; - end if; - end process PROC_TESTPULSE_OUT; - - -- Transfer testpulse_p to CLK_IN Domain - pulse_dtrans_TESTPULSE: pulse_dtrans - generic map ( - CLK_RATIO => 6 - ) - port map ( - CLK_A_IN => NX_MAIN_CLK_IN, - RESET_A_IN => RESET_NX_MAIN_CLK_IN, - PULSE_A_IN => testpulse_p, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => testpulse - ); - - PROC_CAL_RATES: process (CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - testpulse_rate_t <= (others => '0'); - testpulse_rate <= (others => '0'); - rate_timer <= (others => '0'); - else - if (rate_timer < x"5f5e100") then - if (testpulse = '1') then - testpulse_rate_t <= testpulse_rate_t + 1; - end if; - rate_timer <= rate_timer + 1; - else - testpulse_rate <= testpulse_rate_t; - - testpulse_rate_t(27 downto 1) <= (others => '0'); - testpulse_rate_t(0) <= testpulse; - - rate_timer <= (others => '0'); - end if; - end if; - end if; - end process PROC_CAL_RATES; ----------------------------------------------------------------------------- -- Self Trigger @@ -233,13 +98,20 @@ begin self_trigger_busy <= '0'; self_trigger <= '0'; else - frame_bits := TIMESTAMP_IN(31) & - TIMESTAMP_IN(23) & - TIMESTAMP_IN(15) & - TIMESTAMP_IN(7); + frame_bits := DATA_IN(31) & + DATA_IN(23) & + DATA_IN(15) & + DATA_IN(7); self_trigger <= '0'; self_trigger_busy <= '0'; + if (DATA_CLK_IN = '1' and + frame_bits = "1000") then + new_data_frame_debug <= '1'; + else + new_data_frame_debug <= '0'; + end if; + case ST_STATE is when ST_IDLE => if (TRIGGER_BUSY_IN = '0' and @@ -286,30 +158,17 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - reg_trigger_period <= x"00ff"; - reg_trigger_num_cycles <= x"01"; - reg_testpulse_length <= x"064"; - reg_ts_reset_on <= '0'; - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - start_cycle <= '0'; - slv_ack_o <= '0'; + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; else - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - start_cycle <= '0'; - + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); if (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is - when x"0000" => - if (unsigned(SLV_DATA_IN(11 downto 0)) > 0) then - reg_testpulse_length <= - unsigned(SLV_DATA_IN(11 downto 0)); - end if; - slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; @@ -318,16 +177,6 @@ begin elsif (SLV_READ_IN = '1') then case SLV_ADDR_IN is - when x"0000" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(reg_testpulse_length); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0001" => - slv_data_out_o(27 downto 0) <= std_logic_vector(testpulse_rate); - slv_data_out_o(31 downto 28) <= (others => '0'); - slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; @@ -345,19 +194,14 @@ begin -- Output Signals ----------------------------------------------------------------------------- - -- Buffer for timing - testpulse_o_b <= testpulse_o when rising_edge(NX_MAIN_CLK_IN); - -- Trigger Output - TRIGGER_OUT <= trigger_o; - TS_RESET_OUT <= ts_reset_o; - TESTPULSE_OUT <= testpulse_o_b; - SELF_TRIGGER_OUT <= self_trigger_o; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; + TRIGGER_OUT <= '0'; + SELF_TRIGGER_OUT <= self_trigger_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; end Behavioral; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index a3a078d..e99744b 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -54,7 +54,7 @@ entity nx_trigger_handler is TRIGGER_BUSY_OUT : out std_logic; -- Pulser - TRIGGER_TESTPULSE_OUT : out std_logic; + NX_TESTPULSE_OUT : out std_logic; -- Slave bus SLV_READ_IN : in std_logic; @@ -72,6 +72,8 @@ entity nx_trigger_handler is end entity; architecture Behavioral of nx_trigger_handler is + attribute HGROUP : string; + attribute HGROUP of Behavioral : architecture is "NX_TRIGGER_HANDLER"; -- Timing Trigger Handler constant NUM_FF : integer := 10; @@ -112,7 +114,8 @@ architecture Behavioral of nx_trigger_handler is signal fee_trg_release_o : std_logic; signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); signal send_testpulse : std_logic; - + signal testpulse_enable : std_logic; + type STATES is (S_IDLE, S_CTS_TRIGGER, S_WAIT_TRG_DATA_VALID, @@ -136,19 +139,25 @@ architecture Behavioral of nx_trigger_handler is -- Testpulse Handler type T_STATES is (T_IDLE, - T_WAIT_TIMER, - T_SET_TESTPULSE + T_WAIT_TESTPULE_DELAY, + T_SET_TESTPULSE, + T_WAIT_TESTPULE_END ); signal T_STATE : T_STATES; - signal trigger_testpulse_o : std_logic; + signal testpulse_delay : unsigned(11 downto 0); + signal testpulse_length : unsigned(11 downto 0); + signal testpulse_o : std_logic; signal wait_timer_reset : std_logic; signal wait_timer_start : std_logic; signal wait_timer_done : std_logic; + signal wait_timer_end : unsigned(11 downto 0); -- Rate Calculation signal accepted_trigger_rate_t : unsigned(27 downto 0); + signal testpulse_o_clk100 : std_logic; + signal testpulse_rate_t : unsigned(27 downto 0); signal rate_timer : unsigned(27 downto 0); -- TRBNet Slave Bus @@ -158,13 +167,15 @@ architecture Behavioral of nx_trigger_handler is signal slv_ack_o : std_logic; signal reg_testpulse_delay : unsigned(11 downto 0); + signal reg_testpulse_length : unsigned(11 downto 0); signal reg_testpulse_enable : std_logic; signal accepted_trigger_rate : unsigned(27 downto 0); + signal testpulse_rate : unsigned(27 downto 0); signal invalid_t_trigger_ctr_clear : std_logic; -- Reset signal RESET_NX_MAIN_CLK_IN : std_logic; - + begin -- Debug Line @@ -183,7 +194,7 @@ begin DEBUG_OUT(12) <= trigger_busy_o; DEBUG_OUT(13) <= timestamp_trigger_o; DEBUG_OUT(14) <= send_testpulse; - DEBUG_OUT(15) <= trigger_testpulse_o; + DEBUG_OUT(15) <= testpulse_o; ----------------------------------------------------------------------------- -- Reset Domain Transfer @@ -250,6 +261,8 @@ begin PROC_TIMING_TRIGGER_HANDLER: process(NX_MAIN_CLK_IN) begin if( rising_edge(NX_MAIN_CLK_IN) ) then + testpulse_enable <= reg_testpulse_enable; + if (RESET_NX_MAIN_CLK_IN = '1') then invalid_timing_trigger_n <= '1'; ts_wait_timer_start <= '0'; @@ -515,23 +528,26 @@ begin CLK_IN => NX_MAIN_CLK_IN, RESET_IN => wait_timer_reset, TIMER_START_IN => wait_timer_start, - TIMER_END_IN => reg_testpulse_delay, + TIMER_END_IN => wait_timer_end, TIMER_DONE_OUT => wait_timer_done ); PROC_TESTPULSE_HANDLER: process (NX_MAIN_CLK_IN) begin if( rising_edge(NX_MAIN_CLK_IN) ) then + testpulse_delay <= reg_testpulse_delay; + testpulse_length <= reg_testpulse_length; + if (RESET_NX_MAIN_CLK_IN = '1') then wait_timer_start <= '0'; wait_timer_reset <= '1'; - trigger_testpulse_o <= '0'; + testpulse_o <= '0'; T_STATE <= T_IDLE; else - trigger_testpulse_o <= '0'; wait_timer_start <= '0'; wait_timer_reset <= '0'; - + testpulse_o <= '0'; + if (fast_clear = '1') then wait_timer_reset <= '1'; T_STATE <= T_IDLE; @@ -541,30 +557,55 @@ begin when T_IDLE => if (send_testpulse = '1') then if (reg_testpulse_delay > 0) then - wait_timer_start <= '1'; - T_STATE <= T_WAIT_TIMER; + wait_timer_end <= testpulse_delay; + wait_timer_start <= '1'; + T_STATE <= T_WAIT_TESTPULE_DELAY; else - T_STATE <= T_SET_TESTPULSE; + T_STATE <= T_SET_TESTPULSE; end if; else - T_STATE <= T_IDLE; + T_STATE <= T_IDLE; end if; - when T_WAIT_TIMER => + when T_WAIT_TESTPULE_DELAY => if (wait_timer_done = '0') then - T_STATE <= T_WAIT_TIMER; + T_STATE <= T_WAIT_TESTPULE_DELAY; else - T_STATE <= T_SET_TESTPULSE; + T_STATE <= T_SET_TESTPULSE; end if; when T_SET_TESTPULSE => - trigger_testpulse_o <= '1'; - T_STATE <= T_IDLE; + testpulse_o <= '1'; + wait_timer_end <= testpulse_length; + wait_timer_start <= '1'; + T_STATE <= T_WAIT_TESTPULE_END; + + when T_WAIT_TESTPULE_END => + if (wait_timer_done = '0') then + testpulse_o <= '1'; + T_STATE <= T_WAIT_TESTPULE_END; + else + T_STATE <= T_IDLE; + end if; + end case; end if; end if; end if; end process PROC_TESTPULSE_HANDLER; + + pulse_dtrans_TESTPULSE_RATE: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_MAIN_CLK_IN, + RESET_A_IN => RESET_NX_MAIN_CLK_IN, + PULSE_A_IN => testpulse_o, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => testpulse_o_clk100 + ); PROC_CAL_RATES: process (CLK_IN) begin @@ -572,19 +613,26 @@ begin if (RESET_IN = '1') then accepted_trigger_rate_t <= (others => '0'); accepted_trigger_rate <= (others => '0'); + testpulse_rate_t <= (others => '0'); + testpulse_rate <= (others => '0'); rate_timer <= (others => '0'); else if (rate_timer < x"5f5e100") then if (timing_trigger_o = '1') then accepted_trigger_rate_t <= accepted_trigger_rate_t + 1; end if; + + if (testpulse_o_clk100 = '1') then + testpulse_rate_t <= testpulse_rate_t + 1; + end if; rate_timer <= rate_timer + 1; else rate_timer <= (others => '0'); accepted_trigger_rate <= accepted_trigger_rate_t; - - accepted_trigger_rate_t(27 downto 0) <= (others => '0'); - accepted_trigger_rate_t(0) <= timing_trigger_o; + testpulse_rate <= testpulse_rate_t; + + accepted_trigger_rate_t <= (others => '0'); + testpulse_rate_t <= (others => '0'); end if; end if; end if; @@ -603,6 +651,7 @@ begin slv_unknown_addr_o <= '0'; slv_ack_o <= '0'; reg_testpulse_delay <= (others => '0'); + reg_testpulse_length <= x"064"; reg_testpulse_enable <= '0'; invalid_t_trigger_ctr_clear <= '1'; else @@ -610,7 +659,7 @@ begin slv_no_more_data_o <= '0'; slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; - invalid_t_trigger_ctr_clear <= '1'; + invalid_t_trigger_ctr_clear <= '0'; if (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is @@ -619,10 +668,15 @@ begin slv_ack_o <= '1'; when x"0001" => - reg_testpulse_delay <= + reg_testpulse_delay <= unsigned(SLV_DATA_IN(11 downto 0)); slv_ack_o <= '1'; + when x"0002" => + reg_testpulse_length <= + unsigned(SLV_DATA_IN(11 downto 0)); + slv_ack_o <= '1'; + when x"0003" => invalid_t_trigger_ctr_clear <= '1'; slv_ack_o <= '1'; @@ -647,15 +701,27 @@ begin slv_ack_o <= '1'; when x"0002" => + slv_data_out_o(11 downto 0) <= + std_logic_vector(reg_testpulse_length); + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0003" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(invalid_timing_trigger_ctr); + slv_data_out_o(31 downto 26) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0004" => slv_data_out_o(27 downto 0) <= std_logic_vector(accepted_trigger_rate); slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; - when x"0003" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(invalid_timing_trigger_ctr); - slv_data_out_o(31 downto 26) <= (others => '0'); + when x"0005" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(testpulse_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; when others => @@ -686,7 +752,7 @@ begin FEE_TRG_RELEASE_OUT <= fee_trg_release_o; FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o; - TRIGGER_TESTPULSE_OUT <= trigger_testpulse_o; + NX_TESTPULSE_OUT <= testpulse_o; -- Slave Bus SLV_DATA_OUT <= slv_data_out_o; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 8a1c541..93be57d 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -384,6 +384,17 @@ component fifo_data_stream_44to44_dc ); end component; +component dynamic_shift_register8x64 + port ( + Din : in std_logic_vector(7 downto 0); + Addr : in std_logic_vector(5 downto 0); + Clock : in std_logic; + ClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0) + ); +end component; + component ram_fifo_delay_256x44 port ( WrAddress : in std_logic_vector(7 downto 0); @@ -431,6 +442,9 @@ component fifo_32_data end component; component nx_data_receiver + generic ( + DEBUG_ENABLE : boolean + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -447,8 +461,7 @@ component nx_data_receiver ADC_NX_IN : in std_logic_vector(1 downto 0); ADC_D_IN : in std_logic_vector(1 downto 0); ADC_SCLK_LOCK_OUT : out std_logic; - NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_OUT : out std_logic_vector(43 downto 0); DATA_CLK_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -467,11 +480,9 @@ component nx_data_delay port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_FRAME_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); + DATA_IN : in std_logic_vector(43 downto 0); DATA_CLK_IN : in std_logic; - NX_FRAME_OUT : out std_logic_vector(31 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_OUT : out std_logic_vector(43 downto 0); DATA_CLK_OUT : out std_logic; FIFO_DELAY_IN : in std_logic_vector(7 downto 0); SLV_READ_IN : in std_logic; @@ -490,8 +501,7 @@ component nx_data_validate port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); + DATA_IN : in std_logic_vector(43 downto 0); DATA_CLK_IN : in std_logic; TIMESTAMP_OUT : out std_logic_vector(13 downto 0); CHANNEL_OUT : out std_logic_vector(6 downto 0); @@ -839,10 +849,10 @@ component nx_fpga_timestamp CLK_IN : in std_logic; RESET_IN : in std_logic; NX_MAIN_CLK_IN : in std_logic; - TIMESTAMP_RESET_IN : in std_logic; + TIMESTAMP_RESET_1_IN : in std_logic; + TIMESTAMP_RESET_2_IN : in std_logic; TIMESTAMP_RESET_OUT : out std_logic; TRIGGER_IN : in std_logic; - TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); TIMESTAMP_TRIGGER_OUT : out std_logic; SLV_READ_IN : in std_logic; @@ -891,7 +901,7 @@ component nx_trigger_handler TRIGGER_STATUS_OUT : out std_logic; FAST_CLEAR_OUT : out std_logic; TRIGGER_BUSY_OUT : out std_logic; - TRIGGER_TESTPULSE_OUT : out std_logic; + NX_TESTPULSE_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -910,12 +920,8 @@ component nx_trigger_generator RESET_IN : in std_logic; NX_MAIN_CLK_IN : in std_logic; TRIGGER_BUSY_IN : in std_logic; - TRIGGER_IN : in std_logic; TRIGGER_OUT : out std_logic; - TS_RESET_OUT : out std_logic; - TESTPULSE_OUT : out std_logic; - TIMESTAMP_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); + DATA_IN : in std_logic_vector(43 downto 0); DATA_CLK_IN : in std_logic; SELF_TRIGGER_OUT : out std_logic; SLV_READ_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 0b130ac..6500021 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -1,4 +1,4 @@ ---------------------------------------------------------------------------- +-------------------------------------------------------------------------- -- -- One nXyter FEB -- @@ -115,10 +115,8 @@ architecture Behavioral of nXyter_FEE_board is signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); -- TRB Register - signal nx_timestamp_reset_1 : std_logic; - signal nx_timestamp_reset_2 : std_logic; - signal nx_timestamp_reset_3 : std_logic; - signal nx_timestamp_reset : std_logic; + signal nx_timestamp_reset_status : std_logic; + signal nx_timestamp_reset_receiver : std_logic; signal nx_timestamp_reset_o : std_logic; signal i2c_reg_reset_o : std_logic; signal nxyter_online : std_logic; @@ -139,15 +137,13 @@ architecture Behavioral of nXyter_FEE_board is signal spi_sdo : std_logic; -- Data Receiver - signal timestamp_recv : std_logic_vector(31 downto 0); - signal adc_data_recv : std_logic_vector(11 downto 0); + signal data_recv : std_logic_vector(43 downto 0); signal data_clk_recv : std_logic; signal self_trigger : std_logic; signal pll_sadc_clk_lock : std_logic; -- Data Delay - signal timestamp_delayed : std_logic_vector(31 downto 0); - signal adc_data_delayed : std_logic_vector(11 downto 0); + signal data_delayed : std_logic_vector(43 downto 0); signal data_clk_delayed : std_logic; signal data_fifo_delay : std_logic_vector(7 downto 0); @@ -204,16 +200,12 @@ architecture Behavioral of nXyter_FEE_board is signal trigger_busy : std_logic; signal fast_clear : std_logic; signal fee_trg_release_o : std_logic; - signal trigger_testpulse : std_logic; -- FPGA Timestamp - signal timestamp_current : unsigned(11 downto 0); signal timestamp_hold : unsigned(11 downto 0); - signal nx_timestamp_trigger_o : std_logic; -- Trigger Generator signal trigger_intern : std_logic; - signal nx_testpulse_o : std_logic; -- Error signal error_all : std_logic_vector(7 downto 0); @@ -327,10 +319,10 @@ begin PLL_ADC_DCLK_LOCK_IN => PLL_ADC_DCLK_LOCK_IN, PLL_ADC_SCLK_LOCK_IN => pll_sadc_clk_lock, PLL_RESET_OUT => PLL_RESET_OUT, - + I2C_SM_RESET_OUT => I2C_SM_RESET_OUT, I2C_REG_RESET_OUT => i2c_reg_reset_o, - NX_TS_RESET_OUT => nx_timestamp_reset_1, + NX_TS_RESET_OUT => nx_timestamp_reset_status, NX_ONLINE_OUT => nxyter_online, ERROR_ALL_IN => error_all, @@ -446,12 +438,12 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, - TIMESTAMP_RESET_IN => nx_timestamp_reset, + TIMESTAMP_RESET_1_IN => nx_timestamp_reset_status, + TIMESTAMP_RESET_2_IN => nx_timestamp_reset_receiver, TIMESTAMP_RESET_OUT => nx_timestamp_reset_o, TRIGGER_IN => timestamp_trigger, - TIMESTAMP_CURRENT_OUT => timestamp_current, TIMESTAMP_HOLD_OUT => timestamp_hold, - TIMESTAMP_TRIGGER_OUT => nx_timestamp_trigger_o, + TIMESTAMP_TRIGGER_OUT => NX_TIMESTAMP_TRIGGER_OUT, SLV_READ_IN => open, SLV_WRITE_IN => open, SLV_DATA_OUT => open, @@ -509,7 +501,7 @@ begin FAST_CLEAR_OUT => fast_clear, TRIGGER_BUSY_OUT => trigger_busy, - TRIGGER_TESTPULSE_OUT => trigger_testpulse, + NX_TESTPULSE_OUT => NX_TESTPULSE_OUT, SLV_READ_IN => slv_read(7), SLV_WRITE_IN => slv_write(7), @@ -534,13 +526,9 @@ begin NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, TRIGGER_BUSY_IN => trigger_busy, - TRIGGER_IN => trigger_testpulse, TRIGGER_OUT => trigger_intern, - TS_RESET_OUT => nx_timestamp_reset_2, - TESTPULSE_OUT => nx_testpulse_o, - TIMESTAMP_IN => timestamp_recv, - ADC_DATA_IN => adc_data_recv, + DATA_IN => data_recv, DATA_CLK_IN => data_clk_recv, SELF_TRIGGER_OUT => self_trigger, @@ -561,6 +549,9 @@ begin ------------------------------------------------------------------------------- nx_data_receiver_1: nx_data_receiver + generic map ( + DEBUG_ENABLE => true + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, @@ -568,7 +559,7 @@ begin NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset_3, + NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset_receiver, ADC_CLK_DAT_IN => CLK_ADC_IN, ADC_FCLK_IN => ADC_FCLK_IN, @@ -580,8 +571,7 @@ begin ADC_D_IN => ADC_D_IN, ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock, - NX_TIMESTAMP_OUT => timestamp_recv, - ADC_DATA_OUT => adc_data_recv, + DATA_OUT => data_recv, DATA_CLK_OUT => data_clk_recv, SLV_READ_IN => slv_read(2), @@ -604,12 +594,10 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, - NX_FRAME_IN => timestamp_recv, - ADC_DATA_IN => adc_data_recv, + DATA_IN => data_recv, DATA_CLK_IN => data_clk_recv, - NX_FRAME_OUT => timestamp_delayed, - ADC_DATA_OUT => adc_data_delayed, + DATA_OUT => data_delayed, DATA_CLK_OUT => data_clk_delayed, FIFO_DELAY_IN => data_fifo_delay, @@ -635,8 +623,7 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, - NX_TIMESTAMP_IN => timestamp_delayed, - ADC_DATA_IN => adc_data_delayed, + DATA_IN => data_delayed, DATA_CLK_IN => data_clk_delayed, TIMESTAMP_OUT => timestamp, @@ -802,11 +789,7 @@ begin ------------------------------------------------------------------------------- -- nXyter Signals ------------------------------------------------------------------------------- - nx_timestamp_reset <= nx_timestamp_reset_1 or - nx_timestamp_reset_2 or - nx_timestamp_reset_3; - NX_RESET_OUT <= not nx_timestamp_reset_o; - NX_TESTPULSE_OUT <= nx_testpulse_o; + NX_RESET_OUT <= not nx_timestamp_reset_o; ------------------------------------------------------------------------------- -- I2C Signals @@ -817,7 +800,6 @@ begin ------------------------------------------------------------------------------- -- Others ------------------------------------------------------------------------------- - NX_TIMESTAMP_TRIGGER_OUT <= nx_timestamp_trigger_o; TRIGGER_OUT <= self_trigger; ------------------------------------------------------------------------------- @@ -842,6 +824,8 @@ begin SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(11) ); + --DEBUG_LINE_OUT <= (others => '0'); + ------------------------------------------------------------------------------- -- END ------------------------------------------------------------------------------- diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index e0ab33e..738238c 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -36,14 +36,13 @@ 0x8270 : r Token register, 14 in a row -- Trigger Generator -0x8140 : r/w Length of Trigger TestPulse (12 Bit, in 4ns) -0x8141 : r Testpulse Rate (in Hz) -- Trigger Handler 0x8160 : r/w Enable Testpulse Signal (default: off) 0x8161 : r/w Delay Testpulse Signal after Trigger (12 Bit, in 10ns) -0x8162 : r Accepted Trigger Rate (28 Bit, in Hz) -0x8163 : r/w r: Invalid Timing Trigger Counter +0x8162 : r/w Length of Trigger TestPulse (12 Bit, in 4ns) +0x8163 : r Accepted Trigger Rate (28 Bit, in Hz) +0x8164 : r/w r: Invalid Timing Trigger Counter w: Clear Counter -- NX Data Receiver @@ -203,7 +202,7 @@ 10: nx_trigger_validate 11: nx_event_buffer 12: nx_histograms - 13: nx_calib_event + 13: nx_status_event 14: Checkerboard --- Trigger Selction Window Setup diff --git a/nxyter/trb3_periph.p2t b/nxyter/trb3_periph.p2t index dcd85bb..2968146 100644 --- a/nxyter/trb3_periph.p2t +++ b/nxyter/trb3_periph.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 26 +-t 69 -c 1 -e 2 -m nodelist.txt diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 9e9cde8..42306ef 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -152,6 +152,7 @@ add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd" add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd" add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" +add_file -vhdl -lib "work" "cores/dynamic_shift_register8x64.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 59fbdb3..0ceebf7 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -39,7 +39,7 @@ BLOCK RD_DURING_WR_PATHS ; USE PRIMARY NET "clk_100_i_c"; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; - USE PRIMARY2EDGE NET "nx_clk_adc_dat"; +# USE PRIMARY2EDGE NET "nx_clk_adc_dat"; ################################################################# # Reset Nets @@ -61,16 +61,20 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLI BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*"; MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 10 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 20 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_status_*/nx_ts_reset_o" 10 ns; + +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_status_*/nx_ts_reset_o" 100 ns; + MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_o" 20 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/reg_testpulse_length_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns; +MULTICYCLE TO CELL "*/timestamp_sync_o*" 10 ns; + +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_o" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; @@ -79,27 +83,31 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_* MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/signal_async_trans_RESET_IN/*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/sampling_clk_reset*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_bit_shift*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_r*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_clk_ok" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_notlock_ctr_r* 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reg_nx_frame_synced*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns; #SPI Interface REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE; LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; -#LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; ################################################################# # Constraints for nxyter inputs @@ -108,6 +116,10 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; # look at .par and .twr.setup file for clocks # and .mrp or errors +#PROHIBIT PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; +#PROHIBIT SECONDARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; + + PROHIBIT PRIMARY NET "NX1_DATA_CLK_*"; PROHIBIT SECONDARY NET "NX1_DATA_CLK_*"; @@ -119,3 +131,11 @@ INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_DATA_CLK_IN"; #DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*"; #INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_DATA_CLK_IN"; + +UGROUP NXYTER1 BBOX 76 58 + BLKNAME nXyter_FEE_board_0; + +LOCATE UGROUP NXYTER1 SITE "R28C2D"; + +#LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ; +LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R61C5" ; diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nx1.vhd index ff10ddd..91a776d 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nx1.vhd @@ -272,8 +272,8 @@ architecture trb3_periph_arch of trb3_periph is signal nx1_regio_write_ack_out : std_logic; signal nx1_regio_no_more_data_out : std_logic; signal nx1_regio_unknown_addr_out : std_logic; - - signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0); + + -- Internal Trigger signal fee1_trigger : std_logic; begin -- 2.43.0