From 057c3aa18e8b61776af1ad5a937b2483eb2f0317 Mon Sep 17 00:00:00 2001 From: Rene Hagdorn Date: Thu, 26 Apr 2018 15:37:03 +0200 Subject: [PATCH] Pseudo data generator and Multiplexer added --- mupix/Mupix8/sources/DatasourceSelector.vhd | 91 +++++++ mupix/Mupix8/sources/FrameGenMux2.vhd | 269 ++++++++++++++++++++ mupix/Mupix8/sources/Generator3.vhd | 129 ++++++++++ mupix/Mupix8/sources/MupixBoard.vhd | 252 +++++++++++------- 4 files changed, 649 insertions(+), 92 deletions(-) create mode 100644 mupix/Mupix8/sources/DatasourceSelector.vhd create mode 100644 mupix/Mupix8/sources/FrameGenMux2.vhd create mode 100644 mupix/Mupix8/sources/Generator3.vhd diff --git a/mupix/Mupix8/sources/DatasourceSelector.vhd b/mupix/Mupix8/sources/DatasourceSelector.vhd new file mode 100644 index 0000000..f3be680 --- /dev/null +++ b/mupix/Mupix8/sources/DatasourceSelector.vhd @@ -0,0 +1,91 @@ +---------------------------------------------------------------------------------- +-- Datasource selector to switch beween MuPix data and pseudo data from FrameGen +-- +-- René Hagdorn, Ruhr-Universität Bochum +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity DataSel is + generic( + constant WIDTH : natural := 32; + constant DEPTH : natural := 256 + ); + port( + -- FrameGen Data + fg0in : in std_logic_vector(WIDTH - 1 downto 0); + fg1in : in std_logic_vector(WIDTH - 1 downto 0); + fg2in : in std_logic_vector(WIDTH - 1 downto 0); + fg3in : in std_logic_vector(WIDTH - 1 downto 0); + fg_full : in std_logic_vector(3 downto 0); + fg_empty : in std_logic_vector(3 downto 0); + + -- SerDes Data + serdes0 : in std_logic_vector(WIDTH - 1 downto 0); + serdes1 : in std_logic_vector(WIDTH - 1 downto 0); + serdes2 : in std_logic_vector(WIDTH - 1 downto 0); + serdes3 : in std_logic_vector(WIDTH - 1 downto 0); + sd_full : in std_logic_vector(3 downto 0); + sd_empty : in std_logic_vector(3 downto 0); + + sel : in std_logic; -- Selects FrameGen + clk : in std_logic; + rst : in std_logic; + + out_data0 : out std_logic_vector(WIDTH - 1 downto 0); + out_data1 : out std_logic_vector(WIDTH - 1 downto 0); + out_data2 : out std_logic_vector(WIDTH - 1 downto 0); + out_data3 : out std_logic_vector(WIDTH - 1 downto 0); + fifo_full : out std_logic_vector(3 downto 0); + fifo_empty: out std_logic_vector(3 downto 0) + ); +end DataSel; + +architecture Behavioral of DataSel is + +begin + + Dsel: process (clk, sel) + begin + if rising_edge(clk) then + if rst = '1' then + out_data0 <= (others => '0'); + out_data1 <= (others => '0'); + out_data2 <= (others => '0'); + out_data3 <= (others => '0'); + else + case sel is + + when '1' => -- FrameGen Data + out_data0 <= fg0in; + out_data1 <= fg1in; + out_data2 <= fg2in; + out_data3 <= fg3in; + fifo_full <= fg_full; + fifo_empty <= fg_empty; + + when '0' => -- SerDes Data + out_data0 <= serdes0; + out_data1 <= serdes1; + out_data2 <= serdes2; + out_data3 <= serdes3; + fifo_full <= sd_full; + fifo_empty <= sd_empty; + + when others => + out_data0 <= (others => '0'); + out_data1 <= (others => '0'); + out_data2 <= (others => '0'); + out_data3 <= (others => '0'); + fifo_full <= (others => '0'); + fifo_empty <= (others => '0'); + + end case; + end if; + end if; + end process Dsel; + +end Behavioral; diff --git a/mupix/Mupix8/sources/FrameGenMux2.vhd b/mupix/Mupix8/sources/FrameGenMux2.vhd new file mode 100644 index 0000000..7d6ff39 --- /dev/null +++ b/mupix/Mupix8/sources/FrameGenMux2.vhd @@ -0,0 +1,269 @@ +---------------------------------------------------------------------------------- +-- Pseudo Data Generator and Data Source Selector +-- René Hagdorn, Ruhr-Universität Bochum +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity FrameGeneratorMux is + generic( + fpga_clk_speed : integer := 1e8; + spi_clk_speed : integer := 1e4; + FIFODEPTH : positive := 256; + DATAWIDTH : natural := 32 + ); + port( + clk : in std_logic; + reset : in std_logic; + serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0); + serdes_fifo_full : in std_logic_vector(3 downto 0); + serdes_fifo_empty : in std_logic_vector(3 downto 0); + serdes_fifo_rden : out std_logic_vector(3 downto 0); + out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0); + out_fifo_full : out std_logic_vector(3 downto 0); + out_fifo_empty : out std_logic_vector(3 downto 0); + --TRB slow control + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); +end FrameGeneratorMux; + +architecture Behavioral of FrameGeneratorMux is + +component Generator3 + generic( + constant iWIDTH : natural + ); + port( + clk : in std_logic; + reset : in std_logic; + start_gen : in std_logic; + data_num : in std_logic_vector(31 downto 0); + data_pause : in std_logic_vector(31 downto 0); + data_down : in std_logic_vector(31 downto 0); + chan_sel : in std_logic_vector(1 downto 0); + data_out : out std_logic_vector(iWIDTH - 1 downto 0); + writeEn : out std_logic + ); +end component Generator3; + +component STD_FIFO + generic ( + constant DATA_WIDTH : positive; + constant FIFO_DEPTH : positive + ); + port ( + CLK : in std_logic; + RST : in std_logic; + WriteEn : in std_logic; + DataIn : in std_logic_vector (DATA_WIDTH - 1 downto 0); + ReadEn : in std_logic; + DataOut : out std_logic_vector (DATA_WIDTH - 1 downto 0); + Empty : out std_logic; + Full : out std_logic + ); +end component STD_FIFO; + +component DataSel is + generic( + constant WIDTH : natural + ); + port( + -- FrameGen Data + fg0in : in std_logic_vector(WIDTH - 1 downto 0); + fg1in : in std_logic_vector(WIDTH - 1 downto 0); + fg2in : in std_logic_vector(WIDTH - 1 downto 0); + fg3in : in std_logic_vector(WIDTH - 1 downto 0); + fg_full : in std_logic_vector(3 downto 0); + fg_empty : in std_logic_vector(3 downto 0); + + -- SerDes Data + serdes0 : in std_logic_vector(WIDTH - 1 downto 0); + serdes1 : in std_logic_vector(WIDTH - 1 downto 0); + serdes2 : in std_logic_vector(WIDTH - 1 downto 0); + serdes3 : in std_logic_vector(WIDTH - 1 downto 0); + sd_full : in std_logic_vector(3 downto 0); + sd_empty : in std_logic_vector(3 downto 0); + + sel : in std_logic; -- Selects FrameGen + clk : in std_logic; + rst : in std_logic; + + out_data0 : out std_logic_vector(WIDTH - 1 downto 0); + out_data1 : out std_logic_vector(WIDTH - 1 downto 0); + out_data2 : out std_logic_vector(WIDTH - 1 downto 0); + out_data3 : out std_logic_vector(WIDTH - 1 downto 0); + fifo_full : out std_logic_vector(3 downto 0); + fifo_empty: out std_logic_vector(3 downto 0) + ); +end component DataSel; + +-- signal types +type chan_type is array (0 to 3) of std_logic_vector(1 downto 0); +type data_type is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0); + +-- Internal signals: Data Generator +signal gen_start : std_logic := '0'; +signal gen_num : std_logic_vector(31 downto 0) := (others => '0'); +signal gen_pause : std_logic_vector(31 downto 0) := (others => '0'); +signal gen_down : std_logic_vector(31 downto 0) := (others => '0'); +signal gen_wren : std_logic := '0'; +signal gen_chansel : chan_type := ("00", "01", "10", "11"); +signal gen_data : data_type; + +-- Internal signals: Fifo +signal fifo_data : data_type; +signal fifo_rden : std_logic_vector(3 downto 0); +signal fifo_ff : std_logic_vector(3 downto 0); +signal fifo_ef : std_logic_vector(3 downto 0); + +-- Internal signals: Datasource Selector +signal mux_sel : std_logic := '0'; + +signal sd_fifo_rden : std_logic_vector(3 downto 0); + +begin -- Behavioral + + Frame_Generator: for J in 0 to 3 generate + Data_Gen_J: Generator3 + generic map( + iWIDTH => DATAWIDTH + ) + port map( + clk => clk, + reset => reset, + start_gen => gen_start, + data_num => gen_num, + data_pause => gen_pause, + data_down => gen_down, + chan_sel => gen_chansel(J), + writeEn => gen_wren, + data_out => gen_data(J) + ); + + FIFO_J: STD_FIFO + generic map( + DATA_WIDTH => DATAWIDTH, + FIFO_DEPTH => FIFODEPTH + ) + port map( + CLK => clk, + RST => reset, + WriteEn => gen_wren, + ReadEn => fifo_rden(J), + DataIn => gen_data(J), + DataOut => fifo_data(J), + Full => fifo_ff(J), + Empty => fifo_ef(J) + ); + end generate Frame_Generator; + + Mux: DataSel + generic map( + WIDTH => DATAWIDTH + ) + port map( + clk => clk, + rst => reset, + sel => mux_sel, + fg0in => fifo_data(0), + fg1in => fifo_data(1), + fg2in => fifo_data(2), + fg3in => fifo_data(3), + fg_full => fifo_ff, + fg_empty => fifo_ef, + serdes0 => serdes_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH), + serdes1 => serdes_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH), + serdes2 => serdes_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH), + serdes3 => serdes_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH), + sd_full => serdes_fifo_full, + sd_empty => serdes_fifo_empty, + out_data0 => out_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH), + out_data1 => out_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH), + out_data2 => out_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH), + out_data3 => out_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH), + fifo_full => out_fifo_full, + fifo_empty => out_fifo_empty + ); + + serdes_fifo_rden <= sd_fifo_rden; + +---------------------------------------------------------------------------------- +-- TRB Slave Bus +-- 0x0140: start pseudo data generator (writes data to fifo) +-- 0x0141: number of datawords per block +-- 0x0142: pause between words +-- 0x0143: downtime between blocks +-- 0x0144: start DataGen fifo readout +-- 0x0145: start SerDes fifo readout +-- 0x0146: select data source (0 for MuPix data, 1 for pseudo data) +---------------------------------------------------------------------------------- + +SLV_BUS_HANDLER: process (clk) + begin + if rising_edge(clk) then + SLV_DATA_OUT <= (others => '0'); + SLV_ACK_OUT <= '0'; + SLV_UNKNOWN_ADDR_OUT <= '0'; + SLV_NO_MORE_DATA_OUT <= '0'; + gen_start <= '0'; + + if SLV_READ_IN = '1' then + case SLV_ADDR_IN is + when x"0141" => + SLV_DATA_OUT <= gen_num; + SLV_ACK_OUT <= '1'; + when x"0142" => + SLV_DATA_OUT <= gen_pause; + SLV_ACK_OUT <= '1'; + when x"0143" => + SLV_DATA_OUT <= gen_down; + SLV_ACK_OUT <= '1'; + when x"0146" => + SLV_DATA_OUT(0) <= mux_sel; + SLV_ACK_OUT <= '1'; + when others => + SLV_UNKNOWN_ADDR_OUT <= '1'; + end case; + + elsif SLV_WRITE_IN = '1' then + case SLV_ADDR_IN is + when x"0140" => + gen_start <= SLV_DATA_IN(0); + SLV_ACK_OUT <= '1'; + when x"0141" => + gen_num <= SLV_DATA_IN; + SLV_ACK_OUT <= '1'; + when x"0142" => + gen_pause <= SLV_DATA_IN; + SLV_ACK_OUT <= '1'; + when x"0143" => + gen_down <= SLV_DATA_IN; + SLV_ACK_OUT <= '1'; + when x"0144" => + fifo_rden <= SLV_DATA_IN(3 downto 0); + SLV_ACK_OUT <= '1'; + when x"0145" => + sd_fifo_rden <= SLV_DATA_IN(3 downto 0); + SLV_ACK_OUT <= '1'; + when x"0146" => + mux_sel <= SLV_DATA_IN(0); + SLV_ACK_OUT <= '1'; + when others => + SLV_UNKNOWN_ADDR_OUT <= '1'; + end case; + end if; + end if; + end process SLV_BUS_HANDLER; + +end Behavioral; diff --git a/mupix/Mupix8/sources/Generator3.vhd b/mupix/Mupix8/sources/Generator3.vhd new file mode 100644 index 0000000..078ea5e --- /dev/null +++ b/mupix/Mupix8/sources/Generator3.vhd @@ -0,0 +1,129 @@ +---------------------------------------------------------------------------------- +-- Pseudo data generator with +-- * adjustable word count for data block +-- * adjustable pause between single datawords +-- * adjustable downtime between data blocks +-- * channel number encoding +-- +-- René Hagdorn, Ruhr-Universität Bochum +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity Generator3 is + generic( + constant iWIDTH : natural := 32 + ); + + port( + clk : in std_logic; + reset : in std_logic; + start_gen : in std_logic; + data_num : in std_logic_vector(31 downto 0); + data_pause : in std_logic_vector(31 downto 0); + data_down : in std_logic_vector(31 downto 0); + chan_sel : in std_logic_vector(1 downto 0); + data_out : out std_logic_vector(iWIDTH - 1 downto 0); + writeEn : out std_logic + ); +end Generator3; + +architecture Behavior of Generator3 is + +type state is (idle, gen, pause, down); +type chan_type is array (0 to 3) of std_logic_vector(15 downto 0); + +signal data_fsm : state := idle; +signal writeEn_int : std_logic := '0'; +signal num_ctr : unsigned(31 downto 0) := (others => '0'); +signal pause_ctr : unsigned(31 downto 0) := (others => '0'); +signal down_ctr : unsigned(31 downto 0) := (others => '0'); +--signal data_int : unsigned(15 downto 0) := (others => '0'); +signal chan_sig : chan_type := ( + 0 => x"CA00", + 1 => x"CA01", + 2 => x"CA02", + 3 => x"CA03" +); + +begin + generator: process (clk) + begin + if rising_edge(clk) then + if reset = '1' then + data_fsm <= idle; + num_ctr <= (others => '0'); + pause_ctr <= (others => '0'); + down_ctr <= (others => '0'); +-- data_int <= (others => '0'); + writeEn_int <= '0'; + else + case data_fsm is + + when idle => + num_ctr <= (others => '0'); + pause_ctr <= (others => '0'); + down_ctr <= (others => '0'); + writeEn_int <= '0'; + if start_gen = '1' and unsigned(data_num) > 0 then + data_fsm <= gen; + else + data_fsm <= idle; + end if; + + when gen => + if unsigned(data_num) > 0 then + pause_ctr <= (others => '0'); + down_ctr <= (others => '0'); +-- data_int <= data_int + 1; + writeEn_int <= '1'; + num_ctr <= num_ctr + 1; + if num_ctr < unsigned(data_num) - 1 then + data_fsm <= pause; + else + data_fsm <= down; + end if; + else + data_fsm <= idle; + end if; + + when pause => + writeEn_int <= '0'; + if unsigned(data_pause) > 0 then + if pause_ctr < unsigned(data_pause) - 1 then + data_fsm <= pause; + pause_ctr <= pause_ctr + 1; + else + data_fsm <= gen; + end if; + else + data_fsm <= idle; + end if; + + when down => + writeEn_int <= '0'; + num_ctr <= (others => '0'); + if unsigned(data_down) > 0 then + if down_ctr < unsigned(data_down) - 1 then + data_fsm <= down; + down_ctr <= down_ctr + 1; + else + data_fsm <= gen; + end if; + else + data_fsm <= idle; + end if; + + end case; + end if; + writeEn <= writeEn_int; + data_out(iWIDTH - 1 downto iWIDTH - 16) <= std_logic_vector(num_ctr(15 downto 0)); + data_out(iWIDTH - 17 downto 16) <= (others => '0'); + data_out(15 downto 0) <= chan_sig(to_integer(unsigned(chan_sel))); + end if; + end process generator; + +end Behavior; diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index ee3d9ae..182f71f 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -1,6 +1,7 @@ ------------------------------------------------------------------------------- --MuPix Block for readout/controll of MuPix3 Sensorboard --T. Weber, University Mainz +--R. Hagdorn, Ruhr-University Bochum ------------------------------------------------------------------------------- library IEEE; @@ -42,6 +43,11 @@ entity MupixBoard8 is fifo_empty : in std_logic_vector(3 downto 0); -- mupix data FIFO empty flags fifo_full : in std_logic_vector(3 downto 0); -- mupix data FIFO full flags fifo_data : in std_logic_vector(127 downto 0); -- mupix readout data from FIFOs + + --hit generator / source selector outputs + mux_data_out : out std_logic_vector(127 downto 0); + mux_fifo_full : out std_logic_vector(3 downto 0); + mux_fifo_empty : out std_logic_vector(3 downto 0); --resets timestampreset_in : in std_logic; --time stamp reset @@ -255,10 +261,42 @@ architecture Behavioral of MupixBoard8 is SLV_UNKNOWN_ADDR_OUT : out std_logic ); end component TriggerHandler; + + component FrameGeneratorMux + generic( + fpga_clk_speed : integer; + spi_clk_speed : integer; + FIFODEPTH : positive; + DATAWIDTH : natural + ); + port( + clk : in std_logic; + reset : in std_logic; + serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0); + serdes_fifo_full : in std_logic_vector(3 downto 0); + serdes_fifo_empty : in std_logic_vector(3 downto 0); + serdes_fifo_rden : out std_logic_vector(3 downto 0); + out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0); + out_fifo_full : out std_logic_vector(3 downto 0); + out_fifo_empty : out std_logic_vector(3 downto 0); + --TRB slow control + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component FrameGeneratorMux; + + constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos + constant DATA_WIDTH : natural := 32; --width of datawords --signal declarations -- Bus Handler - constant NUM_PORTS : integer := 5; + constant NUM_PORTS : integer := 6; signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); @@ -290,6 +328,7 @@ begin -- Behavioral 2 => x"0090", -- Board Control 3 => x"0100", -- mupix readout 4 => x"0120", -- trigger handler + 5 => x"0140", -- hit generator others => x"0000"), PORT_ADDR_MASK => ( 0 => 4, -- HitBus Histograms @@ -297,6 +336,7 @@ begin -- Behavioral 2 => 4, -- Board Control 3 => 4, -- mupix readout 4 => 4, -- trigger handler + 5 => 4, -- hit generator others => 0) --PORT_MASK_ENABLE => 1 ) @@ -373,76 +413,76 @@ begin -- Behavioral SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) ); - pixelcontrol_1 : component PixelControl - generic map( - fpga_clk_speed => fpga_clk_speed, - spi_clk_speed => mupix_spi_clk_speed - ) - port map( - clk => clk, - reset => reset, - mupixslctrl => mupixslctrl_i, - ctrl_dout => ctrl_dout_sync, - SLV_READ_IN => slv_read(1), - SLV_WRITE_IN => slv_write(1), - SLV_DATA_OUT => slv_data_rd(1*32 + 31 downto 1*32), - SLV_DATA_IN => slv_data_wr(1*32 + 31 downto 1*32), - SLV_ADDR_IN => slv_addr(1*16 + 15 downto 1*16), - SLV_ACK_OUT => slv_ack(1), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1) - ); + pixelcontrol_1 : component PixelControl + generic map( + fpga_clk_speed => fpga_clk_speed, + spi_clk_speed => mupix_spi_clk_speed + ) + port map( + clk => clk, + reset => reset, + mupixslctrl => mupixslctrl_i, + ctrl_dout => ctrl_dout_sync, + SLV_READ_IN => slv_read(1), + SLV_WRITE_IN => slv_write(1), + SLV_DATA_OUT => slv_data_rd(1*32 + 31 downto 1*32), + SLV_DATA_IN => slv_data_wr(1*32 + 31 downto 1*32), + SLV_ADDR_IN => slv_addr(1*16 + 15 downto 1*16), + SLV_ACK_OUT => slv_ack(1), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1) + ); - ctrl_din <= mupixslctrl_i.sin; + ctrl_din <= mupixslctrl_i.sin; ctrl_clk1 <= mupixslctrl_i.clk1; ctrl_clk2 <= mupixslctrl_i.clk2; ctrl_ld <= mupixslctrl_i.load; ctrl_rb <= mupixslctrl_i.rb; - boardcontrol_1 : component MupixBoardDAC - port map( - clk => clk, - reset => reset, - spi_dout_dac => spi_dout_dac_sync, - dac4_dout => dac4_dout_sync, - spi_dout_adc => spi_dout_adc_sync, - spi_clk => spi_clk_i, - spi_din => spi_din_i, - spi_ld_tmp_dac => spi_ld_tmp_dac_i, - spi_ld_thres => spi_ld_thres_i, - spi_cs_adc => spi_cs_adc_i, - injection_pulse => testpulse_i, - SLV_READ_IN => slv_read(2), - SLV_WRITE_IN => slv_write(2), - SLV_DATA_OUT => slv_data_rd(2*32 + 31 downto 2*32), - SLV_DATA_IN => slv_data_wr(2*32 + 31 downto 2*32), - SLV_ADDR_IN => slv_addr(2*16 + 15 downto 2*16), - SLV_ACK_OUT => slv_ack(2), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) - ); + boardcontrol_1 : component MupixBoardDAC + port map( + clk => clk, + reset => reset, + spi_dout_dac => spi_dout_dac_sync, + dac4_dout => dac4_dout_sync, + spi_dout_adc => spi_dout_adc_sync, + spi_clk => spi_clk_i, + spi_din => spi_din_i, + spi_ld_tmp_dac => spi_ld_tmp_dac_i, + spi_ld_thres => spi_ld_thres_i, + spi_cs_adc => spi_cs_adc_i, + injection_pulse => testpulse_i, + SLV_READ_IN => slv_read(2), + SLV_WRITE_IN => slv_write(2), + SLV_DATA_OUT => slv_data_rd(2*32 + 31 downto 2*32), + SLV_DATA_IN => slv_data_wr(2*32 + 31 downto 2*32), + SLV_ADDR_IN => slv_addr(2*16 + 15 downto 2*16), + SLV_ACK_OUT => slv_ack(2), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) + ); - testpulse <= testpulse_i; + testpulse <= testpulse_i; - spi_output_pipe : process (clk) is - begin - if rising_edge(clk) then - if reset = '1' then - spi_clk <= '0'; - spi_din <= '0'; - spi_ld_tmp_dac <= '0'; - spi_ld_thres <= '0'; - spi_cs_adc <= '1'; - else - spi_clk <= spi_clk_i; - spi_din <= spi_din_i; - spi_ld_tmp_dac <= spi_ld_tmp_dac_i; - spi_ld_thres <= spi_ld_thres_i; - spi_cs_adc <= spi_cs_adc_i; - end if; - end if; - end process spi_output_pipe; + spi_output_pipe : process (clk) is + begin + if rising_edge(clk) then + if reset = '1' then + spi_clk <= '0'; + spi_din <= '0'; + spi_ld_tmp_dac <= '0'; + spi_ld_thres <= '0'; + spi_cs_adc <= '1'; + else + spi_clk <= spi_clk_i; + spi_din <= spi_din_i; + spi_ld_tmp_dac <= spi_ld_tmp_dac_i; + spi_ld_thres <= spi_ld_thres_i; + spi_cs_adc <= spi_cs_adc_i; + end if; + end if; + end process spi_output_pipe; mupixreadout1 : entity work.MupixTRBReadout generic map( @@ -471,35 +511,63 @@ begin -- Behavioral SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3) ); - triggerhandler1 : entity work.TriggerHandler - port map( - CLK_IN => clk, - RESET_IN => reset, - TIMING_TRIGGER_IN => TIMING_TRG_IN, - LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, - LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, - LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, - LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, - LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, - LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, - LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, - FEE_DATA_OUT => FEE_DATA_OUT, - FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, - FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, - FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, - FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, - FEE_DATA_0_IN => mupixdata_i, - FEE_DATA_WRITE_0_IN => mupixdata_valid_i, - TRIGGER_BUSY_BUFFER_READ_IN => mupixreadout_busy_i, - VALID_TRIGGER_OUT => trb_trigger_i, - SLV_READ_IN => slv_read(4), - SLV_WRITE_IN => slv_write(4), - SLV_DATA_OUT => slv_data_rd(4*32 + 31 downto 4*32), - SLV_DATA_IN => slv_data_wr(4*32 + 31 downto 4*32), - SLV_ADDR_IN => slv_addr(4*16 + 15 downto 4*16), - SLV_ACK_OUT => slv_ack(4), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4) - ); + triggerhandler1 : entity work.TriggerHandler + port map( + CLK_IN => clk, + RESET_IN => reset, + TIMING_TRIGGER_IN => TIMING_TRG_IN, + LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, + LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, + LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, + LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, + LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, + LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, + FEE_DATA_OUT => FEE_DATA_OUT, + FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, + FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, + FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, + FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, + FEE_DATA_0_IN => mupixdata_i, + FEE_DATA_WRITE_0_IN => mupixdata_valid_i, + TRIGGER_BUSY_BUFFER_READ_IN => mupixreadout_busy_i, + VALID_TRIGGER_OUT => trb_trigger_i, + SLV_READ_IN => slv_read(4), + SLV_WRITE_IN => slv_write(4), + SLV_DATA_OUT => slv_data_rd(4*32 + 31 downto 4*32), + SLV_DATA_IN => slv_data_wr(4*32 + 31 downto 4*32), + SLV_ADDR_IN => slv_addr(4*16 + 15 downto 4*16), + SLV_ACK_OUT => slv_ack(4), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4) + ); + + hitgenerator_1: component FrameGeneratorMux + generic map( + fpga_clk_speed => fpga_clk_speed + spi_clk_speed => spi_clk_speed + FIFODEPTH => FIFO_DEPTH, + DATAWIDTH => DATA_WIDTH + ) + port map( + clk => clk + reset => reset, + serdes_data => fifo_data, + serdes_fifo_full => fifo_full, + serdes_fifo_empty => fifo_empty, + serdes_fifo_rden => fifo_rden, + out_data => mux_data_out, + out_fifo_full => mux_fifo_full, + out_fifo_empty => mux_fifo_empty, + --TRB slow control + SLV_READ_IN => slv_read(5), + SLV_WRITE_IN => slv_write(5), + SLV_DATA_OUT => slv_data_rd(5*32 + 31 downto 5*32), + SLV_DATA_IN => slv_data_wr(5*32 + 31 downto 5*32), + SLV_ADDR_IN => slv_addr(5*16 + 15 downto 5*16), + SLV_ACK_OUT => slv_ack(5), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5) + ); end Behavioral; -- 2.43.0