From 073e48018a41de404a10a891e610e3295232d483 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 7 Dec 2021 11:22:44 +0100 Subject: [PATCH] M_LINK_FULL_DONE fixed --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 12 +- media_interfaces/sync/rx_control_RS.vhd | 538 +++++++++--------- media_interfaces/sync/tx_control_RS.vhd | 52 +- 3 files changed, 305 insertions(+), 297 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 427e944..5eb1298 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -186,10 +186,14 @@ begin -- TX ref clock -- output only if a slave port is available in QUAD ------------------------------------------------- - MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else - clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else - clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + clk_tx_full(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else -- just for testing + clk_tx_full(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else -- just for testing + clk_tx_full(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else -- just for testing + clk_tx_full(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else -- just for testing '0'; ------------------------------------------------- diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 4a574c3..31e17ab 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -1,280 +1,280 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; ---use work.trb_net_components.all; -use work.med_sync_define_RS.all; - -entity rx_control_RS is - generic( - SIM_MODE : integer := 0 - ); - port( - CLK_RXI : in std_logic; - CLK_SYS : in std_logic; - RESET : in std_logic; -- synchronous to RXI - -- Media Interface - RX_DATA_OUT : out std_logic_vector(15 downto 0); - RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0); - RX_WRITE_OUT : out std_logic; - -- SerDex data stream - RX_DATA_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; - -- synchronous link signals - WORD_SYNC_OUT : out std_logic; - RX_DLM_OUT : out std_logic; - RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); - RX_RST_OUT : out std_logic; - RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); - -- link status signals +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; +use work.med_sync_define_RS.all; + +entity rx_control_RS is + generic( + SIM_MODE : integer := 0 + ); + port( + CLK_RXI : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; -- synchronous to RXI + -- Media Interface + RX_DATA_OUT : out std_logic_vector(15 downto 0); + RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0); + RX_WRITE_OUT : out std_logic; + -- SerDex data stream + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + -- synchronous link signals + WORD_SYNC_OUT : out std_logic; + RX_DLM_OUT : out std_logic; + RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + RX_RST_OUT : out std_logic; + RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); + -- link status signals LINK_RX_READY_IN : in std_logic; LINK_TX_READY_IN : in std_logic; LINK_HALF_DONE_IN : in std_logic; - LINK_FULL_DONE_IN : in std_logic; - -- debug - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture rx_control_arch of rx_control_RS is - - type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST); - - signal rx_state : rx_state_t; - signal rx_state_bits : std_logic_vector(3 downto 0); - signal rx_packet_num : std_logic_vector(2 downto 0); - signal buf_rx_write_out : std_logic; - - signal rx_data : std_logic_vector(17 downto 0); - signal ct_fifo_write : std_logic; - signal ct_fifo_read : std_logic; - signal ct_fifo_reset : std_logic; - signal ct_fifo_data_out : std_logic_vector(17 downto 0); - signal ct_fifo_empty : std_logic; - signal ct_fifo_full : std_logic; - signal ct_fifo_afull : std_logic; - signal last_ct_fifo_empty : std_logic; - signal last_ct_fifo_read : std_logic; - - signal rx_dlm_i : std_logic; - signal rx_dlm_word_i : std_logic_vector(7 downto 0); - - signal rx_rst_i : std_logic; - signal rx_rst_word_i : std_logic_vector(7 downto 0); - - signal next_sop : std_logic; - - signal reg_rx_data_in : std_logic_vector(7 downto 0); - signal reg_rx_k_in : std_logic; - - signal sync_k_i : std_logic; -- denotes a K_IDLE detected - - signal link_rx_ready_qrx : std_logic; - signal link_full_done_qrx : std_logic; - signal link_full_done_qsys : std_logic; - -begin + LINK_FULL_DONE_IN : in std_logic; + -- debug + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture rx_control_arch of rx_control_RS is + + type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST); + + signal rx_state : rx_state_t; + signal rx_state_bits : std_logic_vector(3 downto 0); + signal rx_packet_num : std_logic_vector(2 downto 0); + signal buf_rx_write_out : std_logic; + + signal rx_data : std_logic_vector(17 downto 0); + signal ct_fifo_write : std_logic; + signal ct_fifo_read : std_logic; + signal ct_fifo_reset : std_logic; + signal ct_fifo_data_out : std_logic_vector(17 downto 0); + signal ct_fifo_empty : std_logic; + signal ct_fifo_full : std_logic; + signal ct_fifo_afull : std_logic; + signal last_ct_fifo_empty : std_logic; + signal last_ct_fifo_read : std_logic; + + signal rx_dlm_i : std_logic; + signal rx_dlm_word_i : std_logic_vector(7 downto 0); + + signal rx_rst_i : std_logic; + signal rx_rst_word_i : std_logic_vector(7 downto 0); + + signal next_sop : std_logic; + + signal reg_rx_data_in : std_logic_vector(7 downto 0); + signal reg_rx_k_in : std_logic; + + signal sync_k_i : std_logic; -- denotes a K_IDLE detected + + signal link_rx_ready_qrx : std_logic; + signal link_full_done_qrx : std_logic; + signal link_full_done_qsys : std_logic; + +begin -- Syncing things SYNC_RXI: signal_sync generic map( WIDTH => 2, DEPTH => 3 - ) - port map( - RESET => '0', - CLK0 => CLK_RXI, - CLK1 => CLK_RXI, + ) + port map( + RESET => '0', + CLK0 => CLK_RXI, + CLK1 => CLK_RXI, D_IN(0) => LINK_RX_READY_IN, - D_IN(1) => LINK_FULL_DONE_IN, + D_IN(1) => LINK_FULL_DONE_IN, D_OUT(0) => link_rx_ready_qrx, - D_OUT(1) => link_full_done_qrx - ); - - -- Syncing things - SYNC_SYS: signal_sync - generic map( - WIDTH => 1, - DEPTH => 3 - ) - port map( - RESET => '0', - CLK0 => CLK_SYS, - CLK1 => CLK_SYS, - D_IN(0) => LINK_FULL_DONE_IN, - D_OUT(0) => link_full_done_qsys - ); - ----------------------------------------------------------------------- --- Data to Endpoint ----------------------------------------------------------------------- - buf_rx_write_out <= (last_ct_fifo_read and not last_ct_fifo_empty) when rising_edge(CLK_SYS); - - RX_WRITE_OUT <= buf_rx_write_out; - RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; - RX_PACKET_NUMBER_OUT <= rx_packet_num; - - last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_SYS); - last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_SYS); - - process begin - wait until rising_edge(CLK_SYS); - if ( link_full_done_qsys = '0' ) then - rx_packet_num <= "100"; - elsif( buf_rx_write_out = '1' ) then - if rx_packet_num = "100" then - rx_packet_num <= "000"; - else - rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1); - end if; - end if; - end process; - ----------------------------------------------------------------------- --- Clock Domain Transfer ----------------------------------------------------------------------- - THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg - port map( - Data => rx_data, - WrClock => CLK_RXI, - RdClock => CLK_SYS, - WrEn => ct_fifo_write, - RdEn => ct_fifo_read, - Reset => ct_fifo_reset, - RPReset => ct_fifo_reset, - Q(17 downto 0) => ct_fifo_data_out, - Empty => ct_fifo_empty, - Full => ct_fifo_full, - AlmostFull => ct_fifo_afull - ); - - ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; - - ct_fifo_reset <= not link_full_done_qrx; - ----------------------------------------------------------------------- --- Read incoming data ----------------------------------------------------------------------- - PROC_RX_FSM : process begin - wait until rising_edge(CLK_RXI); - ct_fifo_write <= '0'; - rx_dlm_i <= '0'; - rx_rst_i <= '0'; - sync_k_i <= '0'; - - case rx_state is - when SLEEP => - rx_state_bits <= x"1"; - rx_data(7 downto 0) <= reg_rx_data_in; - if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then - rx_state <= WAIT_1; - sync_k_i <= '1'; - end if; - - when WAIT_1 => - rx_state <= FIRST; - - when FIRST => - rx_state_bits <= x"2"; - rx_data(7 downto 0) <= reg_rx_data_in; - sync_k_i <= '1'; - if( reg_rx_k_in = '1' ) then - case reg_rx_data_in is - when K_IDLE => - rx_state <= GET_IDLE; - when K_DLM => - rx_state <= GET_DLM; - when K_RST => - rx_state <= GET_RST; - when others => null; - end case; - else - rx_state <= GET_DATA; - end if; - - when GET_IDLE => - rx_state_bits <= x"3"; - rx_state <= FIRST; - next_sop <= '1'; - - when GET_DATA => - rx_state_bits <= x"4"; - -- rx_state <= FIRST - if reg_rx_k_in = '0' then - next_sop <= '0'; - rx_data(15 downto 8)<= reg_rx_data_in; - rx_data(16) <= next_sop; - rx_data(17) <= '0'; - ct_fifo_write <= '1'; - rx_state <= FIRST; - else -- not needed? - rx_state <= FIRST; -- not needed? - end if; - - when GET_DLM => - rx_state_bits <= x"5"; - rx_dlm_i <= '1'; - rx_dlm_word_i <= reg_rx_data_in; - rx_state <= FIRST; - - when GET_RST => - rx_state_bits <= x"6"; - rx_rst_i <= '1'; - rx_rst_word_i <= reg_rx_data_in; - rx_state <= FIRST; - - end case; - - if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then - rx_state <= SLEEP; - rx_dlm_word_i <= x"00"; - rx_rst_word_i <= x"00"; - end if; - end process; - --- we store incoming data in a register - reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_RXI); - reg_rx_k_in <= RX_K_IN when rising_edge(CLK_RXI); - ----------------------------------------------------------------------- --- Signals out ----------------------------------------------------------------------- - WORD_SYNC_OUT <= sync_k_i; - - RX_DLM_OUT <= rx_dlm_i when rising_edge(CLK_RXI); - RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_RXI); - RX_RST_OUT <= rx_rst_i when rising_edge(CLK_RXI); - RX_RST_WORD_OUT <= rx_rst_word_i when rising_edge(CLK_RXI); - ----------------------------------------------------------------------- --- Debug and Status ----------------------------------------------------------------------- - STAT_REG_OUT(3 downto 0) <= rx_state_bits; - STAT_REG_OUT(4) <= '0'; - STAT_REG_OUT(5) <= ct_fifo_afull; - STAT_REG_OUT(6) <= ct_fifo_empty; - STAT_REG_OUT(7) <= ct_fifo_write; - STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(CLK_SYS); - STAT_REG_OUT(16) <= rx_data(16); - STAT_REG_OUT(17) <= '0'; - STAT_REG_OUT(31 downto 18) <= (others => '0'); - - DEBUG_OUT(3 downto 0) <= rx_state_bits; - DEBUG_OUT(4) <= '0'; - DEBUG_OUT(5) <= ct_fifo_afull; - DEBUG_OUT(6) <= ct_fifo_empty; - DEBUG_OUT(7) <= ct_fifo_write; - DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); - DEBUG_OUT(16) <= reg_rx_k_in; - DEBUG_OUT(17) <= '0'; - DEBUG_OUT(18) <= '0'; - DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0'; - --DEBUG_OUT(16) <= rx_data(16); - DEBUG_OUT(31 downto 20) <= (others => '0'); - -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); - -- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0); - -end architecture; + D_OUT(1) => link_full_done_qrx + ); + + -- Syncing things + SYNC_SYS: signal_sync + generic map( + WIDTH => 1, + DEPTH => 3 + ) + port map( + RESET => '0', + CLK0 => CLK_SYS, + CLK1 => CLK_SYS, + D_IN(0) => LINK_FULL_DONE_IN, + D_OUT(0) => link_full_done_qsys + ); + +---------------------------------------------------------------------- +-- Data to Endpoint +---------------------------------------------------------------------- + buf_rx_write_out <= (last_ct_fifo_read and not last_ct_fifo_empty) when rising_edge(CLK_SYS); + + RX_WRITE_OUT <= buf_rx_write_out; + RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; + RX_PACKET_NUMBER_OUT <= rx_packet_num; + + last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_SYS); + last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_SYS); + + process begin + wait until rising_edge(CLK_SYS); + if ( link_full_done_qsys = '0' ) then + rx_packet_num <= "100"; + elsif( buf_rx_write_out = '1' ) then + if rx_packet_num = "100" then + rx_packet_num <= "000"; + else + rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1); + end if; + end if; + end process; + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- + THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg + port map( + Data => rx_data, + WrClock => CLK_RXI, + RdClock => CLK_SYS, + WrEn => ct_fifo_write, + RdEn => ct_fifo_read, + Reset => ct_fifo_reset, + RPReset => ct_fifo_reset, + Q(17 downto 0) => ct_fifo_data_out, + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + + ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; + + ct_fifo_reset <= not link_full_done_qrx; + +---------------------------------------------------------------------- +-- Read incoming data +---------------------------------------------------------------------- + PROC_RX_FSM : process begin + wait until rising_edge(CLK_RXI); + ct_fifo_write <= '0'; + rx_dlm_i <= '0'; + rx_rst_i <= '0'; + sync_k_i <= '0'; + + case rx_state is + when SLEEP => + rx_state_bits <= x"1"; + rx_data(7 downto 0) <= reg_rx_data_in; + if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then + rx_state <= WAIT_1; + sync_k_i <= '1'; + end if; + + when WAIT_1 => + rx_state <= FIRST; + + when FIRST => + rx_state_bits <= x"2"; + rx_data(7 downto 0) <= reg_rx_data_in; + sync_k_i <= '1'; + if( reg_rx_k_in = '1' ) then + case reg_rx_data_in is + when K_IDLE => + rx_state <= GET_IDLE; + when K_DLM => + rx_state <= GET_DLM; + when K_RST => + rx_state <= GET_RST; + when others => null; + end case; + else + rx_state <= GET_DATA; + end if; + + when GET_IDLE => + rx_state_bits <= x"3"; + rx_state <= FIRST; + next_sop <= '1'; + + when GET_DATA => + rx_state_bits <= x"4"; + -- rx_state <= FIRST + if reg_rx_k_in = '0' then + next_sop <= '0'; + rx_data(15 downto 8)<= reg_rx_data_in; + rx_data(16) <= next_sop; + rx_data(17) <= '0'; + ct_fifo_write <= '1'; + rx_state <= FIRST; + else -- not needed? + rx_state <= FIRST; -- not needed? + end if; + + when GET_DLM => + rx_state_bits <= x"5"; + rx_dlm_i <= '1'; + rx_dlm_word_i <= reg_rx_data_in; + rx_state <= FIRST; + + when GET_RST => + rx_state_bits <= x"6"; + rx_rst_i <= '1'; + rx_rst_word_i <= reg_rx_data_in; + rx_state <= FIRST; + + end case; + + if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then + rx_state <= SLEEP; + rx_dlm_word_i <= x"00"; + rx_rst_word_i <= x"00"; + end if; + end process; + +-- we store incoming data in a register + reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_RXI); + reg_rx_k_in <= RX_K_IN when rising_edge(CLK_RXI); + +---------------------------------------------------------------------- +-- Signals out +---------------------------------------------------------------------- + WORD_SYNC_OUT <= sync_k_i; + + RX_DLM_OUT <= rx_dlm_i when rising_edge(CLK_RXI); + RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_RXI); + RX_RST_OUT <= rx_rst_i when rising_edge(CLK_RXI); + RX_RST_WORD_OUT <= rx_rst_word_i when rising_edge(CLK_RXI); + +---------------------------------------------------------------------- +-- Debug and Status +---------------------------------------------------------------------- + STAT_REG_OUT(3 downto 0) <= rx_state_bits; + STAT_REG_OUT(4) <= '0'; + STAT_REG_OUT(5) <= ct_fifo_afull; + STAT_REG_OUT(6) <= ct_fifo_empty; + STAT_REG_OUT(7) <= ct_fifo_write; + STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(CLK_SYS); + STAT_REG_OUT(16) <= rx_data(16); + STAT_REG_OUT(17) <= '0'; + STAT_REG_OUT(31 downto 18) <= (others => '0'); + + DEBUG_OUT(3 downto 0) <= rx_state_bits; + DEBUG_OUT(4) <= '0'; + DEBUG_OUT(5) <= ct_fifo_afull; + DEBUG_OUT(6) <= ct_fifo_empty; + DEBUG_OUT(7) <= ct_fifo_write; + DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); + DEBUG_OUT(16) <= reg_rx_k_in; + DEBUG_OUT(17) <= '0'; + DEBUG_OUT(18) <= '0'; + DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0'; + --DEBUG_OUT(16) <= rx_data(16); + DEBUG_OUT(31 downto 20) <= (others => '0'); + -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); + -- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0); + +end architecture; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 31dcbf5..acde2e6 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -260,6 +260,7 @@ begin current_state <= IDLE; TX_K_OUT <= '1'; TX_DATA_OUT <= K_NULL; +-- toggle_idle <= '1'; -- added else if( rising_edge(CLK_TX) ) then TX_K_OUT <= '0'; @@ -308,11 +309,11 @@ begin current_state <= SEND_RST_H; debug_sending_rst <= '1'; - when IDLE => - TX_DATA_OUT <= K_NULL; - TX_K_OUT <= '1'; - current_state <= SEND_IDLE_L; - -- used to get out of async reset + when IDLE => + TX_DATA_OUT <= K_NULL; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_L; + -- used to get out of async reset when SEND_RST_H => TX_DATA_OUT <= send_rst_word_i; @@ -357,26 +358,29 @@ begin -- ---------------------------------------------------------------------- +send_dlm_i <= SEND_DLM_IN; +send_dlm_word_i <= SEND_DLM_WORD_IN; + --Send DLM message - THE_STORE_DLM_PROC: process( CLK_TX, RESET ) - begin - if( RESET = '1' ) then - send_dlm_i <= '0'; - send_dlm_word_i <= (others => '0'); - elsif( rising_edge(CLK_TX) ) then - if ( link_active_qtx = '0' ) then - send_dlm_i <= '0'; - send_dlm_word_i <= (others => '0'); - elsif( SEND_DLM_IN = '1' ) then - send_dlm_i <= '1'; - send_dlm_word_i <= SEND_DLM_WORD_IN; - elsif( current_state = SEND_DLM_L ) then - send_dlm_i <= '0'; - elsif( current_state = SEND_DLM_H ) then - send_dlm_word_i <= (others => '0'); - end if; - end if; - end process THE_STORE_DLM_PROC; +-- THE_STORE_DLM_PROC: process( CLK_TX, RESET ) +-- begin +-- if( RESET = '1' ) then +-- send_dlm_i <= '0'; +-- send_dlm_word_i <= (others => '0'); +-- elsif( rising_edge(CLK_TX) ) then +-- if ( link_active_qtx = '0' ) then +-- send_dlm_i <= '0'; +-- send_dlm_word_i <= (others => '0'); +-- elsif( SEND_DLM_IN = '1' ) then +-- send_dlm_i <= '1'; +-- send_dlm_word_i <= SEND_DLM_WORD_IN; +-- elsif( current_state = SEND_DLM_L ) then +-- send_dlm_i <= '0'; +-- elsif( current_state = SEND_DLM_H ) then +-- send_dlm_word_i <= (others => '0'); +-- end if; +-- end if; +-- end process THE_STORE_DLM_PROC; --Send RST message THE_STORE_RST_PROC: process( CLK_TX, RESET ) -- 2.43.0