From 07558dc0a0c481b74587c3d4b77cab862f72f2ea Mon Sep 17 00:00:00 2001 From: hadaq Date: Sun, 18 Nov 2012 20:56:04 +0000 Subject: [PATCH] i2c and spi working --- nxyter/compile_frankfurt.pl | 156 --------- nxyter/compile_munich.sh | 5 + nxyter/source/adc_spi_master.vhd | 423 +++++++++++++++++++++++ nxyter/source/adc_spi_readbyte.vhd | 168 +++++++++ nxyter/source/adc_spi_sendbyte.vhd | 157 +++++++++ nxyter/source/nx_data_buffer.vhd | 151 ++++++++ nxyter/source/nx_i2c_master.vhd | 31 +- nxyter/source/nx_i2c_readbyte.vhd | 22 +- nxyter/source/nx_i2c_sendbyte.vhd | 22 +- nxyter/source/nx_i2c_startstop.vhd | 14 +- nxyter/source/nx_timestamp_fifo_read.vhd | 2 +- nxyter/source/nxyter.vhd | 75 ++-- nxyter/source/nxyter_components.vhd | 99 +++++- nxyter/trb3_periph.prj | 31 +- nxyter/trb3_periph.vhd | 151 ++++---- 15 files changed, 1184 insertions(+), 323 deletions(-) delete mode 100755 nxyter/compile_frankfurt.pl create mode 100755 nxyter/compile_munich.sh create mode 100644 nxyter/source/adc_spi_master.vhd create mode 100644 nxyter/source/adc_spi_readbyte.vhd create mode 100644 nxyter/source/adc_spi_sendbyte.vhd create mode 100644 nxyter/source/nx_data_buffer.vhd diff --git a/nxyter/compile_frankfurt.pl b/nxyter/compile_frankfurt.pl deleted file mode 100755 index d1dafbc..0000000 --- a/nxyter/compile_frankfurt.pl +++ /dev/null @@ -1,156 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; -my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); - - -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -execute($c); - -# IOR IO Timing Report -# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -# execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/nxyter/compile_munich.sh b/nxyter/compile_munich.sh new file mode 100755 index 0000000..ed1ab06 --- /dev/null +++ b/nxyter/compile_munich.sh @@ -0,0 +1,5 @@ +#!/bin/sh + +. /usr/local/opt/lattice_diamond/diamond/new/bin/lin/diamond_env + +exec ./compile_munich2.pl diff --git a/nxyter/source/adc_spi_master.vhd b/nxyter/source/adc_spi_master.vhd new file mode 100644 index 0000000..afc61ef --- /dev/null +++ b/nxyter/source/adc_spi_master.vhd @@ -0,0 +1,423 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity adc_spi_master is + generic ( + SPI_SPEED : unsigned(7 downto 0) := x"32" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- SPI connections + SCLK_OUT : out std_logic; + SDIO_INOUT : inout std_logic; + CSB_OUT : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of adc_spi_master is + + signal sdio_i : std_logic; + signal sdio_x : std_logic; + signal sdio : std_logic; + + signal sclk_o : std_logic; + + -- SPI Master + signal csb_o : std_logic; + signal spi_start : std_logic; + + signal spi_busy : std_logic; + signal takeover_sdio : std_logic; + signal wait_timer_init : unsigned(7 downto 0); + signal sendbyte_seq_start : std_logic; + signal readbyte_seq_start : std_logic; + signal sendbyte_byte : std_logic_vector(7 downto 0); + signal read_seq_ctr : std_logic; + signal reg_data : std_logic_vector(31 downto 0); + + signal spi_busy_x : std_logic; + signal wait_timer_init_x : unsigned(7 downto 0); + signal sendbyte_seq_start_x : std_logic; + signal sendbyte_byte_x : std_logic_vector(7 downto 0); + signal readbyte_seq_start_x : std_logic; + signal read_seq_ctr_x : std_logic; + signal reg_data_x : std_logic_vector(31 downto 0); + + signal sdio_sendbyte : std_logic; + signal sclk_sendbyte : std_logic; + signal sendbyte_done : std_logic; + + signal sclk_readbyte : std_logic; + signal readbyte_byte : std_logic_vector(7 downto 0); + signal readbyte_done : std_logic; + + type STATES is (S_RESET, + S_IDLE, + S_START, + S_START_WAIT, + + S_SEND_CMD_A, + S_SEND_CMD_A_WAIT, + S_SEND_CMD_B, + S_SEND_CMD_B_WAIT, + + S_SEND_DATA, + S_SEND_DATA_WAIT, + S_GET_DATA, + S_GET_DATA_WAIT, + + S_STOP, + S_STOP_WAIT + ); + signal STATE, NEXT_STATE : STATES; + + -- SPI Timer + signal wait_timer_done : std_logic; + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal spi_chipid : std_logic_vector(6 downto 0); + signal spi_rw_bit : std_logic; + signal spi_registerid : std_logic_vector(12 downto 0); + signal spi_register_data : std_logic_vector(7 downto 0); + signal spi_register_value_read : std_logic_vector(7 downto 0); + +begin + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + adc_spi_sendbyte_1: adc_spi_sendbyte + generic map ( + SPI_SPEED => SPI_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => sendbyte_seq_start, + BYTE_IN => sendbyte_byte, + SEQUENCE_DONE_OUT => sendbyte_done, + SDIO_OUT => sdio_sendbyte, + SCLK_OUT => sclk_sendbyte + ); + + adc_spi_readbyte_1: adc_spi_readbyte + generic map ( + SPI_SPEED => SPI_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => readbyte_seq_start, + BYTE_OUT => readbyte_byte, + SEQUENCE_DONE_OUT => readbyte_done, + SDIO_IN => sdio, + SCLK_OUT => sclk_readbyte + ); + + -- Debug Line + + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= SCLK_OUT; + DEBUG_OUT(2) <= SDIO_INOUT; + DEBUG_OUT(3) <= CSB_OUT; + DEBUG_OUT(4) <= spi_busy; + DEBUG_OUT(5) <= wait_timer_done; + DEBUG_OUT(6) <= sendbyte_seq_start; + DEBUG_OUT(7) <= sendbyte_done; + DEBUG_OUT(8) <= sclk_sendbyte; + DEBUG_OUT(9) <= sdio_sendbyte; + DEBUG_OUT(10) <= sclk_readbyte; + DEBUG_OUT(11) <= takeover_sdio; + + -- Sync SPI SDIO Line + sdio_i <= SDIO_INOUT; + + PROC_I2C_LINES_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sdio_x <= '1'; + sdio <= '1'; + else + sdio_x <= sdio_i; + sdio <= sdio_x; + end if; + end if; + end process PROC_I2C_LINES_SYNC; + + PROC_I2C_MASTER_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + spi_busy <= '1'; + sendbyte_seq_start <= '0'; + readbyte_seq_start <= '0'; + sendbyte_byte <= (others => '0'); + wait_timer_init <= (others => '0'); + reg_data <= (others => '0'); + read_seq_ctr <= '0'; + STATE <= S_RESET; + else + spi_busy <= spi_busy_x; + sendbyte_seq_start <= sendbyte_seq_start_x; + readbyte_seq_start <= readbyte_seq_start_x; + sendbyte_byte <= sendbyte_byte_x; + wait_timer_init <= wait_timer_init_x; + reg_data <= reg_data_x; + read_seq_ctr <= read_seq_ctr_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_I2C_MASTER_TRANSFER; + + + PROC_I2C_MASTER: process(STATE) + + begin + -- Defaults + takeover_sdio <= '0'; + sclk_o <= '0'; + csb_o <= '0'; + spi_busy_x <= '1'; + sendbyte_seq_start_x <= '0'; + sendbyte_byte_x <= (others => '0'); + readbyte_seq_start_x <= '0'; + wait_timer_init_x <= (others => '0'); + reg_data_x <= reg_data; + read_seq_ctr_x <= read_seq_ctr; + + case STATE is + + when S_RESET => + reg_data_x <= (others => '0'); + NEXT_STATE <= S_IDLE; + + when S_IDLE => + csb_o <= '1'; + if (spi_start = '1') then + reg_data_x <= x"8000_0000"; -- Set Running , clear all other bits + NEXT_STATE <= S_START; + else + spi_busy_x <= '0'; + reg_data_x <= reg_data and x"7fff_ffff"; -- clear running bit; + read_seq_ctr_x <= '0'; + NEXT_STATE <= S_IDLE; + end if; + + -- SPI START Sequence + when S_START => + wait_timer_init_x <= SPI_SPEED srl 2; + NEXT_STATE <= S_START_WAIT; + + when S_START_WAIT => + if (wait_timer_done = '0') then + NEXT_STATE <= S_START_WAIT; + else + takeover_sdio <= '1'; + NEXT_STATE <= S_SEND_CMD_A; + end if; + + -- I2C SEND CMD Part1 + when S_SEND_CMD_A => + takeover_sdio <= '1'; + sendbyte_byte_x(7) <= spi_rw_bit; + sendbyte_byte_x(6 downto 5) <= "00"; + sendbyte_byte_x(4 downto 0) <= spi_registerid(12 downto 8); + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_CMD_A_WAIT; + + when S_SEND_CMD_A_WAIT => + takeover_sdio <= '1'; + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_CMD_A_WAIT; + else + NEXT_STATE <= S_SEND_CMD_B; + end if; + + -- I2C SEND CMD Part1 + when S_SEND_CMD_B => + takeover_sdio <= '1'; + sendbyte_byte_x(7 downto 0) <= spi_registerid(7 downto 0); + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_CMD_B_WAIT; + + when S_SEND_CMD_B_WAIT => + takeover_sdio <= '1'; + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_CMD_B_WAIT; + else + if (spi_rw_bit = '1') then + NEXT_STATE <= S_GET_DATA; + else + NEXT_STATE <= S_SEND_DATA; + end if; + end if; + + -- I2C SEND DataWord + when S_SEND_DATA => + takeover_sdio <= '1'; + sendbyte_byte_x <= spi_register_data; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_DATA_WAIT; + + when S_SEND_DATA_WAIT => + takeover_sdio <= '1'; + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_DATA_WAIT; + else + NEXT_STATE <= S_STOP; + end if; + + -- I2C GET DataWord + when S_GET_DATA => + readbyte_seq_start_x <= '1'; + NEXT_STATE <= S_GET_DATA_WAIT; + + when S_GET_DATA_WAIT => + if (readbyte_done = '0') then + NEXT_STATE <= S_GET_DATA_WAIT; + else + reg_data_x(7 downto 0) <= readbyte_byte; + NEXT_STATE <= S_STOP; + end if; + + -- SPI STOP Sequence + when S_STOP => + wait_timer_init_x <= SPI_SPEED srl 2; + NEXT_STATE <= S_STOP_WAIT; + + when S_STOP_WAIT => + if (wait_timer_done = '0') then + NEXT_STATE <= S_STOP_WAIT; + else + reg_data_x <= reg_data or x"4000_0000"; -- Set DONE Bit + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_I2C_MASTER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + -- + -- Write bit definition + -- ==================== + -- + -- D[31] SPI_GO 0 => don't do anything on SPI, + -- 1 => start SPI access + -- D[30] SPI_ACTION 0 => write byte, 1 => read byte + -- D[20:8] SPI_CMD SPI Register Id + -- D[7:0] SPI_DATA data to be written + -- + -- Read bit definition + -- =================== + -- + -- D[31] RUNNING whatever + -- D[30] SPI_DONE whatever + -- D[29:21] reserved reserved + -- D[20:16] debug subject to change, don't use + -- D[15:8] reserved reserved + -- D[7:0] SPI_DATA result of SPI read operation + -- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + spi_start <= '0'; + + spi_chipid <= (others => '0'); + spi_rw_bit <= '0'; + spi_registerid <= (others => '0'); + spi_register_data <= (others => '0'); + spi_register_value_read <= (others => '0'); + + else + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + spi_start <= '0'; + + if (SLV_WRITE_IN = '1') then + if (spi_busy = '0' and SLV_DATA_IN(31) = '1') then + spi_rw_bit <= SLV_DATA_IN(30); + spi_registerid <= SLV_DATA_IN(20 downto 8); + spi_register_data <= SLV_DATA_IN(7 downto 0); + spi_start <= '1'; + end if; + + elsif (SLV_READ_IN = '1') then + if (spi_busy = '1') then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '1'; + slv_ack_o <= '0'; + else + slv_data_out_o <= reg_data; + end if; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- SPI Outputs + SDIO_INOUT <= sdio_sendbyte when (takeover_sdio = '1') + else 'Z'; + + SCLK_OUT <= sclk_o or + sclk_sendbyte or + sclk_readbyte; + + CSB_OUT <= csb_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/adc_spi_readbyte.vhd b/nxyter/source/adc_spi_readbyte.vhd new file mode 100644 index 0000000..c4ebe00 --- /dev/null +++ b/nxyter/source/adc_spi_readbyte.vhd @@ -0,0 +1,168 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity adc_spi_readbyte is + generic ( + SPI_SPEED : unsigned(7 downto 0) := x"32" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_OUT : out std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- SPI connections + SDIO_IN : in std_logic; + SCLK_OUT : out std_logic + ); +end entity; + +architecture Behavioral of adc_spi_readbyte is + + -- Send Byte + signal sclk_o : std_logic; + signal spi_start : std_logic; + + signal sequence_done_o : std_logic; + signal spi_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal spi_ack_o : std_logic; + signal wait_timer_init : unsigned(7 downto 0); + + signal sequence_done_o_x : std_logic; + signal spi_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal spi_ack_o_x : std_logic; + signal wait_timer_init_x : unsigned(7 downto 0); + + type STATES is (S_IDLE, + S_UNSET_SCKL, + S_UNSET_SCKL_HOLD, + S_GET_BIT, + S_SET_SCKL, + S_NEXT_BIT, + S_DONE + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_READ_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + spi_ack_o <= '0'; + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + spi_byte <= spi_byte_x; + bit_ctr <= bit_ctr_x; + spi_ack_o <= spi_ack_o_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_READ_BYTE_TRANSFER; + + PROC_READ_BYTE: process(STATE) + begin + sclk_o <= '0'; + sequence_done_o_x <= '0'; + spi_byte_x <= spi_byte; + bit_ctr_x <= bit_ctr; + spi_ack_o_x <= spi_ack_o; + wait_timer_init_x <= (others => '0'); + + case STATE is + when S_IDLE => + if (START_IN = '1') then + spi_byte_x <= (others => '0'); + bit_ctr_x <= x"7"; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_UNSET_SCKL; + else + NEXT_STATE <= S_IDLE; + end if; + + -- SPI Read byte + when S_UNSET_SCKL => + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_UNSET_SCKL_HOLD; + + when S_UNSET_SCKL_HOLD => + if (wait_timer_done = '0') then + NEXT_STATE <= S_UNSET_SCKL_HOLD; + else + NEXT_STATE <= S_GET_BIT; + end if; + + when S_GET_BIT => + spi_byte_x(0) <= SDIO_IN; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SCKL; + + when S_SET_SCKL => + sclk_o <= '1'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCKL; + else + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sclk_o <= '1'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + spi_byte_x <= spi_byte sll 1; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_UNSET_SCKL; + else + NEXT_STATE <= S_DONE; + end if; + + when S_DONE => + sclk_o <= '1'; + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + + end case; + end process PROC_READ_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + BYTE_OUT <= spi_byte; + + -- I2c Outputs + SCLK_OUT <= sclk_o; + +end Behavioral; diff --git a/nxyter/source/adc_spi_sendbyte.vhd b/nxyter/source/adc_spi_sendbyte.vhd new file mode 100644 index 0000000..d8edfed --- /dev/null +++ b/nxyter/source/adc_spi_sendbyte.vhd @@ -0,0 +1,157 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity adc_spi_sendbyte is + generic ( + SPI_SPEED : unsigned(7 downto 0) := x"32" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- SPI connections + SCLK_OUT : out std_logic; + SDIO_OUT : out std_logic + ); +end entity; + +architecture Behavioral of adc_spi_sendbyte is + + -- Send Byte + signal sclk_o : std_logic; + signal sdio_o : std_logic; + signal spi_start : std_logic; + + signal sequence_done_o : std_logic; + signal spi_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal wait_timer_init : unsigned(7 downto 0); + + signal sequence_done_o_x : std_logic; + signal spi_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal wait_timer_init_x : unsigned(7 downto 0); + + type STATES is (S_IDLE, + S_SET_SDIO, + S_SET_SCLK, + S_NEXT_BIT, + S_DONE + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_SEND_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + spi_byte <= spi_byte_x; + bit_ctr <= bit_ctr_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_SEND_BYTE_TRANSFER; + + PROC_SEND_BYTE: process(STATE) + begin + sdio_o <= '0'; + sclk_o <= '0'; + sequence_done_o_x <= '0'; + spi_byte_x <= spi_byte; + bit_ctr_x <= bit_ctr; + wait_timer_init_x <= (others => '0'); + + case STATE is + when S_IDLE => + if (START_IN = '1') then + spi_byte_x <= BYTE_IN; + bit_ctr_x <= x"7"; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SDIO; + else + NEXT_STATE <= S_IDLE; + end if; + + when S_SET_SDIO => + sdio_o <= spi_byte(7); + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SDIO; + else + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SCLK; + end if; + + when S_SET_SCLK => + sdio_o <= spi_byte(7); + sclk_o <= '1'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCLK; + else + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sdio_o <= spi_byte(7); + sclk_o <= '1'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + spi_byte_x <= spi_byte sll 1; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SDIO; + else + NEXT_STATE <= S_DONE; + end if; + + when S_DONE => + sdio_o <= spi_byte(7); + sclk_o <= '1'; + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + + end case; + end process PROC_SEND_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + + -- SPI Outputs + SDIO_OUT <= sdio_o; + SCLK_OUT <= sclk_o; + +end Behavioral; diff --git a/nxyter/source/nx_data_buffer.vhd b/nxyter/source/nx_data_buffer.vhd new file mode 100644 index 0000000..815156f --- /dev/null +++ b/nxyter/source/nx_data_buffer.vhd @@ -0,0 +1,151 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.nxyter_components.all; + +entity nx_data_buffer is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- Data Buffer FIFO + FIFO_DATA_IN : std_logic_vector(31 downto 0); + FIFO_WRITE_ENABLE_IN : std_logic; + FIFO_READ_ENABLE_IN : std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + +end nx_data_buffer; + +architecture Behavioral of nx_data_buffer is + +-- FIFO Handler + signal fifo_o : std_logic_vector(31 downto 0); + signal fifo_empty : std_logic; + signal fifo_full : std_logic; + signal fifo_read_enable : std_logic; + signal fifo_write_enable : std_logic; + +-- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal register_fifo_status : std_logic_vector(31 downto 0); + signal register_write_enable : std_logic; + +begin + +------------------------------------------------------------------------------- +-- FIFO Handler +------------------------------------------------------------------------------- + fifo_32_data_1: fifo_32_data + port map ( + Data => FIFO_DATA_IN, + Clock => CLK_IN, + WrEn => fifo_write_enable, + RdEn => fifo_read_enable, + Reset => RESET_IN, + Q => fifo_o, + Empty => fifo_empty, + Full => fifo_full + ); + + PROC_FIFO_HANDLER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + fifo_write_enable <= '0'; + fifo_read_enable <= '0'; + else + fifo_write_enable <= '1'; + fifo_read_enable <= '1'; + + if (fifo_full = '1' + or FIFO_WRITE_ENABLE_IN = '0' + or register_write_enable <= '0') then + fifo_write_enable <= '0'; + end if; + + if (fifo_empty = '1' or FIFO_READ_ENABLE_IN = '0') then + fifo_read_enable <= '0'; + end if; + + end if; + end if; + end process PROC_FIFO_HANDLER; + +------------------------------------------------------------------------------- +-- Slave Bus Slow Control +------------------------------------------------------------------------------- + + register_fifo_status(0) <= fifo_write_enable; + register_fifo_status(1) <= fifo_full; + register_fifo_status(3 downto 2) <= (others => '0'); + register_fifo_status(4) <= fifo_read_enable; + register_fifo_status(5) <= fifo_empty; + register_fifo_status(7 downto 6) <= (others => '0'); + register_fifo_status(31 downto 8) <= (others => '0'); + + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + register_write_enable <= '0'; + else + slv_data_out_o <= (others => '0'); + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + + if (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => if (fifo_empty = '1') then + slv_no_more_data_o <= '1'; + else + slv_data_out_o <= fifo_o; + slv_ack_o <= '1'; + end if; + when x"0001" => slv_data_out_o <= register_fifo_status; + when others => slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + elsif (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0001" => register_write_enable <= SLV_DATA_IN(0); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + +-- Output Signals + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_master.vhd b/nxyter/source/nx_i2c_master.vhd index 8f1b799..b30647c 100644 --- a/nxyter/source/nx_i2c_master.vhd +++ b/nxyter/source/nx_i2c_master.vhd @@ -7,7 +7,7 @@ use work.nxyter_components.all; entity nx_i2c_master is generic ( - i2c_speed : unsigned(11 downto 0) := x"3e8" + I2C_SPEED : unsigned(11 downto 0) := x"3e8" ); port( CLK_IN : in std_logic; @@ -58,7 +58,6 @@ architecture Behavioral of nx_i2c_master is signal i2c_busy_x : std_logic; signal startstop_select_x : std_logic; signal startstop_seq_start_x : std_logic; - signal wait_timer_init_x : std_logic_vector(11 downto 0); signal sendbyte_seq_start_x : std_logic; signal sendbyte_byte_x : std_logic_vector(7 downto 0); signal readbyte_seq_start_x : std_logic; @@ -99,11 +98,6 @@ architecture Behavioral of nx_i2c_master is ); signal STATE, NEXT_STATE : STATES; - - -- I2C Timer - signal wait_timer_init : unsigned(11 downto 0); - signal wait_timer_done : std_logic; - -- TRBNet Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -117,22 +111,10 @@ architecture Behavioral of nx_i2c_master is begin - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 12 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - -- Start / Stop Sequence nx_i2c_startstop_1: nx_i2c_startstop generic map ( - i2c_speed => i2c_speed + I2C_SPEED => I2C_SPEED ) port map ( CLK_IN => CLK_IN, @@ -147,7 +129,7 @@ begin nx_i2c_sendbyte_1: nx_i2c_sendbyte generic map ( - i2c_speed => i2c_speed + I2C_SPEED => I2C_SPEED ) port map ( CLK_IN => CLK_IN, @@ -163,7 +145,7 @@ begin nx_i2c_readbyte_1: nx_i2c_readbyte generic map ( - i2c_speed => i2c_speed + I2C_SPEED => I2C_SPEED ) port map ( CLK_IN => CLK_IN, @@ -228,7 +210,6 @@ begin sendbyte_seq_start <= '0'; readbyte_seq_start <= '0'; sendbyte_byte <= (others => '0'); - wait_timer_init <= (others => '0'); reg_data <= (others => '0'); read_seq_ctr <= '0'; STATE <= S_RESET; @@ -239,7 +220,6 @@ begin sendbyte_seq_start <= sendbyte_seq_start_x; readbyte_seq_start <= readbyte_seq_start_x; sendbyte_byte <= sendbyte_byte_x; - wait_timer_init <= wait_timer_init_x; reg_data <= reg_data_x; read_seq_ctr <= read_seq_ctr_x; STATE <= NEXT_STATE; @@ -260,7 +240,6 @@ begin sendbyte_seq_start_x <= '0'; sendbyte_byte_x <= (others => '0'); readbyte_seq_start_x <= '0'; - wait_timer_init_x <= (others => '0'); reg_data_x <= reg_data; read_seq_ctr_x <= read_seq_ctr; @@ -416,12 +395,10 @@ begin -- D[23:16] I2C_ADDRESS address of I2C chip -- D[15:8] I2C_CMD command byte for access -- D[7:0] I2C_DATA data to be written - -- -- -- Read bit definition -- =================== -- - -- D[31:24] status status information -- D[31] RUNNING whatever -- D[30] I2C_DONE whatever -- D[29] ERROR_RADDACK no acknowledge for repeated address byte diff --git a/nxyter/source/nx_i2c_readbyte.vhd b/nxyter/source/nx_i2c_readbyte.vhd index 42857f9..497c5a4 100644 --- a/nxyter/source/nx_i2c_readbyte.vhd +++ b/nxyter/source/nx_i2c_readbyte.vhd @@ -8,7 +8,7 @@ use work.nxyter_components.all; entity nx_i2c_readbyte is generic ( - i2c_speed : unsigned(11 downto 0) := x"3e8" + I2C_SPEED : unsigned(11 downto 0) := x"3e8" ); port( CLK_IN : in std_logic; @@ -36,7 +36,7 @@ architecture Behavioral of nx_i2c_readbyte is signal i2c_byte : unsigned(7 downto 0); signal bit_ctr : unsigned(3 downto 0); signal i2c_ack_o : std_logic; - signal wait_timer_init : unsigned(11 downto 0); + signal wait_timer_init : unsigned(11 downto 0); signal sequence_done_o_x : std_logic; signal i2c_byte_x : unsigned(7 downto 0); @@ -125,7 +125,7 @@ begin when S_INIT => sda_o <= '0'; scl_o <= '0'; - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_INIT_WAIT; when S_INIT_WAIT => @@ -141,7 +141,7 @@ begin when S_READ_BYTE => scl_o <= '0'; bit_ctr_x <= x"7"; - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_UNSET_SCL1; when S_UNSET_SCL1 => @@ -149,7 +149,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_UNSET_SCL1; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_SET_SCL1; end if; @@ -157,7 +157,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_SET_SCL1; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_GET_BIT; end if; @@ -169,7 +169,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_SET_SCL2; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_UNSET_SCL2; end if; @@ -186,10 +186,10 @@ begin if (bit_ctr > 0) then bit_ctr_x <= bit_ctr - 1; i2c_byte_x <= i2c_byte sll 1; - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_UNSET_SCL1; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_SET_ACK; end if; @@ -200,7 +200,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_SET_ACK; else - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_ACK_SET_SCL; end if; @@ -209,7 +209,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_ACK_SET_SCL; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_ACK_UNSET_SCL; end if; diff --git a/nxyter/source/nx_i2c_sendbyte.vhd b/nxyter/source/nx_i2c_sendbyte.vhd index 88d0be9..5148529 100644 --- a/nxyter/source/nx_i2c_sendbyte.vhd +++ b/nxyter/source/nx_i2c_sendbyte.vhd @@ -8,7 +8,7 @@ use work.nxyter_components.all; entity nx_i2c_sendbyte is generic ( - i2c_speed : unsigned(11 downto 0) := x"3e8" + I2C_SPEED : unsigned(11 downto 0) := x"3e8" ); port( CLK_IN : in std_logic; @@ -37,7 +37,7 @@ architecture Behavioral of nx_i2c_sendbyte is signal i2c_byte : unsigned(7 downto 0); signal bit_ctr : unsigned(3 downto 0); signal i2c_ack_o : std_logic; - signal wait_timer_init : unsigned(11 downto 0); + signal wait_timer_init : unsigned(11 downto 0); signal sequence_done_o_x : std_logic; signal i2c_byte_x : unsigned(7 downto 0); @@ -125,7 +125,7 @@ begin when S_INIT => sda_o <= '0'; scl_o <= '0'; - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_INIT_WAIT; when S_INIT_WAIT => @@ -142,7 +142,7 @@ begin sda_o <= '0'; scl_o <= '0'; bit_ctr_x <= x"7"; - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_SET_SDA; when S_SET_SDA => @@ -151,7 +151,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_SET_SDA; else - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_SET_SCL; end if; @@ -160,7 +160,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_SET_SCL; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_UNSET_SCL; end if; @@ -179,10 +179,10 @@ begin if (bit_ctr > 0) then bit_ctr_x <= bit_ctr - 1; i2c_byte_x <= i2c_byte sll 1; - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_SET_SDA; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_GET_ACK; end if; @@ -192,7 +192,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_GET_ACK; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_ACK_SET_SCL; end if; @@ -200,7 +200,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_ACK_SET_SCL; else - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_STORE_ACK; end if; @@ -209,7 +209,7 @@ begin NEXT_STATE <= S_STORE_ACK; else i2c_ack_o_x <= not SDA_IN; - wait_timer_init_x <= i2c_speed srl 2; + wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_ACK_UNSET_SCL; end if; diff --git a/nxyter/source/nx_i2c_startstop.vhd b/nxyter/source/nx_i2c_startstop.vhd index 82d612a..b413390 100644 --- a/nxyter/source/nx_i2c_startstop.vhd +++ b/nxyter/source/nx_i2c_startstop.vhd @@ -7,7 +7,7 @@ use work.nxyter_components.all; entity nx_i2c_startstop is generic ( - i2c_speed : unsigned(11 downto 0) := x"3e8" + I2C_SPEED : unsigned(11 downto 0) := x"3e8" ); port( CLK_IN : in std_logic; @@ -103,14 +103,14 @@ begin -- I2C START Sequence when S_START => - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_WAIT_START_1; when S_WAIT_START_1 => if (wait_timer_done = '0') then NEXT_STATE <= S_WAIT_START_1; else - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_WAIT_START_2; end if; @@ -119,7 +119,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_WAIT_START_2; else - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_WAIT_START_3; end if; @@ -137,7 +137,7 @@ begin when S_STOP => sda_o <= '0'; scl_o <= '0'; - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_WAIT_STOP_1; when S_WAIT_STOP_1 => @@ -146,7 +146,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_WAIT_STOP_1; else - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_WAIT_STOP_2; end if; @@ -155,7 +155,7 @@ begin if (wait_timer_done = '0') then NEXT_STATE <= S_WAIT_STOP_2; else - wait_timer_init_x <= i2c_speed srl 1; + wait_timer_init_x <= I2C_SPEED srl 1; NEXT_STATE <= S_WAIT_STOP_3; end if; diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index f444ac7..7043f6c 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -177,7 +177,7 @@ begin if( RESET_IN = '1' ) then frame_clock_ctr <= (others => '0'); nx_frame_clock_o <= '0'; - frame_tag_o <= '1'; + frame_tag_o <= '0'; else case frame_clock_ctr is diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index 5c69f69..3a7b99b 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -85,10 +85,6 @@ architecture Behavioral of nXyter_FEE_board is signal slv_unknown_addr : std_logic_vector(8-1 downto 0); -- I2C Master --- ADCM signal i2c_sda_o : std_logic; --- ADCM signal i2c_sda_i : std_logic; --- ADCM signal i2c_scl_o : std_logic; --- ADCM signal i2c_scl_i : std_logic; signal i2c_sm_reset_o : std_logic; signal i2c_reg_reset_o : std_logic; @@ -111,17 +107,17 @@ begin ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- - DEBUG_LINE_OUT(0) <= CLK_IN; - DEBUG_LINE_OUT(1) <= NX_CLK128_IN; - DEBUG_LINE_OUT(2) <= ADC_SC_CLK32_OUT; - DEBUG_LINE_OUT(3) <= ADC_FCLK_IN; - DEBUG_LINE_OUT(4) <= ADC_DCLK_IN; - DEBUG_LINE_OUT(5) <= ADC_NX_IN; - DEBUG_LINE_OUT(6) <= ADC_A_IN; - DEBUG_LINE_OUT(7) <= ADC_B_IN; - DEBUG_LINE_OUT(8) <= ADC_D_IN; - - DEBUG_LINE_OUT(15 downto 9) <= (others => '0'); +-- DEBUG_LINE_OUT(0) <= CLK_IN; +-- DEBUG_LINE_OUT(1) <= NX_CLK128_IN; +-- DEBUG_LINE_OUT(2) <= ADC_SC_CLK32_OUT; +-- DEBUG_LINE_OUT(3) <= ADC_FCLK_IN; +-- DEBUG_LINE_OUT(4) <= ADC_DCLK_IN; +-- DEBUG_LINE_OUT(5) <= ADC_NX_IN; +-- DEBUG_LINE_OUT(6) <= ADC_A_IN; +-- DEBUG_LINE_OUT(7) <= ADC_B_IN; +-- DEBUG_LINE_OUT(8) <= ADC_D_IN; +-- +-- DEBUG_LINE_OUT(15 downto 9) <= (others => '0'); -- -- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN; -- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN; @@ -143,8 +139,6 @@ begin -- Port Maps ------------------------------------------------------------------------------- - - pll_nx_clk256_1: pll_nx_clk256 port map ( CLK => CLK_IN, @@ -158,18 +152,18 @@ begin THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 4, + PORT_NUMBER => 5, PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler 1 => x"0040", -- I2C master 2 => x"0100", -- Timestamp Fifo 3 => x"0200", -- Data Buffer - -- 3 => x"d100", -- SPI data memory + 4 => x"0060", -- SPI Master others => x"0000"), PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler 1 => 0, -- I2C master 2 => 1, -- Timestamp Fifo 3 => 1, -- Data Buffer - -- 3 => 6, -- SPI data memory + 4 => 0, -- Master others => 0) ) port map( @@ -238,7 +232,19 @@ begin BUS_WRITE_ACK_IN(3) => slv_ack(3), BUS_NO_MORE_DATA_IN(3) => slv_no_more_data(3), BUS_UNKNOWN_ADDR_IN(3) => slv_unknown_addr(3), - + + -- SPI master + BUS_READ_ENABLE_OUT(4) => slv_read(4), + BUS_WRITE_ENABLE_OUT(4) => slv_write(4), + BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), + BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), + BUS_ADDR_OUT(4*16+15 downto 4*16) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATAREADY_IN(4) => slv_ack(4), + BUS_WRITE_ACK_IN(4) => slv_ack(4), + BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4), + BUS_UNKNOWN_ADDR_IN(4) => slv_unknown_addr(4), + ---- SPI control registers --BUS_READ_ENABLE_OUT(4) => slv_read(4), --BUS_WRITE_ENABLE_OUT(4) => slv_write(4), @@ -297,7 +303,7 @@ begin nx_i2c_master_1: nx_i2c_master generic map ( - i2c_speed => x"3e8" + I2C_SPEED => x"3e8" ) port map ( CLK_IN => CLK_IN, @@ -313,7 +319,32 @@ begin SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1), DEBUG_OUT => open ); + +------------------------------------------------------------------------------- +-- SPI master block to access the ADC +------------------------------------------------------------------------------- + adc_spi_master_1: adc_spi_master + generic map ( + SPI_SPEED => x"32" + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SCLK_OUT => SPI_SCLK_OUT, + SDIO_INOUT => SPI_SDIO_INOUT, + CSB_OUT => SPI_CSB_OUT, + SLV_READ_IN => slv_read(4), + SLV_WRITE_IN => slv_write(4), + SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), + SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32), + SLV_ACK_OUT => slv_ack(4), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4), + DEBUG_OUT => DEBUG_LINE_OUT + -- DEBUG_OUT => open + ); + ------------------------------------------------------------------------------- -- nXyter TimeStamp Read ------------------------------------------------------------------------------- diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index c0806ea..39ea853 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -60,7 +60,7 @@ end component; component nx_i2c_master generic ( - i2c_speed : unsigned(11 downto 0) + I2C_SPEED : unsigned(11 downto 0) ); port ( CLK_IN : in std_logic; @@ -78,21 +78,10 @@ component nx_i2c_master ); end component; -component nx_timer - generic ( - CTR_WIDTH : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TIMER_START_IN : in unsigned(11 downto 0); - TIMER_DONE_OUT : out std_logic - ); -end component; - component nx_i2c_startstop generic ( - i2c_speed : unsigned(11 downto 0)); + I2C_SPEED : unsigned(11 downto 0) + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -107,7 +96,7 @@ end component; component nx_i2c_sendbyte generic ( - i2c_speed : unsigned(11 downto 0) + I2C_SPEED : unsigned(11 downto 0) ); port ( CLK_IN : in std_logic; @@ -124,7 +113,7 @@ end component; component nx_i2c_readbyte generic ( - i2c_speed : unsigned(11 downto 0) + I2C_SPEED : unsigned(11 downto 0) ); port ( CLK_IN : in std_logic; @@ -138,6 +127,61 @@ component nx_i2c_readbyte ); end component; +------------------------------------------------------------------------------- +-- ADC SPI Interface +------------------------------------------------------------------------------- + +component adc_spi_master + generic ( + SPI_SPEED : unsigned(7 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SCLK_OUT : out std_logic; + SDIO_INOUT : inout std_logic; + CSB_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; + +component adc_spi_sendbyte + generic ( + SPI_SPEED : unsigned(7 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SCLK_OUT : out std_logic; + SDIO_OUT : out std_logic + ); +end component; + +component adc_spi_readbyte + generic ( + SPI_SPEED : unsigned(7 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + BYTE_OUT : out std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SDIO_IN : in std_logic; + SCLK_OUT : out std_logic + ); +end component; + ------------------------------------------------------------------------------- -- TRBNet Registers ------------------------------------------------------------------------------- @@ -212,7 +256,8 @@ end component; component Gray_Decoder generic ( - WIDTH : integer); + WIDTH : integer + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -224,7 +269,8 @@ end component; component Gray_Encoder generic ( - WIDTH : integer); + WIDTH : integer + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -272,6 +318,22 @@ component pll_nx_clk256 LOCK : out std_logic); end component; +------------------------------------------------------------------------------- +-- Misc Tools +------------------------------------------------------------------------------- + +component nx_timer + generic ( + CTR_WIDTH : integer + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TIMER_START_IN : in unsigned(CTR_WIDTH - 1 downto 0); + TIMER_DONE_OUT : out std_logic + ); +end component; + ------------------------------------------------------------------------------- -- Simulations ------------------------------------------------------------------------------- @@ -285,5 +347,4 @@ component nxyter_timestamp_sim ); end component; - end package; diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 0a93884..c1bf9e4 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -146,13 +146,24 @@ add_file -vhdl -lib "work" "./source/adcmv3_components.vhd" add_file -vhdl -lib "work" "./source/nxyter_components.vhd" add_file -vhdl -lib "work" "./source/nxyter.vhd" -add_file -vhdl -lib "work" "./source/slave_bus.vhd" -#add_file -vhdl -lib "work" "./source/slv_ped_thr_mem.vhd" -add_file -vhdl -lib "work" "./source/slv_register.vhd" -#add_file -vhdl -lib "work" "./source/gray_decoder.vhd" - -add_file -vhdl -lib "work" "./source/i2c_gstart.vhd" -add_file -vhdl -lib "work" "./source/i2c_master.vhd" -add_file -vhdl -lib "work" "./source/i2c_sendb.vhd" -add_file -vhdl -lib "work" "./source/i2c_slim.vhd" - +add_file -vhdl -lib "work" "./source/pll_nx_clk256.vhd" +add_file -vhdl -lib "work" "./source/nxyter_registers.vhd" +add_file -vhdl -lib "work" "./source/nx_timestamp_fifo_read.vhd" +add_file -vhdl -lib "work" "./source/fifo_dc_9to36.vhd" +add_file -vhdl -lib "work" "./source/level_to_pulse.vhd" +add_file -vhdl -lib "work" "./source/gray_decoder.vhd" +add_file -vhdl -lib "work" "./source/gray_encoder.vhd" +add_file -vhdl -lib "work" "./source/nx_data_buffer.vhd" +add_file -vhdl -lib "work" "./source/fifo_32_data.vhd" +add_file -vhdl -lib "work" "./source/nx_timer.vhd" + +add_file -vhdl -lib "work" "./source/nx_i2c_master.vhd" +add_file -vhdl -lib "work" "./source/nx_i2c_startstop.vhd" +add_file -vhdl -lib "work" "./source/nx_i2c_sendbyte.vhd" +add_file -vhdl -lib "work" "./source/nx_i2c_readbyte.vhd" + +add_file -vhdl -lib "work" "./source/adc_spi_master.vhd" +add_file -vhdl -lib "work" "./source/adc_spi_sendbyte.vhd" +add_file -vhdl -lib "work" "./source/adc_spi_readbyte.vhd" + +add_file -vhdl -lib "work" "./source/nx_timestamp_sim.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 9aec957..d6a6f83 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -39,11 +39,11 @@ entity trb3_periph is NX1_RESET_OUT : out std_logic; NX1_I2C_SDA_INOUT : inout std_logic; - NX1_I2C_SCL_OUT : out std_logic; + NX1_I2C_SCL_INOUT : inout std_logic; NX1_I2C_SM_RESET_OUT : out std_logic; NX1_I2C_REG_RESET_OUT : out std_logic; NX1_SPI_SCLK_OUT : out std_logic; - NX1_SPI_SDIO_INOUT : in std_logic; + NX1_SPI_SDIO_INOUT : inout std_logic; NX1_SPI_CSB_OUT : out std_logic; NX1_CLK128_IN : in std_logic; NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0); @@ -61,14 +61,14 @@ entity trb3_periph is NX2_RESET_OUT : out std_logic; NX2_I2C_SDA_INOUT : inout std_logic; - NX2_I2C_SCL_OUT : out std_logic; + NX2_I2C_SCL_INOUT : inout std_logic; NX2_I2C_SM_RESET_OUT : out std_logic; NX2_I2C_REG_RESET_OUT : out std_logic; NX2_SPI_SCLK_OUT : out std_logic; - NX2_SPI_SDIO_INOUT : in std_logic; + NX2_SPI_SDIO_INOUT : inout std_logic; NX2_SPI_CSB_OUT : out std_logic; NX2_CLK128_IN : in std_logic; - NX2_IN : in std_logic_vector (7 downto 0); + NX2_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX2_CLK256A_OUT : out std_logic; NX2_TESTPULSE_OUT : out std_logic; NX2_ADC_FCLK_IN : in std_logic; @@ -264,6 +264,9 @@ architecture trb3_periph_arch of trb3_periph is signal nx1_regio_no_more_data_out : std_logic; signal nx1_regio_unknown_addr_out : std_logic; + signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0); + signal nx1_clk128_sim_o : std_logic; + -- nXyter 1 Regio Bus signal nx2_regio_addr_in : std_logic_vector (15 downto 0); signal nx2_regio_data_in : std_logic_vector (31 downto 0); @@ -480,16 +483,16 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 4, + PORT_NUMBER => 3, PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8000", - 3 => x"9000", + -- 3 => x"9000", others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, - 2 => 15, - 3 => 15, + 2 => 12, + -- 3 => 12, others => 0) ) port map( @@ -508,54 +511,55 @@ begin DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', --Bus Handler (nXyter1 trb_net16_regio_bus_handler) - BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in, - BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in, - BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in, - BUS_ADDR_OUT(2*16+15 downto 2*16) => nx1_regio_addr_in, - BUS_TIMEOUT_OUT(2) => nx1_regio_timeout_in, - BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out, - BUS_DATAREADY_IN(2) => nx1_regio_dataready_out, - BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out, - BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out, - - --Bus Handler (nXyter2 trb_net16_regio_bus_handler) - BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in, - BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in, - BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in, - BUS_ADDR_OUT(3*16+15 downto 3*16) => nx2_regio_addr_in, - BUS_TIMEOUT_OUT(3) => nx2_regio_timeout_in, - BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out, - BUS_DATAREADY_IN(3) => nx2_regio_dataready_out, - BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out, - BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out, + BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in, + BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in, + BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in, + BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0), + BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open, + BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in, + BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out, + BUS_DATAREADY_IN(2) => nx1_regio_dataready_out, + BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out, + BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out, + BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out, + + -- --Bus Handler (nXyter2 trb_net16_regio_bus_handler) + -- BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in, + -- BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in, + -- BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in, + -- BUS_ADDR_OUT(3*16+15 downto 3*16) => nx2_regio_addr_in, + -- BUS_TIMEOUT_OUT(3) => nx2_regio_timeout_in, + -- BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out, + -- BUS_DATAREADY_IN(3) => nx2_regio_dataready_out, + -- BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out, + -- BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out, + -- BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out, STAT_DEBUG => open ); @@ -643,7 +647,7 @@ begin RESET_IN => reset_i, I2C_SDA_INOUT => NX1_I2C_SDA_INOUT, - I2C_SCL_OUT => NX1_I2C_SCL_OUT, + I2C_SCL_INOUT => NX1_I2C_SCL_INOUT, I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT, I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT, @@ -653,6 +657,9 @@ begin NX_CLK128_IN => NX1_CLK128_IN, NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN, +-- NX_CLK128_IN => nx1_clk128_sim_o, +-- NX_TIMESTAMP_IN => nx1_timestamp_sim_o, + NX_RESET_OUT => NX1_RESET_OUT, NX_CLK256A_OUT => NX1_CLK256A_OUT, NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, @@ -674,15 +681,41 @@ begin REGIO_DATAREADY_OUT => nx1_regio_dataready_out, REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out, REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out, - REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out + REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out, + + CLK_128_IN => CLK_GPLL_LEFT, + DEBUG_LINE_OUT => TEST_LINE + -- DEBUG_LINE_OUT => open ); + + -- TEST_LINE(0) <= clk_100_i; + -- TEST_LINE(1) <= clk_200_i; + -- TEST_LINE(2) <= NX1_CLK128_IN; + -- TEST_LINE(3) <= NX2_CLK128_IN; + -- TEST_LINE(7 downto 4) <= (others => '0'); + -- TEST_LINE(11 downto 8) <= NX1_TIMESTAMP_IN(3 downto 0); + -- TEST_LINE(15 downto 12) <= NX2_TIMESTAMP_IN(3 downto 0); + + + +------------------------------------------------------------------------------- +-- Timestamp Simulator +------------------------------------------------------------------------------- +-- nxyter_timestamp_sim_1: nxyter_timestamp_sim +-- port map ( +-- CLK_IN => CLK_GPLL_LEFT, +-- RESET_IN => reset_i, +-- TIMESTAMP_OUT => nx1_timestamp_sim_o, +-- CLK128_OUT => nx1_clk128_sim_o +-- ); + --------------------------------------------------------------------------- -- Test Connector - Logic Analyser --------------------------------------------------------------------------- - TEST_LINE(15 downto 0) <= (others => '0'); - + -- TEST_LINE(15 downto 0) <= (others => '0'); + end architecture; -- 2.43.0