From 07dd2912f8086eb0b56a1bdd8c5355695ae5eccd Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 21 Dec 2021 13:42:19 +0100 Subject: [PATCH] reset issues to be handled --- code/clock_reset_handler.vhd | 11 +++++------ cts/trb3sc_cts.vhd | 6 ++++-- hub/trb3sc_hub.vhd | 19 +++++++++++++------ tdctemplate/trb3sc_tdctemplate.vhd | 10 ++++++---- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 1272a73..9681112 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -10,7 +10,6 @@ library work; -- REMARK: USE_RXCLOCK doesnt't make sense here, can be removed -- REMARK: USE_EXTERNAL_CLOCK seems to be mandatory, can be simplified --- REMARK: RESET_ROM_NET should be RESET_FROM_NET_IN entity clock_reset_handler is port( @@ -21,18 +20,18 @@ entity clock_reset_handler is GLOBAL_RESET_IN : in std_logic; -- from Link Layer RESET_FROM_NET_IN : in std_logic := '0'; -- stat_op(13) SEND_RESET_IN : in std_logic := '0'; -- stat_op(15) - + BUS_RX : in CTRLBUS_RX; -- NOT USED BUS_TX : out CTRLBUS_TX; -- NOT USED RESET_OUT : out std_logic; CLEAR_OUT : out std_logic; GSR_OUT : out std_logic; - + FULL_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock - + ENPIRION_CLOCK : out std_logic; LED_RED_OUT : out std_logic_vector( 1 downto 0); LED_GREEN_OUT : out std_logic_vector( 1 downto 0); @@ -225,9 +224,9 @@ clear_n_i <= timer(27-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN); THE_RESET_HANDLER : trb_net_reset_handler generic map( RESET_DELAY => x"FEEE" - ) + ) port map( - CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_IN => GLOBAL_RESET_IN, -- reset input (high active, async) CLEAR_N_IN => clear_n_i, -- reset input (low active, async) CLK_IN => INT_CLK_IN, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_selected_half, -- PLL/DLL remastered clock diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index aed6cd4..a0b12b0 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -293,7 +293,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler reset_via_gbe_long <= reset_via_gbe_timer; end if; last_reset_via_gbe_long <= reset_via_gbe_long; - make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; -- pulse, 1 clock cycle end process; pll_calibration : entity work.pll_in125_out33 @@ -353,8 +353,10 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => clk_full_osc, -- CTS MASTER MASTER_CLK_OUT => master_clk_i, - GLOBAL_RESET_IN => '0', -- check + QUAD_RST_IN => '0', -- check GLOBAL_RESET_OUT => open, + SLAVE_ACTIVE_OUT => open, + SLAVE_ACTIVE_IN => '1', TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index ffb23b7..27b1e45 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -164,7 +164,7 @@ architecture trb3sc_arch of trb3sc_hub is signal word_sync_i : std_logic; signal master_clk_i : std_logic; - signal master_reset_i : std_logic; + signal global_reset_i : std_logic; signal tx_pll_lol_qd_a_i : std_logic; signal tx_pll_lol_qd_b_i : std_logic; signal tx_pll_lol_qd_c_i : std_logic; @@ -174,6 +174,7 @@ architecture trb3sc_arch of trb3sc_hub is signal tx_pcs_rst_i : std_logic; signal sync_tx_quad_i : std_logic; signal link_tx_ready_i : std_logic; + signal slave_active_i : std_logic; signal rx_dlm_i : std_logic; signal tx_reset_state : std_logic_vector(3 downto 0); signal debug_i : std_logic_vector(31 downto 0); @@ -188,7 +189,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full, NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half, - GLOBAL_RESET_IN => master_reset_i, -- BUG + GLOBAL_RESET_IN => global_reset_i, -- BUG RESET_FROM_NET_IN => med2int(INTERFACE_NUM-1).stat_op(13), SEND_RESET_IN => med2int(INTERFACE_NUM-1).stat_op(15), BUS_RX => bustc_rx, @@ -331,8 +332,10 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => master_clk_i, - GLOBAL_RESET_IN => '0', - GLOBAL_RESET_OUT => master_reset_i, + QUAD_RST_IN => '0', + GLOBAL_RESET_OUT => global_reset_i, + SLAVE_ACTIVE_OUT => slave_active_i, + SLAVE_ACTIVE_IN => slave_active_i, TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, @@ -422,8 +425,10 @@ end generate; WORD_SYNC_OUT => open, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - GLOBAL_RESET_IN => master_reset_i, + QUAD_RST_IN => global_reset_i, GLOBAL_RESET_OUT => open, + SLAVE_ACTIVE_OUT => open, + SLAVE_ACTIVE_IN => slave_active_i, TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, @@ -491,8 +496,10 @@ gen_PCSD : if INCLUDE_GBE = c_NO generate WORD_SYNC_OUT => open, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - GLOBAL_RESET_IN => master_reset_i, + QUAD_RST_IN => global_reset_i, GLOBAL_RESET_OUT => open, + SLAVE_ACTIVE_OUT => open, + SLAVE_ACTIVE_IN => slave_active_i, TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 696d9b5..f5ed104 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -157,7 +157,7 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal master_clk_i : std_logic; signal tx_reset_state : std_logic_vector(3 downto 0); - signal master_reset_i : std_logic; + signal global_reset_i : std_logic; begin @@ -170,7 +170,7 @@ begin EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => med2int(0).clk_full, NET_CLK_HALF_IN => med2int(0).clk_half, - GLOBAL_RESET_IN => master_reset_i, -- BUG + GLOBAL_RESET_IN => global_reset_i, -- BUG RESET_FROM_NET_IN => med2int(0).stat_op(13), SEND_RESET_IN => med2int(0).stat_op(15), BUS_RX => bustc_rx, @@ -245,8 +245,10 @@ end generate; WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, -- downlink uses uplink clock MASTER_CLK_OUT => master_clk_i, - GLOBAL_RESET_IN => '0', - GLOBAL_RESET_OUT => master_reset_i, + QUAD_RST_IN => '0', + GLOBAL_RESET_OUT => global_reset_i, + SLAVE_ACTIVE_OUT => open, -- BUG + SLAVE_ACTIVE_IN => '0', -- BUG TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, -- 2.43.0