From 08472d6bf906ec790270d04e83fc6b2f876e10c6 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 21 May 2014 11:40:04 +0200 Subject: [PATCH] added included features bitmap to hadesstart design --- hadesstart/config.vhd | 66 +++++++++++++++------------ hadesstart/trb3_periph_hadesstart.vhd | 1 + 2 files changed, 39 insertions(+), 28 deletions(-) diff --git a/hadesstart/config.vhd b/hadesstart/config.vhd index b3b808b..475070f 100644 --- a/hadesstart/config.vhd +++ b/hadesstart/config.vhd @@ -11,32 +11,26 @@ package config is ------------------------------------------------------------------------------ --TDC settings - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 2; - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons - constant USE_DOUBLE_EDGE : integer := c_YES; ---Define ringbuffer size for TDC channels: 32-64-128 - constant RING_BUFFER_SIZE : integer range 32 to 128 := 64; + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant USE_DOUBLE_EDGE : integer := c_YES; + constant RING_BUFFER_SIZE : integer range 32 to 128 := 64; --ring buffer size: 32,64,128 --use only every fourth input as in HPTDC high precision mode - constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES; + constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES; --Include SPI on AddOn connector - constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; --Add logic to generate configurable trigger signal from input signals. - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs + constant PHYSICAL_INPUTS : integer := 16; --number of inputs connected ---Do histos of all inputs - constant INCLUDE_STATISTICS : integer := c_YES; - ---number of real inputs to the FPGA - constant PHYSICAL_INPUTS : integer := 16; - ---Run wih 125 MHz instead of 100 MHz - constant USE_125_MHZ : integer := c_NO; --not implemented yet! - ---Use sync mode, RX clock for all parts of the FPGA - constant USE_RXCLOCK : integer := c_NO; --not implemented yet! +--Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet! --Address settings constant INIT_ADDRESS : std_logic_vector := x"F305"; @@ -47,17 +41,13 @@ package config is ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ type intlist_t is array(0 to 7) of integer; type hw_info_t is array(0 to 7) of unsigned(31 downto 0); - constant HW_INFO_BASE : unsigned(31 downto 0) := x"91000000"; - constant HW_INFO_SPI : hw_info_t := (x"00000000", x"00000400", others => x"00000000"); - constant HW_INFO_DOUBLE_EDGE : hw_info_t := (x"00000000", x"00000800", others => x"00000000"); - constant HW_INFO_NUM_CHANS : hw_info_t := (x"00000000", x"00000010", x"00000020", x"00000030", - x"00000040", x"00000050", x"00000060", x"00000070", - others => x"00000000"); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91001000"; constant CLOCK_FREQUENCY_ARR : intlist_t := (100, 125, others => 0); constant MEDIA_FREQUENCY_ARR : intlist_t := (200, 125, others => 0); @@ -65,16 +55,36 @@ package config is constant HARDWARE_INFO : std_logic_vector(31 downto 0); constant CLOCK_FREQUENCY : integer; constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + +function generateIncludedFeatures return std_logic_vector; + + end; package body config is --compute correct configuration mode - constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( - HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) + - HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2)); +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2 + t(7 downto 0) := std_logic_vector(to_unsigned(USE_HPTDC_FASTMODE_PINOUT*3,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(USE_DOUBLE_EDGE*2,4)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1)); + return t; +end function; + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + constant INCLUDED_FEATURES : std_logic_vector := generateIncludedFeatures; end package body; diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd index d5f18be..b64c8e2 100644 --- a/hadesstart/trb3_periph_hadesstart.vhd +++ b/hadesstart/trb3_periph_hadesstart.vhd @@ -389,6 +389,7 @@ begin BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, REGIO_INIT_ADDRESS => INIT_ADDRESS, REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- 2.43.0