From 085c7b40f72e30ebb42b7b8ddc7b9acbd99d3f03 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 18 Jan 2011 09:40:15 +0000 Subject: [PATCH] *** empty log message *** --- compile_frankfurt.pl | 155 ++++++ constraints_pexor.lpf | 35 ++ design/cores/cpld_fifo.ipx | 9 + design/cores/cpld_fifo.jhd | 9 + design/cores/cpld_fifo.lpc | 48 ++ design/cores/cpld_fifo.naf | 144 ++++++ design/cores/cpld_fifo.srp | 28 ++ design/cores/cpld_fifo.sym | Bin 0 -> 524 bytes design/cores/cpld_fifo.vhd | 226 +++++++++ design/cores/cpld_fifo_tmpl.vhd | 19 + design/cores/tb_cpld_fifo_tmpl.vhd | 106 +++++ design/dma_core.vhd | 739 +++++++++++++++++++++++++++++ design/pci_core.vhd | 561 ++++++++++++++++++++++ design/wb_tlc.vhd | 317 +++++++++++++ pcie_components.vhd | 602 +++++++++++++++++++++++ pexor.p2t | 21 + pexor.prj | 159 +++++++ size.txt | 21 + 18 files changed, 3199 insertions(+) create mode 100755 compile_frankfurt.pl create mode 100644 constraints_pexor.lpf create mode 100644 design/cores/cpld_fifo.ipx create mode 100644 design/cores/cpld_fifo.jhd create mode 100644 design/cores/cpld_fifo.lpc create mode 100644 design/cores/cpld_fifo.naf create mode 100644 design/cores/cpld_fifo.srp create mode 100644 design/cores/cpld_fifo.sym create mode 100644 design/cores/cpld_fifo.vhd create mode 100644 design/cores/cpld_fifo_tmpl.vhd create mode 100644 design/cores/tb_cpld_fifo_tmpl.vhd create mode 100644 design/dma_core.vhd create mode 100644 design/pci_core.vhd create mode 100644 design/wb_tlc.vhd create mode 100644 pcie_components.vhd create mode 100644 pexor.p2t create mode 100644 pexor.prj create mode 100644 size.txt diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl new file mode 100755 index 0000000..9e2acd0 --- /dev/null +++ b/compile_frankfurt.pl @@ -0,0 +1,155 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +# +# Command line for synplify_pro +# + + +use Data::Dumper; + +use warnings; +use strict; + +#my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/'; +my $lattice_path = '/d/sugar/lattice/diamond/1.1'; +#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux'; +my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; + + +my $TOPNAME="pexor"; + +my $FAMILYNAME="LatticeSCM"; +my $DEVICENAME="LFSCM3GA40EP1"; +my $PACKAGE="FFBGA1020"; +my $SPEEDGRADE="7"; + + +#create full lpf file +system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +#my $c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj"; +#my $c="$synplify_path/bin/synplify_pro -Pro -prj $TOPNAME".".prj"; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +#my $c="$synplify_path/bin/synpwrap -prj $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +#if ($r) { +#$c="cat $TOPNAME.srr"; +#system($c); +#exit 129; +#} + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "bdabdhsadbhjasdhasldhbas"; + exit 129; + } +} +#if (0){ + +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + + +system("rm $TOPNAME.ncd"); + +#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/constraints_pexor.lpf b/constraints_pexor.lpf new file mode 100644 index 0000000..cf0ef87 --- /dev/null +++ b/constraints_pexor.lpf @@ -0,0 +1,35 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +######################################### +# Clock Constraints +######################################### + FREQUENCY PORT CLK_100 100.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY PORT CLK_125 125.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY PORT CLK_FPGA 100.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY PORT PE_RFCK 100.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET THE_PCI_CORE/CLK_125_OUT_inferred_clock 125.0 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_250_inferred_clock 250.0 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET THE_MEDIA_INTERFACE_0/sfp_ref_clk 100 MHz; + FREQUENCY NET THE_MEDIA_INTERFACE_0/rx_halfclk_c 100 MHz; + FREQUENCY NET clk_125_i_c 125 MHz ; + FREQUENCY NET THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/ref_pclk 250 MHz; + +######################################### +# Serdes +######################################### +LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_100_THE_SERDES/PCSA_INST" SITE "PCS36000"; + +LOCATE COMP "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/u1_pci_exp_pcs/pcsa_inst" SITE "PCS3E100" ; +LOCATE COMP "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/u1_flxmc_pcie_core/u1_phy_dll/u1_flxmc_top_ebr/flxmc_top_mib" SITE "RUMACO1" ; +LOCATE COMP "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/u1_flxmc_pcie_core/u1_phy_dll/LTSSM" SITE "RUMACO0" ; + +MULTICYCLE "M1" START CLKNET "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_250_inferred_clock" END CLKNET "clk_125_i_c" 8.000000 ns ; +MULTICYCLE "M2" START CLKNET "clk_125_i_c" END CLKNET "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_250_inferred_clock" 8.000000 ns ; + +MULTICYCLE "M1" START CLKNET "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_250_inferred_clock" END CLKNET "THE_PCI_CORE/CLK_125_OUT_inferred_clock" 8.000000 ns ; +MULTICYCLE "M2" START CLKNET "THE_PCI_CORE/CLK_125_OUT_inferred_clock" END CLKNET "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_250_inferred_clock" 8.000000 ns ; + + diff --git a/design/cores/cpld_fifo.ipx b/design/cores/cpld_fifo.ipx new file mode 100644 index 0000000..1815f29 --- /dev/null +++ b/design/cores/cpld_fifo.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/design/cores/cpld_fifo.jhd b/design/cores/cpld_fifo.jhd new file mode 100644 index 0000000..2b008d4 --- /dev/null +++ b/design/cores/cpld_fifo.jhd @@ -0,0 +1,9 @@ +MODULE cpld_fifo DEFIN cpld_fifo.vhd + SUBMODULE FIFO16KA + INSTANCE cpld_fifo_1_0 + SUBMODULE VLO + INSTANCE scuba_vlo_inst + SUBMODULE VHI + INSTANCE scuba_vhi_inst + SUBMODULE FIFO16KA + INSTANCE cpld_fifo_0_1 diff --git a/design/cores/cpld_fifo.lpc b/design/cores/cpld_fifo.lpc new file mode 100644 index 0000000..ff7ba3a --- /dev/null +++ b/design/cores/cpld_fifo.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FFA1020C +SpeedGrade=7 +Package=FFABGA1020 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=cpld_fifo +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/18/2011 +Time=10:35:07 + +[Parameters] +Verilog=1 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=512 +RWidth=67 +WDepth=512 +WWidth=67 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=1 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=2 +PfDeassert=506 +Reset=Async +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/design/cores/cpld_fifo.naf b/design/cores/cpld_fifo.naf new file mode 100644 index 0000000..4ae6757 --- /dev/null +++ b/design/cores/cpld_fifo.naf @@ -0,0 +1,144 @@ +Data[66] i +Data[65] i +Data[64] i +Data[63] i +Data[62] i +Data[61] i +Data[60] i +Data[59] i +Data[58] i +Data[57] i +Data[56] i +Data[55] i +Data[54] i +Data[53] i +Data[52] i +Data[51] i +Data[50] i +Data[49] i +Data[48] i +Data[47] i +Data[46] i +Data[45] i +Data[44] i +Data[43] i +Data[42] i +Data[41] i +Data[40] i +Data[39] i +Data[38] i +Data[37] i +Data[36] i +Data[35] i +Data[34] i +Data[33] i +Data[32] i +Data[31] i +Data[30] i +Data[29] i +Data[28] i +Data[27] i +Data[26] i +Data[25] i +Data[24] i +Data[23] i +Data[22] i +Data[21] i +Data[20] i +Data[19] i +Data[18] i +Data[17] i +Data[16] i +Data[15] i +Data[14] i +Data[13] i +Data[12] i +Data[11] i +Data[10] i +Data[9] i +Data[8] i +Data[7] i +Data[6] i +Data[5] i +Data[4] i +Data[3] i +Data[2] i +Data[1] i +Data[0] i +WrClock i +RdClock i +WrEn i +RdEn i +Reset i +RPReset i +Q[66] o +Q[65] o +Q[64] o +Q[63] o +Q[62] o +Q[61] o +Q[60] o +Q[59] o +Q[58] o +Q[57] o +Q[56] o +Q[55] o +Q[54] o +Q[53] o +Q[52] o +Q[51] o +Q[50] o +Q[49] o +Q[48] o +Q[47] o +Q[46] o +Q[45] o +Q[44] o +Q[43] o +Q[42] o +Q[41] o +Q[40] o +Q[39] o +Q[38] o +Q[37] o +Q[36] o +Q[35] o +Q[34] o +Q[33] o +Q[32] o +Q[31] o +Q[30] o +Q[29] o +Q[28] o +Q[27] o +Q[26] o +Q[25] o +Q[24] o +Q[23] o +Q[22] o +Q[21] o +Q[20] o +Q[19] o +Q[18] o +Q[17] o +Q[16] o +Q[15] o +Q[14] o +Q[13] o +Q[12] o +Q[11] o +Q[10] o +Q[9] o +Q[8] o +Q[7] o +Q[6] o +Q[5] o +Q[4] o +Q[3] o +Q[2] o +Q[1] o +Q[0] o +Empty o +Full o +AlmostEmpty o +AlmostFull o diff --git a/design/cores/cpld_fifo.srp b/design/cores/cpld_fifo.srp new file mode 100644 index 0000000..90eaaed --- /dev/null +++ b/design/cores/cpld_fifo.srp @@ -0,0 +1,28 @@ +SCUBA, Version Diamond_1.1_Production (517) +Tue Jan 18 10:35:07 2011 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n cpld_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 67 -rwidth 67 -no_enable -pe 1 -pf 2 -e + Circuit name : cpld_fifo + Module type : ebfifo + Module Version : 5.4 + Ports : + Inputs : Data[66:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[66:0], Empty, Full, AlmostEmpty, AlmostFull + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : cpld_fifo.vhd + VHDL template : cpld_fifo_tmpl.vhd + VHDL testbench : tb_cpld_fifo_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : cpld_fifo.srp + Element Usage : + FIFO16KA : 2 + Estimated Resource Usage: + EBR : 2 diff --git a/design/cores/cpld_fifo.sym b/design/cores/cpld_fifo.sym new file mode 100644 index 0000000000000000000000000000000000000000..d5187d3964d5f37c90e904d2adf6e5302ed23823 GIT binary patch literal 524 zcmY+Aze~eV6ot?24@;{<2M5O@oy4Jobm$-vn+`74pcE7_rD;)2+t5Z(aB^~z3=WPC zjzuzd6!8xTj^fb4!7)Qe2Txwwp@GNy`0jc4-Mmo){E}QNiByD`h$aP?;s{_!g+{{$ zid90c+H{*I<#MHT3e+h)RO3pk<}ifaBPv3`_3;*K{Fzu}d56VcW$6U0&|y zr|YqOp>^;yvyDOAb4=^wb=I>nhIcttY%w| zZJl*4I(?jThLY&KGejP`+=}3hE}HFLaiIR>QL#_<@vPV*dl*TUd6R5nOdq{kf$KwY nhywctiUV?hZ^b^@$FE|K>|v_dAv-`K%RU-e "011111111000001", FULLPOINTER=> "011111111100001", + AFPOINTER1=> "000000000000001", AFPOINTER=> "000000000100001", + AEPOINTER1=> "000000001011111", AEPOINTER=> "000000000111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, + EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, + WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), + DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), + DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, + AFF=>AlmostFull, FF=>Full_int); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + cpld_fifo_1_0: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", + AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", + AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, + CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, + CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(54), + DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), + DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), + DO11=>Q(65), DO12=>Q(66), DO13=>open, DO14=>open, DO15=>open, + DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37), + DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), + DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), + DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), + DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53), EF=>open, + AEF=>open, AFF=>open, FF=>open); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of cpld_fifo is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/design/cores/cpld_fifo_tmpl.vhd b/design/cores/cpld_fifo_tmpl.vhd new file mode 100644 index 0000000..8f4534c --- /dev/null +++ b/design/cores/cpld_fifo_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +-- Tue Jan 18 10:35:07 2011 + +-- parameterized module component declaration +component cpld_fifo + port (Data: in std_logic_vector(66 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(66 downto 0); + Empty: out std_logic; Full: out std_logic; + AlmostEmpty: out std_logic; AlmostFull: out std_logic); +end component; + +-- parameterized module component instance +__ : cpld_fifo + port map (Data(66 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(66 downto 0)=>__, Empty=>__, + Full=>__, AlmostEmpty=>__, AlmostFull=>__); diff --git a/design/cores/tb_cpld_fifo_tmpl.vhd b/design/cores/tb_cpld_fifo_tmpl.vhd new file mode 100644 index 0000000..be8a3ee --- /dev/null +++ b/design/cores/tb_cpld_fifo_tmpl.vhd @@ -0,0 +1,106 @@ +-- VHDL testbench template generated by SCUBA Diamond_1.1_Production (517) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component cpld_fifo + port (Data : in std_logic_vector(66 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(66 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostEmpty: out std_logic; + AlmostFull: out std_logic + ); + end component; + + signal Data : std_logic_vector(66 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(66 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostEmpty: std_logic; + signal AlmostFull: std_logic; +begin + u1 : cpld_fifo + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty, + AlmostFull => AlmostFull + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 515 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 515 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 515 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/design/dma_core.vhd b/design/dma_core.vhd new file mode 100644 index 0000000..52e3d51 --- /dev/null +++ b/design/dma_core.vhd @@ -0,0 +1,739 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.version.all; + +entity dma_core is + port( + RSTN : in std_logic; + CLK : in std_logic; + + DMA_ADDR : out std_logic_vector(31 downto 0); + DMA_WDAT : out std_logic_vector(63 downto 0); + DMA_RDAT : in std_logic_vector(63 downto 0); + DMA_SEL : out std_logic_vector(7 downto 0); + DMA_WE : out std_logic; + DMA_CYC : out std_logic; + DMA_STB : out std_logic; + DMA_LOCK : out std_logic; + DMA_CTI : out std_logic_vector(2 downto 0); + DMA_ACK : in std_logic; + DMA_ERR : in std_logic; + DMA_RETRY : in std_logic; + DMA_EOD : in std_logic; + + S_ADDR : in std_logic_vector(31 downto 0); + S_WDAT : in std_logic_vector(31 downto 0); + S_RDAT : out std_logic_vector(31 downto 0); + S_CYC : in std_logic; + S_STB : in std_logic; + S_SEL : in std_logic_vector(3 downto 0); + S_WE : in std_logic; + S_ACK : out std_logic; + S_ERR : out std_logic; + + MAX_BURST_SIZE : out std_logic_vector(15 downto 0) + + ); +end entity; + +architecture dma_core_arch of dma_core is + + signal dma_addr : std_logic_vector(31 downto 0); --memory start address for DMA + signal dma_start : std_logic; --dma start pulse + signal dma_size : std_logic_vector(7 downto 0); --number of 64bit words to transfer (max. 32) + +begin + +PROC_SEND : process(CLK) + begin + if rising_edge(CLK) then + if RSTN = '0' then + write_state <= IDLE; + curr_dest <= (others => '0'); + fifo_read_en <= '0'; + else + fifo_read_en <= '0'; + DMA_CYC <= '0'; + DMA_STB <= '0'; + DMA_WE <= '0'; + DMA_CTI <= "000"; + + case write_state is + when IDLE => + if dma_start = '1' then + write_state <= PREPARE_DATA; + write_size <= dma_size; + write_addr <= dma_addr; + end if; + when PREPARE_DATA => + + end case; + end if; + end if; + end process; + + +end architecture; + +module simple_dma_core ( + ,clk, + ,rstn + ,a_addr,a_wdat,a_rdat,a_sel,a_we,a_cyc,a_stb,a_lock,a_cti,a_ack,a_err,a_retry,a_eod + ,b_addr,b_wdat,b_rdat,b_sel,b_we,b_cyc,b_stb,b_lock,b_cti,b_ack,b_err,b_retry,b_eod + ,b_active + ,s_addr,s_wdat,s_rdat,s_cyc,s_stb,s_sel,s_we,s_ack,s_err,a_active + ,max_burst_size, +///// output from rx + ,wb_rx_clk_i + ,rp_stat_0,rp_stat_1,rp_stat_2,rp_stat_3 + ,rp_addr_0,rp_addr_1,rp_addr_2,rp_addr_3 + ,rp_data_0, rp_data_1, rp_data_2, rp_data_3 + ,ddma_en, + ,int, + ,debug +); + +input clk; +input rstn; +output[31:0] a_addr; +output[63:0] a_wdat; +input[63:0] a_rdat; +output[7:0] a_sel; +output a_we; +output a_cyc; +output a_stb; +output a_lock; +output[2:0] a_cti; +input a_ack; +input a_err; +input a_retry; +input a_eod; + +output[31:0] b_addr; +output[63:0] b_wdat; +input[63:0] b_rdat; +output[7:0] b_sel; +output b_we; +output b_cyc; +output b_stb; +output b_lock; +output[2:0] b_cti; +input b_ack; +input b_err; +input b_retry; +input b_eod; + +input[31:0]s_addr; +input[31:0]s_wdat; +output[31:0]s_rdat; +input s_cyc; +input s_stb; +input[3:0] s_sel; +input s_we; +output s_ack; +output s_err; +output a_active; +output b_active; +output[15:0]max_burst_size; +output ddma_en; + + + +input[3:0] wb_rx_clk_i; +input [31:0] rp_stat_0,rp_stat_1,rp_stat_2,rp_stat_3; +input [31:0] rp_addr_0,rp_addr_1,rp_addr_2,rp_addr_3; +input [31:0] rp_data_0, rp_data_1, rp_data_2, rp_data_3; + + + +output int; +output[31:0] debug; +//---------------------------------------------------------- + + +reg a_cyc,b_cyc0,b_cyc; +reg a_stb,b_stb0,b_stb; +reg[2:0] a_cti,b_cti0,b_cti; +//reg a_sel,b_sel; +reg[31:0] a_addr,b_addr0; + +reg [31:0]b_addr; +reg[63:0] b_wdat0; +reg [63:0]b_wdat; +reg b_we0,a_we,b_we; + +wire[31:0] b_addr1[0:3]; +wire[63:0]b_wdat1[0:3]; +wire b_cyc1[0:3]; +wire b_stb1[0:3]; +wire b_we1[0:3]; +wire[2:0] b_cti1[0:3]; + +reg[31:0] wb_dat_local; +reg int; + +reg[31:0] dma_source; +reg[31:0] dma_dest; +reg[31:0] dma_size; +reg[31:0] dma_burst; +reg[31:0] dma_ctrl; +reg[7:0] dma_astat; +reg[31:0] int_ctrl; +reg[31:0] int_status; + +wire s_rd,s_wr; + +reg [31:0] curr_source,curr_dest; +reg [15:0] curr_size,curr_burst,curr_burst2,curr_size2; + + +reg [3:0] sma,sman; +wire [31:0] rdat; +reg s_stb_i; + +reg wr_ena; +reg rd_ena; + +reg[15:0] xfersize,xferburst; +wire[63:0] temp_out; +reg [63:0] temp_out2; +reg[63:0] temp_read2; +wire full,empty; +reg[3:0] smb,smbn; + +reg[2:0] dma_pulse; + +reg rd_ena_p; + +reg[63:0] fifo_wdat; +wire[63:0] fifo_rdat; +reg[63:0] fifo_rdat2; +reg[7:0] exitcounter; +wire[3:0] ddma_ena; +wire[3:0] sfp_busy; + +wire[3:0] wr_lenreg; +wire[16:0]ddma_len[0:3]; +wire[3:0]ddma_busy; +wire[3:0]ddma_end; +reg ddma_act; + +wire[31:0]ddma_deb[0:3]; + +assign max_burst_size = |ddma_ena ? 16'h80 : dma_burst[15:0]; + +assign ddma_en = |ddma_ena; + +assign s_rd = s_stb && ~s_we; +assign s_wr = s_stb && s_we; +assign s_rdat = wb_dat_local; +assign s_ack = s_stb_i && s_cyc; + + +assign ddma_ena = dma_ctrl[4:1]; + + + + + +always @ (posedge clk or negedge rstn) +begin + if(~rstn) + begin + dma_source <= 32'd0; + dma_dest <= 32'd0; + dma_size <= 32'd0; + dma_ctrl <= 32'd0; + dma_burst <= 32'd0; + int_ctrl <= 32'd0; + int_status <= 32'd0; + + end + else + begin + + s_stb_i <= s_stb; + int_status <= int_ctrl; + if(s_stb) + begin + case (s_addr[4:2]) + + 3'b000: // 0x0 = source register + begin + if (s_rd) + begin + wb_dat_local <= dma_source; + end + else if (s_wr) + begin + dma_source <= s_wdat; + end + end + 3'b001: // 0x4 = dest + begin + if (s_rd) + wb_dat_local <= dma_dest; + else if (s_wr) + begin + dma_dest <= s_wdat; + end + end + 3'b010: // 0x8 = len + begin + if (s_rd) + wb_dat_local <= dma_size; + else if (s_wr) + begin + dma_size <= s_wdat; + end + end + 3'b011: // 0xc = burstsize ( bits 15:0) + begin + if (s_rd) + wb_dat_local <= dma_burst; + else if (s_wr) + begin + dma_burst <= s_wdat; + end + end + 3'b100: // 0x10 = dma control + begin + if (s_rd) + wb_dat_local <= dma_ctrl; + else if (s_wr) + begin + dma_ctrl <= s_wdat; + end + end + 3'b101: // 0x14 = interrupt control + begin + if (s_rd) + wb_dat_local <= int_ctrl; + else if (s_wr) + begin + int_ctrl <= s_wdat; + end + end + 3'b110: // 0x18 = interrupt status + begin + if (s_rd) + begin + wb_dat_local <= int_status; + end + end + default: + wb_dat_local <= 32'd0; + endcase + end + else if(dma_astat[0]) + dma_ctrl[0] <= 1'b0; + else if(ddma_act) + begin + dma_ctrl[0] <= |ddma_busy; + if(wr_lenreg[0]) dma_size <= ddma_len[0]; + else if(wr_lenreg[1]) dma_size <= ddma_len[1]; + else if(wr_lenreg[2]) dma_size <= ddma_len[2]; + else if(wr_lenreg[3]) dma_size <= ddma_len[3]; + end + end +end + +always @ (posedge clk) +begin + ddma_act <= |ddma_ena; +end + + + +always @(posedge clk) +begin + dma_pulse[0] <= dma_ctrl[0]; + dma_pulse[1] <= dma_pulse[0]; + dma_pulse[2] <= dma_pulse[0] && ~dma_pulse[1]; +end + + +always @(posedge clk) +begin + int <= |int_ctrl; + +end + + +assign b_sel = 8'b1111111; +assign a_sel = 8'b1111111; + + +always @(*) +begin + if(b_cyc1[0]) + begin + b_addr <= b_addr1[0]; + b_we <= b_we1[0]; + b_cti <= b_cti1[0]; + b_stb <= b_stb1[0]; + b_cyc <= b_cyc1[0]; + b_wdat <= b_wdat1[0]; + end + else if(b_cyc1[1]) + begin + b_addr <= b_addr1[1]; + b_we <= b_we1[1]; + b_cti <= b_cti1[1]; + b_stb <= b_stb1[1]; + b_cyc <= b_cyc1[1]; + b_wdat <= b_wdat1[1]; + end + else if(b_cyc1[2]) + begin + b_addr <= b_addr1[2]; + b_we <= b_we1[2]; + b_cti <= b_cti1[2]; + b_stb <= b_stb1[2]; + b_cyc <= b_cyc1[2]; + b_wdat <= b_wdat1[2]; + end + else if(b_cyc1[3]) + begin + b_addr <= b_addr1[3]; + b_we <= b_we1[3]; + b_cti <= b_cti1[3]; + b_stb <= b_stb1[3]; + b_cyc <= b_cyc1[3]; + b_wdat <= b_wdat1[3]; + end + else + begin + b_addr <= b_addr0; + b_we <= b_we0; + b_cti <= b_cti0; + b_stb <= b_stb0; + b_cyc <= b_cyc0; + b_wdat <= b_wdat0; + end +end + +assign debug = ddma_deb[0]; + +/*assign debug[0] = b_cyc; +assign debug[1] = b_stb; +assign debug[2] = b_we; +assign debug[3] = b_ack; +*/ + + +//control Wishbone read from DPRAM +always @ ( posedge clk or negedge rstn) +begin + if(~rstn) + begin + sma <= 4'h0; + end + else + begin + case (sma) + 4'h0: + begin + a_cyc <= 1'b0; a_stb <= 1'b0; + dma_astat[0] <= 1'b0; + wr_ena <= 1'b0; + curr_source <= dma_source; + curr_burst <= {3'b000,dma_burst[31:3]}; + curr_size <= {3'b000,dma_size[31:3]}; + if(dma_pulse[2] && ~(|ddma_ena)) + sma <= 4'h1; + else + sma <= 4'h0; + end + 4'h1: + begin + a_addr <= curr_source; + a_cyc <= 1'b1; a_cti <= 3'b010; + if(~full) + begin + a_stb <= 1'b1; + if(a_ack) + begin + fifo_wdat <= a_rdat; + wr_ena <= 1'b1; + curr_burst <= curr_burst - 1; + end + else + begin + wr_ena <= 1'b0; + end + + end + else + begin + a_stb <= 1'b0; + end + if(curr_burst == 31'd1) + begin + + a_stb <= 1'b0; + a_cyc <= 1'b0; + sma <= 4'h2; + end + end + 4'h2: + begin + wr_ena <= 1'b0; + curr_burst <= {3'b000,dma_burst[31:3]}; + sma <= 4'h3; + end + 4'h3: + begin + curr_size <= curr_size - curr_burst; + sma <= 4'h4; + end + 4'h4: + begin + if(curr_size > 16'd0) + begin + curr_source <= curr_source + dma_burst; + exitcounter <= 8'd10; // 20 + sma <= 4'h7; + end + else + begin + sma <= 4'h5; + exitcounter <= 8'd100; + end + end + 4'h5: + begin + exitcounter <= exitcounter - 1; + if(exitcounter == 8'd10) + begin + dma_astat[0] <= 1'b1; + end + if(exitcounter == 8'd0) + begin + sma <= 4'b0; + end + end + + 4'h7: + begin + exitcounter <= exitcounter - 1; + if(exitcounter == 8'd0) + begin + sma <= 4'h1; + end + end + + + + + + endcase + end +end +/* Verilog module instantiation template generated by SCUBA ispLever_v72_PROD_Build (44) */ +/* Module Version: 5.0 */ +/* Tue Jan 20 14:52:35 2009 */ + +/* parameterized module instance */ +simpledma_fifo simplefifo (.Data(fifo_wdat ), .WrClock(clk ), .RdClock(clk ), .WrEn(wr_ena ), + .RdEn(rd_ena ), .Reset(~rstn ), .RPReset(1'b0 ), .Q(fifo_rdat ), .Empty(empty ), .Full( ), + .AlmostEmpty( ), .AlmostFull(full )); + +/* Verilog module instantiation template generated by SCUBA ispLever_v72_PROD_Build (44) */ +/* Module Version: 5.0 */ +/* Wed Jan 28 10:44:53 2009 */ + + +//Read fifo and write to DMA adaptor +always @ (posedge clk or negedge rstn) +begin + if(~rstn) + begin + smb <= 4'h0; + curr_dest <= 32'd0; + rd_ena <= 1'b0; + end + else + // rd_ena_p <= rd_ena; + + + case(smb) + 4'h0: + begin + curr_dest <= dma_dest; rd_ena <= 1'b0; + b_cyc0 <= 1'b0; b_stb0 <= 1'b0; b_we0 <= 1'b0; b_cti0 <= 3'b000; + curr_burst2 <= dma_burst[31:0]; + curr_size2 <= dma_size[31:0]; + + if(dma_pulse[2] && ~(|ddma_ena)) + begin + smb <= 4'h1; + end + end + 4'h1: + begin + b_addr0 <= curr_dest; + b_cti0 <= 3'b010; b_we0 <= 1'b1; + if(~empty ) + begin + b_cyc0 <= 1'b1; + rd_ena <= 1'b1; + smb <= 4'h2; + end + end + 4'h2: + begin + smb <= 4'h3; + end + 4'h3: + begin + smb <= 4'h4; + end + 4'h4: // fifo data out start here + begin + b_stb0 <= 1'b1; + b_wdat0 <= fifo_rdat; + curr_burst2 <= curr_burst2 - 8; + smb <= 4'h5; + end + 4'h5: + begin // b_ack received + b_wdat0 <= fifo_rdat2; + curr_burst2 <= curr_burst2 - 8; + smb <= 4'h6; + end + 4'h6: + begin // b_ack received + b_wdat0 <= fifo_rdat2; + curr_burst2 <= curr_burst2 - 8; + if(curr_burst2 == 31'd0) + begin + rd_ena <= 1'b0; + smb <= 4'h7; + end + + end + 4'h7: + begin + b_stb0 <= 1'b0; b_cyc0 <= 1'b0; b_we0 <= 1'b0; + curr_size2 <= curr_size2 - dma_burst; + curr_burst2 <= dma_burst; + smb <= 4'h8; + end + 4'h8: + begin + if(curr_size2 > 16'd0) + begin + curr_dest <= curr_dest + dma_burst; + smb <= 4'h1; + end + else + begin + smb <= 4'h9; + end + end + 4'h9: + begin + smb <= 1'h0; + end + + + endcase +end + +always @ (posedge clk) +begin + fifo_rdat2 <= fifo_rdat; +end + + + +//Read data from SFP -> remove +direct_dma f_ddma0(.clk(clk),.rstn(rstn), + .ddma_ena(ddma_ena[0]), + .ddma_dest(dma_dest), + .wb_rx_clk_i(wb_rx_clk_i[0]), + .rp_stat(rp_stat_0), + .rp_data(rp_data_0), + .b_addr(b_addr1[0]), + .b_wdat(b_wdat1[0]), + .b_sel(), + .b_we(b_we1[0]), + .b_cyc(b_cyc1[0]), + .b_stb(b_stb1[0]), + .b_cti(b_cti1[0]), + .b_ack(b_ack), + .wr_lenreg(wr_lenreg[0]), + .ddma_len(ddma_len[0]), + .ddma_busy(ddma_busy[0]), + .ddma_end(ddma_end[0]), + .debug(ddma_deb[0])); + +direct_dma f_ddma1(.clk(clk),.rstn(rstn), + .ddma_ena(ddma_ena[1]), + .ddma_dest(dma_dest), + .wb_rx_clk_i(wb_rx_clk_i[1]), + .rp_stat(rp_stat_1), + .rp_data(rp_data_1), + .b_addr(b_addr1[1]), + .b_wdat(b_wdat1[1]), + .b_sel(), + .b_we(b_we1[1]), + .b_cyc(b_cyc1[1]), + .b_stb(b_stb1[1]), + .b_cti(b_cti1[1]), + .b_ack(b_ack), + .wr_lenreg(wr_lenreg[1]), + .ddma_len(ddma_len[1]), + .ddma_busy(ddma_busy[1]), + .ddma_end(ddma_end[1]), + .debug(ddma_deb[1])); + +direct_dma f_ddma2(.clk(clk),.rstn(rstn), + .ddma_ena(ddma_ena[2]), + .ddma_dest(dma_dest), + .wb_rx_clk_i(wb_rx_clk_i[2]), + .rp_stat(rp_stat_2), + .rp_data(rp_data_2), + .b_addr(b_addr1[2]), + .b_wdat(b_wdat1[2]), + .b_sel(), + .b_we(b_we1[2]), + .b_cyc(b_cyc1[2]), + .b_stb(b_stb1[2]), + .b_cti(b_cti1[2]), + .b_ack(b_ack), + .wr_lenreg(wr_lenreg[2]), + .ddma_len(ddma_len[2]), + .ddma_busy(ddma_busy[2]), + .ddma_end(ddma_end[2]), + .debug(ddma_deb[2])); + +direct_dma f_ddma3(.clk(clk),.rstn(rstn), + .ddma_ena(ddma_ena[3]), + .ddma_dest(dma_dest), + .wb_rx_clk_i(wb_rx_clk_i[3]), + .rp_stat(rp_stat_3), + .rp_data(rp_data_3), + .b_addr(b_addr1[3]), + .b_wdat(b_wdat1[3]), + .b_sel(), + .b_we(b_we1[3]), + .b_cyc(b_cyc1[3]), + .b_stb(b_stb1[3]), + .b_cti(b_cti1[3]), + .b_ack(b_ack), + .wr_lenreg(wr_lenreg[3]), + .ddma_len(ddma_len[3]), + .ddma_busy(ddma_busy[3]), + .ddma_end(ddma_end[3]), + .debug(ddma_deb[3])); + + + +endmodule diff --git a/design/pci_core.vhd b/design/pci_core.vhd new file mode 100644 index 0000000..7e0da07 --- /dev/null +++ b/design/pci_core.vhd @@ -0,0 +1,561 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + + +entity pci_core is + port( + CLK_PCIE_IN : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_WB_IN : in std_logic; + CLK_125_OUT : out std_logic; + RESET_IN : in std_logic; + CLEAR_IN : in std_logic; + --PCIe + PCIE_DINP : in std_logic_vector(3 downto 0); + PCIE_DINN : in std_logic_vector(3 downto 0); + PCIE_DOUTP : out std_logic_vector(3 downto 0); + PCIE_DOUTN : out std_logic_vector(3 downto 0); + + --single access + BUS_ADDR_OUT : out std_logic_vector(31 downto 0); + BUS_WDAT_OUT : out std_logic_vector(63 downto 0); + BUS_RDAT_IN : in std_logic_vector(63 downto 0); + BUS_SEL_OUT : out std_logic_vector(7 downto 0); + BUS_WE_OUT : out std_logic; + BUS_CYC_OUT : out std_logic; + BUS_STB_OUT : out std_logic; + BUS_LOCK_OUT : out std_logic; +-- BUS_CTI_OUT : out std_logic_vector(2 downto 0); + BUS_ACK_IN : in std_logic; +-- BUS_ERR_IN : in std_logic; +-- BUS_RETRY_IN : in std_logic; +-- BUS_EOD_IN : in std_logic; + + --DMA + DMA_ADDR : in std_logic_vector(31 downto 0); + DMA_WDAT : in std_logic_vector(63 downto 0); + DMA_RDAT : out std_logic_vector(63 downto 0); + DMA_SEL : in std_logic_vector(7 downto 0); + DMA_WE : in std_logic; + DMA_CYC : in std_logic; + DMA_STB : in std_logic; + DMA_LOCK : in std_logic; + DMA_CTI : in std_logic_vector(2 downto 0); + DMA_ACK : out std_logic; + DMA_ERR : out std_logic; + DMA_RETRY : out std_logic; + DMA_EOD : out std_logic; + + --Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + +end entity; + + +architecture pci_arch of pci_core is + + signal clk_50_i : std_logic; + signal clk_125_i : std_logic; + signal clk_250_i : std_logic; + signal pll_locked_i : std_logic; + signal rst_n : std_logic; + + signal tx_req_i : std_logic; + signal tx_data_i : std_logic_vector(63 downto 0); + signal tx_st_i : std_logic; + signal tx_end_i : std_logic; + signal tx_dwen_i : std_logic; + + signal cfgln_i : std_logic_vector(3 downto 0); + signal cfgln_sum_i : std_logic_vector(2 downto 0); + + signal lsm_status_i : std_logic_vector(3 downto 0); + signal tx_val_i : std_logic; + signal tx_rdy_i : std_logic; + signal tx_ca_ph_i : std_logic_vector(8 downto 0); + signal tx_ca_pd_i : std_logic_vector(12 downto 0); + signal tx_ca_nph_i : std_logic_vector(8 downto 0); + signal tx_ca_npd_i : std_logic_vector(12 downto 0); + signal tx_ca_cplh_i : std_logic_vector(8 downto 0); + signal tx_ca_cpld_i : std_logic_vector(12 downto 0); + signal tx_ca_p_recheck_i : std_logic; + signal tx_ca_cpl_recheck_i : std_logic; + signal rx_data_i : std_logic_vector(63 downto 0); + signal rx_st_i : std_logic; + signal rx_end_i : std_logic; + signal rx_dwen_i : std_logic; + signal rx_us_req_i : std_logic; + signal rx_malf_tlp_i : std_logic; + signal rx_bar_hit_i : std_logic_vector(6 downto 0); + + signal bus_num_i : std_logic_vector(7 downto 0); + signal dev_num_i : std_logic_vector(4 downto 0); + signal func_num_i : std_logic_vector(2 downto 0); + signal lnk_cntl_i : std_logic_vector(7 downto 0); + + signal dl_inactive_i : std_logic; + signal dl_init_i : std_logic; + signal dl_active_i : std_logic; + signal dl_up_i : std_logic; + + signal requestor_id_i : std_logic_vector(15 downto 0); + + signal dma_req_adp_i : std_logic_vector(1 downto 0); + signal dma_ack_i : std_logic_vector(1 downto 0); + signal burst_len_i : std_logic_vector(15 downto 0); + signal active_ch_i : std_logic_vector(1 downto 0); + signal tx_st_dma_i : std_logic; + signal tx_end_dma_i : std_logic; + signal tx_dwen_dma_i : std_logic; + signal tx_data_dma_i : std_logic_vector(63 downto 0); + signal tx_req_dma_i : std_logic; + signal tx_rdy_dma_i : std_logic; + signal debug_dma_apater_i : std_logic_vector(31 downto 0); + signal debug_wb_tlc_i : std_logic_vector(31 downto 0); + + signal tx_rdy_ur_i : std_logic; + signal tx_req_ur_i : std_logic; + signal tx_dout_ur_i : std_logic_vector(63 downto 0); + signal tx_sop_ur_i : std_logic; + signal tx_eop_ur_i : std_logic; + signal tx_dwen_ur_i : std_logic; + + signal pd_cr_ur_i : std_logic; + signal pd_num_ur_i : std_logic_vector(7 downto 0); + signal ph_cr_ur_i : std_logic; + signal npd_cr_ur_i : std_logic; + signal nph_cr_ur_i : std_logic; + + signal pd_cr_wb_i : std_logic; + signal ph_cr_wb_i : std_logic; + signal nph_cr_wb_i : std_logic; + signal npd_cr_wb_i : std_logic; + + signal pd_cr_i : std_logic; + signal pd_num_i : std_logic_vector(7 downto 0); + signal ph_cr_i : std_logic; + signal npd_cr_i : std_logic; + signal nph_cr_i : std_logic; + + signal tx_rdy_wbm_i : std_logic; + signal tx_req_wbm_i : std_logic; + signal tx_dout_wbm_i : std_logic_vector(63 downto 0); + signal tx_sop_wbm_i : std_logic; + signal tx_eop_wbm_i : std_logic; + signal tx_dwen_wbm_i : std_logic; + + signal rx_f_empty_i : std_logic; + signal rx_f_full_i : std_logic; + + signal bus_addr_i : std_logic_vector(31 downto 0); + +begin + +----------------------------------------------------------------------- +-- Clock Generation +----------------------------------------------------------------------- +THE_PLL : pll_in100_out50_250 + port map( + CLK => CLK_PCIE_IN, + CLKOP => clk_250_i, + CLKOS => clk_50_i, + LOCK => pll_locked_i + ); + +rst_n <= not RESET_IN; + +----------------------------------------------------------------------- +-- I/O +----------------------------------------------------------------------- + + CLK_125_OUT <= clk_125_i; + +----------------------------------------------------------------------- +-- PCI Core +----------------------------------------------------------------------- + + THE_PCIE : pciexp2 + port map( + --Reset/CLK + RST_N => '1', + SERDES_RST => '0', + REFCLK_250 => clk_250_i, --clk input + CLK_50 => clk_50_i, --clk input + SYS_CLK_125 => clk_125_i, --clk output + FLIP_LANES => '1', + + hdinp_0 => PCIE_DINP(0), + hdinn_0 => PCIE_DINN(0), + hdinp_1 => PCIE_DINP(1), + hdinn_1 => PCIE_DINN(1), + hdinp_2 => PCIE_DINP(2), + hdinn_2 => PCIE_DINN(2), + hdinp_3 => PCIE_DINP(3), + hdinn_3 => PCIE_DINN(3), + hdoutp_0 => PCIE_DOUTP(0), + hdoutn_0 => PCIE_DOUTN(0), + hdoutp_1 => PCIE_DOUTP(1), + hdoutn_1 => PCIE_DOUTN(1), + hdoutp_2 => PCIE_DOUTP(2), + hdoutn_2 => PCIE_DOUTN(2), + hdoutp_3 => PCIE_DOUTP(3), + hdoutn_3 => PCIE_DOUTN(3), + --IRQ + INTA_N => '1', + MSI => (others => '0'), + FORCE_LSM_ACTIVE => '0', + FORCE_REC_EI => '0', + FORCE_PHY_STATUS => '0', + FORCE_DISABLE_SCR => '0', + HL_SND_BEACON => '0', + HL_DISABLE_SCR => '0', + HL_GTO_DIS => '0', + HL_GTO_DET => '0', + HL_GTO_HRST => '0', + HL_GTO_L0STX => '0', + HL_GTO_L1 => '0', + HL_GTO_L2 => '0', + HL_GTO_L0STXFTS => '0', + HL_GTO_LBK => x"0", + HL_GTO_RCVRY => '0', + HL_GTO_CFG => '0', + NO_PCIE_TRAIN => '0', --whatever this is + --Power Management + TX_DLLP_VAL => "00", + TX_PMTYPE => "000", + TX_VSD_DATA => (others => '0'), + --For VC Inputs + TX_REQ_VC0 => tx_req_i, -- VC0 Request from User + TX_DATA_VC0 => tx_data_i, -- VC0 Input data from user logic + TX_ST_VC0 => tx_st_i, -- VC0 start of pkt from user logic. + TX_END_VC0 => tx_end_i, -- VC0 End of pkt from user logic. + TX_NLFY_VC0 => '0', -- VC0 End of nullified pkt from user logic. + TX_DWEN_VC0 => tx_dwen_i, -- VC0 Dword enable from user logic. + PH_BUF_STATUS_VC0 => '0', -- VC0 Indicate the Full/alm.Full status of the PH buffers + PD_BUF_STATUS_VC0 => '0', -- VC0 Indicate PD Buffer has got space less than Max Pkt size + NPH_BUF_STATUS_VC0 => '0', -- VC0 For NPH + NPD_BUF_STATUS_VC0 => '0', -- VC0 For NPD + PH_PROCESSED_VC0 => ph_cr_i, -- VC0 TL has processed one TLP Header - PH Type + PD_PROCESSED_VC0 => pd_cr_i, -- VC0 TL has processed one TLP Data - PD TYPE + NPH_PROCESSED_VC0 => nph_cr_i, -- VC0 For NPH + NPD_PROCESSED_VC0 => npd_cr_i, -- VC0 For NPD + PD_NUM_VC0 => x"01", -- VC0 For PD -- No. of Data processed + NPD_NUM_VC0 => x"01", -- VC0 For PD + --From User logic + CMPLN_TOUT => '0', -- Completion time out. + CMPLTR_ABORT => '0', -- Completor abort. + UNEXP_CMPLN => '0', -- Unexpexted completion. + UR_NP_EXT => '0', -- UR for NP type. + UR_P_EXT => '0', -- UR for P type. + NP_REQ_PEND => '0', -- Non posted request is pending. + PME_STATUS => '0', -- PME status to reg 044h. + RX_RST => '0', + PROG_DONE => '1', + -- System bus + SYSBUS_IN => (others => '0'), -- System bus inputs to PCS + SYSBUS_OUT => open, -- PCS outputs to System bus + -- Power Management/ Vendor specific DLLP + TX_DLLP_SENT => open, -- Requested PM DLLP is sent + RXDP_PMD_TYPE => open, -- PM DLLP type bits. + RXDP_VSD_DATA => open, -- Vendor specific DLLP data. + RXDP_DLLP_VAL => open, -- PM/Vendor specific DLLP valid. + PHY_CFGLN => cfgln_i, -- Indicates the Configured Lanes + PHY_CFGLN_SUM => cfgln_sum_i, -- Number of Configured lanes + PHY_POL_COMPLIANCE => open, -- Polling compliance + PHY_REALIGN_REQ => open, + PHY_LTSSM_STATE => open, + PHY_LTSSM_SUBSTATE => open, + PHY_L0S_TX_STATE => open, + PHY_L1_STATE => open, + PHY_L2_STATE => open, + PHY_MLOOPBACK => open, + PHY_SLOOPBACK => open, + PHY_SND_BEACON => open, + -- Extra + LSM_STATUS_0 => lsm_status_i(0), + LSM_STATUS_1 => lsm_status_i(1), + LSM_STATUS_2 => lsm_status_i(2), + LSM_STATUS_3 => lsm_status_i(3), + TX_VAL => tx_val_i, -- Valid signal toggles during x2/x1 downgrade + TX_RDY_VC0 => tx_rdy_i, -- VC0 TX ready indicating signal + TX_CA_PH_VC0 => tx_ca_ph_i, -- VC0 Available credit for Posted Type Headers + TX_CA_PD_VC0 => tx_ca_pd_i, -- VC0 For Posted - Data + TX_CA_NPH_VC0 => tx_ca_nph_i, -- VC0 For Non-posted - Header + TX_CA_NPD_VC0 => tx_ca_npd_i, -- VC0 For Non-posted - Data + TX_CA_CPLH_VC0 => tx_ca_cplh_i, -- VC0 For Completion - Header + TX_CA_CPLD_VC0 => tx_ca_cpld_i, -- VC0 For Completion - Data + TX_CA_P_RECHECK_VC0 => tx_ca_p_recheck_i, + TX_CA_CPL_RECHECK_VC0 => tx_ca_cpl_recheck_i, + RX_DATA_VC0 => rx_data_i, -- VC0 Receive data + RX_ST_VC0 => rx_st_i, -- VC0 Receive data start + RX_END_VC0 => rx_end_i, -- VC0 Receive data end + RX_DWEN_VC0 => rx_dwen_i, -- VC0 Dword enable + RX_US_REQ_VC0 => rx_us_req_i, -- VC0 unsupported req received + RX_MALF_TLP_VC0 => rx_malf_tlp_i,-- VC0 malformed TLP in received data + RX_BAR_HIT => rx_bar_hit_i, -- Bar hit + MM_ENABLE => open, -- Multiple message enable bits of Register + MSI_ENABLE => open, -- MSI enable bit of Register + -- From Config Registers + BUS_NUM => bus_num_i, -- Bus number + DEV_NUM => dev_num_i, -- Device number + FUNC_NUM => func_num_i, -- Function number + PM_POWER_STATE => open, -- Power state bits of Register at 044h + PME_EN => open, -- PME_En at 044h + CMD_REG_OUT => open, -- Bits 1086210 From register 004h + DEV_CNTL_OUT => open, -- Divice control register at 060h + LNK_CNTL_OUT => lnk_cntl_i, -- Link control register at 068h + -- Data Link Control SM Status + DL_INACTIVE => dl_inactive_i,-- Data Link Control SM is in INACTIVE state + DL_INIT => dl_init_i, -- INIT state + DL_ACTIVE => dl_active_i, -- ACTIVE state + DL_UP => dl_up_i -- Data Link Layer is UP + ); + +----------------------------------------------------------------------- +-- DMA Adapter +----------------------------------------------------------------------- + +requestor_id_i <= bus_num_i & dev_num_i & func_num_i; + +-- THE_DMA_ADAPTER : dma_adapter +-- port map( +-- RSTN => rst_n, +-- CLK_125 => clk_125_i, +-- ENABLE => '1', +-- +-- WB_CLK_I => CLK_WB_IN, +-- WB_RST_I => rst_n, +-- WB_DAT_I => DMA_WDAT, +-- WB_ADR_I => DMA_ADDR, +-- WB_CYC_I => DMA_CYC, +-- WB_LOCK_I => DMA_LOCK, +-- WB_SEL_I => DMA_SEL, +-- WB_STB_I => DMA_STB, +-- WB_WE_I => DMA_WE, +-- WB_DAT_O => DMA_RDAT, +-- WB_ACK_O => DMA_ACK, +-- WB_ERR_O => DMA_ERR, +-- WB_RTY_O => DMA_RETRY, +-- +-- DMA_REQ => dma_req_adp_i, +-- DMA_ACK => dma_ack_i, +-- BURST_LEN => burst_len_i, +-- ACTIVE_CH => active_ch_i, +-- REQUESTOR_ID => requestor_id_i, +-- +-- TX_ST => tx_st_dma_i, +-- TX_END => tx_end_dma_i, +-- TX_DWEN => tx_dwen_dma_i, +-- TX_DATA => tx_data_dma_i, +-- TX_REQ => tx_req_dma_i, +-- TX_RDY => tx_rdy_dma_i, +-- TX_VAL => tx_val_i, +-- TX_CA_PH => tx_ca_ph_i, +-- TX_CA_PD => tx_ca_pd_i, +-- TX_CA_NPH => tx_ca_nph_i, +-- +-- RX_CR_CPLH => open, +-- RX_CR_CPLD => open, +-- UNEXP_CMPL => open, +-- RX_ST => rx_st_i, +-- RX_END => rx_end_i, +-- RX_DWEN => rx_dwen_i, +-- RX_DATA => rx_data_i, +-- +-- DEBUG => debug_dma_apater_i +-- ); + +DMA_ERR <= '0'; +DMA_ACK <= '0'; +DMA_RETRY <= '0'; +DMA_RDAT <= (others => '0'); + +tx_data_dma_i <= (others => '0'); +tx_st_dma_i <= '0'; +tx_end_dma_i <= '0'; +tx_dwen_dma_i <= '0'; +tx_req_dma_i <= '0'; + + + +----------------------------------------------------------------------- +-- Credits handling +----------------------------------------------------------------------- + +THE_IP_RX_CRPR : ip_rx_crpr + port map( + CLK => clk_125_i, + RSTN => rst_n, + RX_ST => rx_st_i, + RX_END => rx_end_i, + RX_DIN => rx_data_i, + RX_DWEN => rx_dwen_i, + RX_BAR_HIT => rx_bar_hit_i, + PD_CR => pd_cr_ur_i, + PD_NUM => pd_num_ur_i, + PH_CR => ph_cr_ur_i, + NPD_CR => npd_cr_ur_i, + NPH_CR => nph_cr_ur_i + ); + + +THE_IP_CRPR_ARB : ip_crpr_arb + port map( + CLK => clk_125_i, + RSTN => rst_n, + + PD_CR_0 => pd_cr_ur_i, + PD_NUM_0 => pd_num_ur_i, + PH_CR_0 => ph_cr_ur_i, + NPD_CR_0 => npd_cr_ur_i, + NPH_CR_0 => nph_cr_ur_i, + + PD_CR_1 => pd_cr_wb_i, + PD_NUM_1 => x"01", + PH_CR_1 => ph_cr_wb_i, + NPD_CR_1 => '0', + NPH_CR_1 => nph_cr_wb_i, + + PD_CR => pd_cr_i, + PD_NUM => pd_num_i, + PH_CR => ph_cr_i, + NPD_CR => npd_cr_i, + NPH_CR => nph_cr_i + + ); + + +----------------------------------------------------------------------- +-- Unsupported Request Handler +----------------------------------------------------------------------- +THE_UR_Handler : UR_gen + port map( + RSTN => rst_n, + CLK => clk_125_i, + RX_DIN => rx_data_i, + RX_SOP => rx_st_i, + RX_EOP => rx_end_i, + RX_DWEN => rx_dwen_i, + RX_US => rx_us_req_i, + RX_BAR_HIT => rx_bar_hit_i, + TX_RDY => tx_rdy_ur_i, + TX_VAL => tx_val_i, + TX_REQ => tx_req_ur_i, + TX_DOUT => tx_dout_ur_i, + TX_SOP => tx_sop_ur_i, + TX_EOP => tx_eop_ur_i, + TX_DWEN => tx_dwen_ur_i, + COMP_ID => requestor_id_i + ); + + +----------------------------------------------------------------------- +-- TX Arbiter +----------------------------------------------------------------------- +THE_TX_ARBITER : ip_tx_arbiter + port map( + RSTN => rst_n, + CLK => clk_125_i, + TX_VAL => tx_val_i, + + TX_REQ_0 => tx_req_wbm_i, + TX_DIN_0 => tx_dout_wbm_i, + TX_SOP_0 => tx_sop_wbm_i, + TX_EOP_0 => tx_eop_wbm_i, + TX_DWEN_0 => tx_dwen_wbm_i, + TX_RDY_0 => tx_rdy_wbm_i, + + TX_REQ_1 => tx_req_dma_i, + TX_DIN_1 => tx_data_dma_i, + TX_SOP_1 => tx_st_dma_i, + TX_EOP_1 => tx_end_dma_i, + TX_DWEN_1 => tx_dwen_dma_i, + TX_RDY_1 => tx_rdy_dma_i, + + TX_REQ_2 => '0', + TX_DIN_2 => (others => '0'), + TX_SOP_2 => '0', + TX_EOP_2 => '0', + TX_DWEN_2 => '0', + TX_RDY_2 => open, + + TX_REQ_3 => tx_req_ur_i, + TX_DIN_3 => tx_dout_ur_i, + TX_SOP_3 => tx_sop_ur_i, + TX_EOP_3 => tx_eop_ur_i, + TX_DWEN_3 => tx_dwen_ur_i, + TX_RDY_3 => tx_rdy_ur_i, + + TX_REQ => tx_req_i, + TX_DOUT => tx_data_i, + TX_SOP => tx_st_i, + TX_EOP => tx_end_i, + TX_DWEN => tx_dwen_i, + TX_RDY => tx_rdy_i + ); + +----------------------------------------------------------------------- +-- TLP Handler +----------------------------------------------------------------------- +THE_WB_TLC : wb_tlc + port map( + RSTN => rst_n, + CLK_125 => clk_125_i, + wb_clk => CLK_WB_IN, + + rx_data => rx_data_i, + rx_st => rx_st_i, + rx_end => rx_end_i, + rx_dwen => rx_dwen_i, + rx_bar_hit => rx_bar_hit_i, + + wb_adr_o => bus_addr_i, + wb_dat_o => BUS_WDAT_OUT, + wb_we_o => BUS_WE_OUT, + wb_sel_o => BUS_SEL_OUT, + wb_stb_o => BUS_STB_OUT, + wb_cyc_o => BUS_CYC_OUT, + wb_lock_o => BUS_LOCK_OUT, + wb_ack_i => BUS_ACK_IN, + wb_dat_i => BUS_RDAT_IN, + + pd_cr => pd_cr_wb_i, + ph_cr => ph_cr_wb_i, + npd_cr => npd_cr_wb_i, + nph_cr => nph_cr_wb_i, + + tx_rdy => tx_rdy_wbm_i, + tx_val => tx_val_i, + tx_req => tx_req_wbm_i, + tx_data => tx_dout_wbm_i, + tx_st => tx_sop_wbm_i, + tx_end => tx_eop_wbm_i, + tx_dwen => tx_dwen_wbm_i, + + comp_id => requestor_id_i, + + f_full => rx_f_full_i, + f_empty => rx_f_empty_i, + + debug => debug_wb_tlc_i + ); + +BUS_ADDR_OUT <= "00" & bus_addr_i(31 downto 2); + + + + +DEBUG_OUT(3 downto 0) <= lsm_status_i; +DEBUG_OUT(4) <= tx_val_i; + +DEBUG_OUT(31 downto 16) <= debug_wb_tlc_i(15 downto 0); + +end architecture; \ No newline at end of file diff --git a/design/wb_tlc.vhd b/design/wb_tlc.vhd new file mode 100644 index 0000000..5217525 --- /dev/null +++ b/design/wb_tlc.vhd @@ -0,0 +1,317 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + +entity wb_tlc is + port( + CLK_125_IN : in std_logic; + WB_CLK_IN : in std_logic; + RSTN_IN : in std_logic; + + RX_DATA_IN : in std_logic_vector(63 downto 0); + RX_ST_IN : in std_logic; + RX_END_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_BAR_HIT_IN : in std_logic_vector(6 downto 0); + + WB_ADR_OUT : out std_logic_vector(31 downto 0); + WB_DAT_OUT : out std_logic_vector(63 downto 0); + WB_WE_OUT : out std_logic; + WB_SEL_OUT : out std_logic_vector(7 downto 0); + WB_STB_OUT : out std_logic; + WB_CYC_OUT : out std_logic; + WB_LOCK_OUT : out std_logic; + WB_ACK_IN : in std_logic; + WB_DAT_IN : in std_logic_vector(63 downto 0); + + PD_CR_OUT : out std_logic; + PH_CR_OUT : out std_logic; + NPD_CR_OUT : out std_logic; + NPH_CR_OUT : out std_logic; + + TX_RDY_IN : in std_logic; + TX_VAL_IN : in std_logic; + TX_REQ_OUT : out std_logic; + TX_DATA_OUT : out std_logic_vector(63 downto 0); + TX_ST_OUT : out std_logic; + TX_END_OUT : out std_logic; + TX_DWEN_OUT : out std_logic; + + COMP_ID_IN : in std_logic_vector(15 downto 0); + + F_FULL_OUT : out std_logic; + F_EMPTY_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture wb_tlc_arch of wb_tlc is + + + +signal to_req_fifo_dout : std_logic_vector(63 downto 0); +signal to_req_fifo_sop : std_logic; +signal to_req_fifo_eop : std_logic; +signal to_req_fifo_bad : std_logic; +signal to_req_fifo_dwen : std_logic; +signal to_req_fifo_wrn : std_logic; +signal to_req_fifo_wen : std_logic; +signal to_req_fifo_bar : std_logic_vector(2 downto 0); + +signal from_req_fifo_dout : std_logic_vector(63 downto 0); +signal from_req_fifo_sop : std_logic; +signal from_req_fifo_eop : std_logic; +signal from_req_fifo_wrn : std_logic; +signal from_req_fifo_ren : std_logic; +signal from_req_fifo_bar : std_logic_vector(2 downto 0); + +signal tlp_avail : std_logic; +signal no_tlp_avail : std_logic; + +signal read_data : std_logic_vector(31 downto 0); +signal tran_len : std_logic_vector(9 downto 0); +signal tran_id : std_logic_vector(23 downto 0); +signal tran_be : std_logic_vector(7 downto 0); +signal tran_addr : std_logic_vector(4 downto 0); +signal tran_tc : std_logic_vector(2 downto 0); +signal tran_attr : std_logic_vector(1 downto 0); + +signal cmpl_d : std_logic_vector(63 downto 0); +signal cmpl_sop : std_logic; +signal cmpl_eop : std_logic; +signal cmpl_dwen : std_logic; +signal cmpl_wen : std_logic; + +signal ph_cr_wb : std_logic; + +signal encoded_bar_hit : std_logic_vector(2 downto 0); + +signal debug_wb_intf : std_logic_vector(31 downto 0); +signal debug_wb_tlc_cpld : std_logic_vector(31 downto 0); +signal debug_wb_tlc_cpld_fifo : std_logic_vector(31 downto 0); + +signal wb_adr_out_i : std_logic_vector(31 downto 0); +signal wb_dat_out_i : std_logic_vector(63 downto 0); +signal wb_we_out_i : std_logic; +signal wb_sel_out_i : std_logic_vector(7 downto 0); +signal wb_stb_out_i : std_logic; +signal wb_cyc_out_i : std_logic; +signal wb_lock_out_i : std_logic; +signal wb_read_i : std_logic; + +signal tx_data_out_i : std_logic_vector(63 downto 0); +signal tx_st_out_i : std_logic; +signal tx_end_out_i : std_logic; +signal tx_dwen_out_i : std_logic; +signal tx_req_out_i : std_logic; + + +begin + +----------------------------------------------------------------------- +-- TLP Decoder +----------------------------------------------------------------------- + + + encoded_bar_hit <= "000" when RX_BAR_HIT_IN = "0000001" else + "001" when RX_BAR_HIT_IN = "0000010" else + "010" when RX_BAR_HIT_IN = "0000100" else + "011" when RX_BAR_HIT_IN = "0001000" else + "100" when RX_BAR_HIT_IN = "0010000" else + "101" when RX_BAR_HIT_IN = "0100000" else + "110" when RX_BAR_HIT_IN = "1000000" else + "111"; + + THE_DECODER : wb_tlc_dec + port map( + RSTN_IN => RSTN_IN, + CLK_125_IN => CLK_125_IN, + + RX_DIN_IN + RX_SOP_IN => RX_DATA_IN, + RX_EOP_IN => RX_EOP_IN, + RX_DWEN_IN => RX_DWEN_IN, + RX_BAR_HIT_IN => encoded_bar_hit, + + FIFO_DOUT_OUT => to_req_fifo_dout, + FIFO_SOP_OUT => to_req_fifo_sop, + FIFO_EOP_OUT => to_req_fifo_eop, + FIFO_DWEN_OUT => to_req_fifo_dwen, + FIFO_WRN_OUT => to_req_fifo_wrn, + FIFO_WEN_OUT => to_req_fifo_wen, + FIFO_BAR_OUT => to_req_fifo_bar + ); + + +----------------------------------------------------------------------- +-- Request FiFo +----------------------------------------------------------------------- + + req_fifo_din <= '0' & encoded_bar_hit & to_req_fifo_dwen & to_req_fifo_wrn & to_req_fifo_eop + & to_req_fifo_sop & to_req_fifo_dout; + tlp_avail <= no_tlp_avail; + + from_req_fifo_dout <= req_fifo_dout(63 downto 0); + from_req_fifo_sop <= req_fifo_dout(64); + from_req_fifo_eop <= req_fifo_dout(65); + from_req_fifo_wrn <= req_fifo_dout(66); + from_req_fifo_dwen <= req_fifo_dout(67); + from_req_fifo_bar <= req_fifo_dout(70 downto 68); + + + THE_REQ_FIFO : fifo_72x512 + port map( + Data => req_fifo_din + WrClock => CLK_125_IN, + RdClock => WB_CLK_IN, + WrEn => to_req_fifo_wen, + RdEn => from_req_fifo_ren, + Reset => RSTN_IN, + RPReset => RSTN_IN, + Q => req_fifo_dout, + Empty => no_tlp_avail, + Full => open, + AlmostEmpty => F_EMPTY_OUT, + AlmostFull => F_FULL_OUT + ); + +----------------------------------------------------------------------- +-- Clock Domain Transfer +----------------------------------------------------------------------- + ph_cr_wb <= from_req_fifo_sop and from_req_fifo_wrn; + PD_CR_OUT <= ph_cr; + + THE_TLP_CR : wb_tlc_cr + port map( + CLK_125_IN => CLK_125_IN, + WB_CLK_IN => WB_CLK_IN, + RSTN_IN => RSTN_IN, + + CR_WB_IN => ph_cr_wb, + CR_125_OUT => ph_cr + ); + + +----------------------------------------------------------------------- +-- Wishbone Interface +----------------------------------------------------------------------- + THE_WB_INTF : wb_intf + port map( + RSTN_IN => RSTN_IN, + WB_CLK_IN => WB_CLK_IN, + + DIN => from_req_fifo_dout, + DIN_BAR => from_req_fifo_bar, + DIN_SOP => from_req_fifo_sop, + DIN_EOP => from_req_fifo_eop, + DIN_DWEN => from_req_fifo_dwen, + DIN_WRN => from_req_fifo_wrn, + DIN_REN => from_req_fifo_ren, + TLP_AVAIL_IN => tlp_avail, + + TRAN_ID_OUT => tran_id, + TRAN_LENGTH_OUT => tran_len, + TRAN_BE_OUT => tran_be, + TRAN_ADDR_OUT => tran_addr, + TRAN_TC_OUT => tran_tc, + TRAN_ATTR_OUT => tran_attr, + + WB_DAT_OUT => wb_dat_out_i, + WB_ADR_OUT => wb_adr_out_i, + WB_WE_OUT => wb_we_out_i, + WB_SEL_OUT => wb_sel_out_i, + WB_STB_OUT => wb_stb_out_i, + WB_CYC_OUT => wb_cyc_out_i, + WB_LOCK_OUT => wb_lock_out_i, + WB_ACK_IN => WB_ACK_IN, + DEBUG_OUT => debug_wb_intf + ); + + WB_DAT_OUT <= wb_dat_out_i; + WB_ADR_OUT <= wb_adr_out_i; + WB_WE_OUT <= wb_we_out_i; + WB_SEL_OUT <= wb_sel_out_i; + WB_STB_OUT <= wb_stb_out_i; + WB_CYC_OUT <= wb_cyc_out_i; + WB_LOCK_OUT<= wb_lock_out_i; + +----------------------------------------------------------------------- +-- TLC Completion Generation +----------------------------------------------------------------------- + read_data <= WB_DAT_IN(7 downto 0) & WB_DAT_IN(15 downto 8) & WB_DAT_IN(23 downto 16) & WB_DAT_IN(31 downto 24); + + wb_read_i <= wb_stb_out_i and not wb_we_out_i; + + + THE_TLC_COMPLETER : wb_tlc_cpld + port( + RSTN_IN => RSTN_IN, + WB_CLK_IN => WB_CLK_IN, + + DATA_IN => read_data, + SEL_IN => WB_SEL_OUT, + READ_IN => wb_read_i, + VALID_IN => WB_ACK_IN, + + TRAN_ID_IN => tran_id, + TRAN_LENGTH_IN => tran_len, + TRAN_BE_IN => tran_be, + TRAN_ADDR_IN => tran_addr, + TRAN_TC_IN => tran_tc, + TRAN_ATTR_IN => tran_attr, + + COMP_ID_IN => COMP_ID_IN, + DOUT_DATA_OUT => cmpl_d, + DOUT_SOP_OUT => cmpl_sop, + DOUT_EOP_OUT => cmpl_eop, + DOUT_DWEN_OUT => cmpl_dwen, + DOUT_WEN_OUT => cmpl_wen, + + DEBUG_OUT => debug_wb_tlc_cpld + ); + +----------------------------------------------------------------------- +-- TLC Completion FiFo +----------------------------------------------------------------------- + NPH_CR_OUT <= tx_st_out_i and TX_VAL_IN; + + TX_DATA_OUT <= tx_data_out_i; + TX_ST_OUT <= tx_st_out_i; + TX_END_OUT <= tx_end_out_i; + TX_DWEN_OUT <= tx_dwen_out_i; + TX_REQ_OUT <= tx_req_out_i; + + THE_TLC_CPLD_FIFO : wb_tlc_cpld_fifo + port map( + RSTN_IN => RSTN_IN, + WB_CLK_IN => WB_CLK_IN, + CLK_125_IN => CLK_125_IN, + + DIN_DATA_IN => cmpl_d, + DIN_SOP_IN => cmpl_sop, + DIN_EOP_IN => cmpl_eop, + DIN_DWEN_IN => cmpl_dwen, + DIN_WEN_IN => cmpl_wen, + + TX_DATA_OUT => tx_data_out_i, + TX_ST_OUT => tx_st_out_i, + TX_END_OUT => tx_end_out_i, + TX_DWEN_OUT => tx_dwen_out_i, + TX_REQ_OUT => tx_req_out_i, + TX_RDY_IN => TX_RDY_IN, + TX_VAL_IN => TX_VAL_IN, + + DEBUG_OUT => debug_wb_tlc_cpld_fifo + ); + + + +end architecture; \ No newline at end of file diff --git a/pcie_components.vhd b/pcie_components.vhd new file mode 100644 index 0000000..6e390b1 --- /dev/null +++ b/pcie_components.vhd @@ -0,0 +1,602 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.ALL; +library work; +use work.trb_net_std.all; + +package pcie_components is + +component pci_core is + port( + CLK_PCIE_IN : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_WB_IN : in std_logic; + CLK_125_OUT : out std_logic; + RESET_IN : in std_logic; + CLEAR_IN : in std_logic; + --PCIe + PCIE_DINP : in std_logic_vector(3 downto 0); + PCIE_DINN : in std_logic_vector(3 downto 0); + PCIE_DOUTP : out std_logic_vector(3 downto 0); + PCIE_DOUTN : out std_logic_vector(3 downto 0); + + --single access + BUS_ADDR_OUT : out std_logic_vector(31 downto 0); + BUS_WDAT_OUT : out std_logic_vector(63 downto 0); + BUS_RDAT_IN : in std_logic_vector(63 downto 0); + BUS_SEL_OUT : out std_logic_vector(7 downto 0); + BUS_WE_OUT : out std_logic; + BUS_CYC_OUT : out std_logic; + BUS_STB_OUT : out std_logic; + BUS_LOCK_OUT : out std_logic; +-- BUS_CTI_OUT : out std_logic_vector(2 downto 0); + BUS_ACK_IN : in std_logic; +-- BUS_ERR_IN : in std_logic; +-- BUS_RETRY_IN : in std_logic; +-- BUS_EOD_IN : in std_logic; + + --DMA + DMA_ADDR : in std_logic_vector(31 downto 0); + DMA_WDAT : in std_logic_vector(63 downto 0); + DMA_RDAT : out std_logic_vector(63 downto 0); + DMA_SEL : in std_logic_vector(7 downto 0); + DMA_WE : in std_logic; + DMA_CYC : in std_logic; + DMA_STB : in std_logic; + DMA_LOCK : in std_logic; + DMA_CTI : in std_logic_vector(2 downto 0); + DMA_ACK : out std_logic; + DMA_ERR : out std_logic; + DMA_RETRY : out std_logic; + DMA_EOD : out std_logic; + + --Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + +end component; + + +--Handler for unsupported requests +component UR_gen is + port( + RSTN : in std_logic; + CLK : in std_logic; + RX_DIN : in std_logic_vector(63 downto 0); + RX_SOP : in std_logic; + RX_EOP : in std_logic; + RX_DWEN : in std_logic; + RX_US : in std_logic; + RX_BAR_HIT : in std_logic_vector(6 downto 0); + TX_RDY : in std_logic; + TX_VAL : in std_logic; + TX_REQ : out std_logic; + TX_DOUT : out std_logic_vector(63 downto 0); + TX_SOP : out std_logic; + TX_EOP : out std_logic; + TX_DWEN : out std_logic; + COMP_ID : in std_logic_vector(15 downto 0) + ); +end component; + + +component dma_adapter is + port( + RSTN : in std_logic; + CLK_125 : in std_logic; + ENABLE : in std_logic; + + WB_CLK_I : in std_logic; + WB_RST_I : in std_logic; + WB_DAT_I : in std_logic_vector(63 downto 0); + WB_ADR_I : in std_logic_vector(31 downto 0); + WB_CYC_I : in std_logic; + WB_LOCK_I : in std_logic; + WB_SEL_I : in std_logic_vector(7 downto 0); + WB_STB_I : in std_logic; + WB_WE_I : in std_logic; + WB_DAT_O : out std_logic_vector(63 downto 0); + WB_ACK_O : out std_logic; + WB_ERR_O : out std_logic; + WB_RTY_O : out std_logic; + + DMA_REQ : out std_logic_vector(1 downto 0); + DMA_ACK : in std_logic_vector(1 downto 0); + BURST_LEN : in std_logic_vector(15 downto 0); + ACTIVE_CH : in std_logic_vector(1 downto 0); + REQUESTOR_ID : in std_logic_vector(15 downto 0); + + TX_ST : out std_logic; + TX_END : out std_logic; + TX_DWEN : out std_logic; + TX_DATA : out std_logic_vector(63 downto 0); + TX_REQ : out std_logic; + TX_RDY : in std_logic; + TX_VAL : in std_logic; + TX_CA_PH : in std_logic_vector(8 downto 0); + TX_CA_PD : in std_logic_vector(12 downto 0); + TX_CA_NPH : in std_logic_vector(8 downto 0); + + RX_CR_CPLH : out std_logic; + RX_CR_CPLD : out std_logic_vector(7 downto 0); + UNEXP_CMPL : out std_logic; + RX_ST : in std_logic; + RX_END : in std_logic; + RX_DWEN : in std_logic; + RX_DATA : in std_logic_vector(63 downto 0); + + DEBUG : out std_logic_vector(31 downto 0) + ); +end component; + + + + + + +component pciexp2 is + port( + rst_n : in std_logic; + serdes_rst : in std_logic; + refclk_250 : in std_logic; + clk_50 : in std_logic; + sys_clk_125 : out std_logic; + flip_lanes : in std_logic; + + inta_n : in std_logic; + msi : in std_logic_vector(7 downto 0); + + hdinp_0 : in std_logic; + hdinn_0 : in std_logic; + hdinp_1 : in std_logic; + hdinn_1 : in std_logic; + hdinp_2 : in std_logic; + hdinn_2 : in std_logic; + hdinp_3 : in std_logic; + hdinn_3 : in std_logic; + hdoutp_0 : out std_logic; + hdoutn_0 : out std_logic; + hdoutp_1 : out std_logic; + hdoutn_1 : out std_logic; + hdoutp_2 : out std_logic; + hdoutn_2 : out std_logic; + hdoutp_3 : out std_logic; + hdoutn_3 : out std_logic; + + force_lsm_active : in std_logic; + force_rec_ei : in std_logic; + force_phy_status : in std_logic; + force_disable_scr : in std_logic; + + hl_snd_beacon : in std_logic; + hl_disable_scr : in std_logic; + hl_gto_dis : in std_logic; + hl_gto_det : in std_logic; + hl_gto_hrst : in std_logic; + hl_gto_l0stx : in std_logic; + hl_gto_l1 : in std_logic; + hl_gto_l2 : in std_logic; + hl_gto_l0stxfts : in std_logic; + hl_gto_lbk : in std_logic_vector(3 downto 0); + hl_gto_rcvry : in std_logic; + hl_gto_cfg : in std_logic; + no_pcie_train : in std_logic; + + --Power Management + tx_dllp_val : in std_logic_vector(1 downto 0); + tx_pmtype : in std_logic_vector(2 downto 0); + tx_vsd_data : in std_logic_vector(23 downto 0); + + --For VC Inputs + tx_req_vc0 : in std_logic; -- VC0 Request from User + tx_data_vc0 : in std_logic_vector(63 downto 0); -- VC0 Input data from user logic + tx_st_vc0 : in std_logic; -- VC0 start of pkt from user logic. + tx_end_vc0 : in std_logic; -- VC0 End of pkt from user logic. + tx_nlfy_vc0 : in std_logic; -- VC0 End of nullified pkt from user logic. + tx_dwen_vc0 : in std_logic; -- VC0 Dword enable from user logic. + ph_buf_status_vc0 : in std_logic; -- VC0 Indicate the Full/alm.Full status of the PH buffers + pd_buf_status_vc0 : in std_logic; -- VC0 Indicate PD Buffer has got space less than Max Pkt size + nph_buf_status_vc0 : in std_logic; -- VC0 For NPH + npd_buf_status_vc0 : in std_logic; -- VC0 For NPD + ph_processed_vc0 : in std_logic; -- VC0 TL has processed one TLP Header - PH Type + pd_processed_vc0 : in std_logic; -- VC0 TL has processed one TLP Data - PD TYPE + nph_processed_vc0 : in std_logic; -- VC0 For NPH + npd_processed_vc0 : in std_logic; -- VC0 For NPD + pd_num_vc0 : in std_logic_vector(7 downto 0); -- VC0 For PD -- No. of Data processed + npd_num_vc0 : in std_logic_vector(7 downto 0); -- VC0 For PD + + --From User logic + cmpln_tout : in std_logic; -- Completion time out. + cmpltr_abort : in std_logic; -- Completor abort. + unexp_cmpln : in std_logic; -- Unexpexted completion. + ur_np_ext : in std_logic; -- UR for NP type. + ur_p_ext : in std_logic; -- UR for P type. + np_req_pend : in std_logic; -- Non posted request is pending. + pme_status : in std_logic; -- PME status to reg 044h. + rx_rst : in std_logic; + prog_done : in std_logic; + + + -- System bus + sysbus_in : in std_logic_vector(44 downto 0); -- System bus inputs to PCS + sysbus_out : out std_logic_vector(16 downto 0); -- PCS outputs to System bus + + -- Power Management/ Vendor specific DLLP + tx_dllp_sent : out std_logic; -- Requested PM DLLP is sent + rxdp_pmd_type : out std_logic_vector(2 downto 0); -- PM DLLP type bits. + rxdp_vsd_data : out std_logic_vector(23 downto 0); -- Vendor specific DLLP data. + rxdp_dllp_val : out std_logic_vector(1 downto 0); -- PM/Vendor specific DLLP valid. + + phy_cfgln : out std_logic_vector(3 downto 0); -- Indicates the Configured Lanes + phy_cfgln_sum : out std_logic_vector(2 downto 0); -- Number of Configured lanes + phy_pol_compliance : out std_logic; -- Polling compliance + phy_realign_req : out std_logic; + phy_ltssm_state : out std_logic_vector(3 downto 0); + phy_ltssm_substate : out std_logic_vector(2 downto 0); + phy_l0s_tx_state : out std_logic_vector(2 downto 0); + phy_l1_state : out std_logic_vector(1 downto 0); + phy_l2_state : out std_logic_vector(1 downto 0); + phy_mloopback : out std_logic; + phy_sloopback : out std_logic; + phy_snd_beacon : out std_logic; + + + -- Extra + lsm_status_0 : out std_logic; + lsm_status_1 : out std_logic; + lsm_status_2 : out std_logic; + lsm_status_3 : out std_logic; + + tx_val : out std_logic; -- Valid signal toggles during x2/x1 downgrade + + tx_rdy_vc0 : out std_logic; -- VC0 TX ready indicating signal + tx_ca_ph_vc0 : out std_logic_vector(8 downto 0); -- VC0 Available credit for Posted Type Headers + tx_ca_pd_vc0 : out std_logic_vector(12 downto 0); -- VC0 For Posted - Data + tx_ca_nph_vc0 : out std_logic_vector(8 downto 0); -- VC0 For Non-posted - Header + tx_ca_npd_vc0 : out std_logic_vector(12 downto 0); -- VC0 For Non-posted - Data + tx_ca_cplh_vc0 : out std_logic_vector(8 downto 0); -- VC0 For Completion - Header + tx_ca_cpld_vc0 : out std_logic_vector(12 downto 0); -- VC0 For Completion - Data + tx_ca_p_recheck_vc0 : out std_logic; + tx_ca_cpl_recheck_vc0 : out std_logic; + rx_data_vc0 : out std_logic_vector(63 downto 0); -- VC0 Receive data + rx_st_vc0 : out std_logic; -- VC0 Receive data start + rx_end_vc0 : out std_logic; -- VC0 Receive data end + rx_dwen_vc0 : out std_logic; -- VC0 Dword enable + rx_us_req_vc0 : out std_logic; -- VC0 unsupported req received + rx_malf_tlp_vc0 : out std_logic; -- VC0 malformed TLP in received data + rx_bar_hit : out std_logic_vector(6 downto 0); -- Bar hit + mm_enable : out std_logic_vector(2 downto 0); -- Multiple message enable bits of Register + msi_enable : out std_logic; -- MSI enable bit of Register + + -- From Config Registers + bus_num : out std_logic_vector(7 downto 0); -- Bus number + dev_num : out std_logic_vector(4 downto 0); -- Device number + func_num : out std_logic_vector(2 downto 0); -- Function number + pm_power_state : out std_logic_vector(1 downto 0); -- Power state bits of Register at 044h + pme_en : out std_logic; -- PME_En at 044h + cmd_reg_out : out std_logic_vector(5 downto 0); -- Bits 1086210 From register 004h + dev_cntl_out : out std_logic_vector(14 downto 0); -- Divice control register at 060h + lnk_cntl_out : out std_logic_vector(7 downto 0); -- Link control register at 068h + + -- Data Link Control SM Status + dl_inactive : out std_logic; -- Data Link Control SM is in INACTIVE state + dl_init : out std_logic; -- INIT state + dl_active : out std_logic; -- ACTIVE state + dl_up : out std_logic -- Data Link Layer is UP + ); +end component; + + +component pll_in100_out150 is + generic ( + SMI_OFFSET : in String := "0x410" + ); + port ( + clk: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic + ); +end component; + + +component pll_in100_out50_250 is + generic ( + SMI_OFFSET : in String := "0x410" + ); + port ( + clk: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic + ); +end component; + + +component ip_rx_crpr is + port( + clk : in std_logic; + rstn : in std_logic; + rx_st : in std_logic; + rx_end : in std_logic; + rx_din : in std_logic_vector(63 downto 0); + rx_dwen : in std_logic; + rx_bar_hit : in std_logic_vector(6 downto 0); + pd_cr : out std_logic; + pd_num : out std_logic_vector(7 downto 0); + ph_cr : out std_logic; + npd_cr : out std_logic; + nph_cr : out std_logic + ); +end component; + + +component ip_crpr_arb is + port( + clk : in std_logic; + rstn : in std_logic; + + pd_cr_0 : in std_logic; + pd_num_0 : in std_logic_vector(7 downto 0); + ph_cr_0 : in std_logic; + npd_cr_0 : in std_logic; + nph_cr_0 : in std_logic; + pd_cr_1 : in std_logic; + pd_num_1 : in std_logic_vector(7 downto 0); + ph_cr_1 : in std_logic; + npd_cr_1 : in std_logic; + nph_cr_1 : in std_logic; + + pd_cr : out std_logic; + pd_num : out std_logic_vector(7 downto 0); + ph_cr : out std_logic; + npd_cr : out std_logic; + nph_cr : out std_logic + ); +end component; + +component ip_tx_arbiter is + port( + clk : in std_logic; + rstn : in std_logic; + tx_val : in std_logic; + + tx_req_0 : in std_logic; + tx_din_0 : in std_logic_vector(63 downto 0); + tx_sop_0 : in std_logic; + tx_eop_0 : in std_logic; + tx_dwen_0 : in std_logic; + tx_rdy_0 : out std_logic; + + tx_req_1 : in std_logic; + tx_din_1 : in std_logic_vector(63 downto 0); + tx_sop_1 : in std_logic; + tx_eop_1 : in std_logic; + tx_dwen_1 : in std_logic; + tx_rdy_1 : out std_logic; + + tx_req_2 : in std_logic; + tx_din_2 : in std_logic_vector(63 downto 0); + tx_sop_2 : in std_logic; + tx_eop_2 : in std_logic; + tx_dwen_2 : in std_logic; + tx_rdy_2 : out std_logic; + + tx_req_3 : in std_logic; + tx_din_3 : in std_logic_vector(63 downto 0); + tx_sop_3 : in std_logic; + tx_eop_3 : in std_logic; + tx_dwen_3 : in std_logic; + tx_rdy_3 : out std_logic; + + tx_req : out std_logic; + tx_dout : out std_logic_vector(63 downto 0); + tx_sop : out std_logic; + tx_eop : out std_logic; + tx_dwen : out std_logic; + tx_rdy : in std_logic + ); +end component; + + +component wb_tlc is + port( + CLK_125_IN : in std_logic; + WB_CLK_IN : in std_logic; + RSTN_IN : in std_logic; + + RX_DATA_IN : in std_logic_vector(63 downto 0); + RX_ST_IN : in std_logic; + RX_END_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_BAR_HIT_IN : in std_logic_vector(6 downto 0); + + WB_ADR_OUT : out std_logic_vector(31 downto 0); + WB_DAT_OUT : out std_logic_vector(63 downto 0); + WB_WE_OUT : out std_logic; + WB_SEL_OUT : out std_logic_vector(7 downto 0); + WB_STB_OUT : out std_logic; + WB_CYC_OUT : out std_logic; + WB_LOCK_OUT : out std_logic; + WB_ACK_IN : in std_logic; + WB_DAT_IN : in std_logic_vector(63 downto 0); + + PD_CR_OUT : out std_logic; + PH_CR_OUT : out std_logic; + NPD_CR_OUT : out std_logic; + NPH_CR_OUT : out std_logic; + + TX_RDY_IN : in std_logic; + TX_VAL_IN : in std_logic; + TX_REQ_OUT : out std_logic; + TX_DATA_OUT : out std_logic_vector(63 downto 0); + TX_ST_OUT : out std_logic; + TX_END_OUT : out std_logic; + TX_DWEN_OUT : out std_logic; + + COMP_ID_IN : in std_logic_vector(15 downto 0); + + F_FULL_OUT : out std_logic; + F_EMPTY_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; + + +component wb_tlc_dec is + port( + RSTN_IN : in std_logic; + CLK_125_IN : in std_logic; + + RX_DIN_IN : in std_logic_vector(63 downto 0); + RX_SOP_IN : in std_logic; + RX_EOP_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_BAR_HIT_IN : in std_logic_vector(2 downto 0); + FIFO_DOUT_OUT : out std_logic_vector(63 downto 0); + FIFO_SOP_OUT : out std_logic; + FIFO_EOP_OUT : out std_logic; + FIFO_DWEN_OUT : out std_logic; + FIFO_WRN_OUT : out std_logic; + FIFO_WEN_OUT : out std_logic; + FIFO_BAR_OUT : out std_logic_vector(6 downto 0) + ); +end component; + +component fifo_72x512 is + port ( + Data: in std_logic_vector(71 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end component; + +component cpld_fifo is + port ( + Data: in std_logic_vector(66 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(66 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end component; + + +component wb_tlc_cr is + port( + CLK_125_IN : in std_logic; + WB_CLK_IN : in std_logic; + RSTN_IN : in std_logic; + + CR_WB_IN : in std_logic; + CR_125 : out std_logic + ); +end component + + +component wb_intf is + port( + RSTN_IN : in std_logic; + WB_CLK_IN : in std_logic; + + DIN : in std_logic_vector(63 downto 0); + DIN_BAR : in std_logic_vector(2 downto 0); + DIN_SOP : in std_logic; + DIN_EOP : in std_logic; + DIN_DWEN : in std_logic; + DIN_WRN : in std_logic; + DIN_REN : out std_logic; + TLP_AVAIL_IN : in std_logic; + + TRAN_ID_OUT : out std_logic_vector(23 downto 0); + TRAN_LENGTH_OUT : out std_logic_vector(9 downto 0); + TRAN_BE_OUT : out std_logic_vector(7 downto 0); + TRAN_ADDR_OUT : out std_logic_vector(4 downto 0); + TRAN_TC_OUT : out std_logic_vector(2 downto 0); + TRAN_ATTR_OUT : out std_logic_vector(1 downto 0); + + WB_DAT_OUT : out std_logic_vector(31 downto 0); + WB_ADR_OUT : out std_logic_vector(31 downto 0); + WB_WE_OUT : out std_logic; + WB_SEL_OUT : out std_logic_vector(7 downto 0); + WB_STB_OUT : out std_logic; + WB_CYC_OUT : out std_logic; + WB_LOCK_OUT : out std_logic; + WB_ACK_IN : in std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; + + +component wb_tlc_cpld is + port( + WB_CLK_IN : in std_logic; + RSTN_IN : in std_logic; + + DATA_IN : in std_logic_vector(31 downto 0); + SEL_IN : in std_logic_vector(7 downto 0); + READ_IN : in std_logic; + VALID_IN : in std_logic; + + TRAN_ID_IN : in std_logic_vector(23 downto 0); + TRAN_LENGTH_IN : in std_logic_vector(9 downto 0); + TRAN_BE_IN : in std_logic_vector(7 downto 0); + TRAN_ADDR_IN : in std_logic_vector(4 downto 0); + TRAN_TC_IN : in std_logic_vector(2 downto 0); + TRAN_ATTR_IN : in std_logic_vector(1 downto 0); + + COMP_ID_IN : in std_logic_vector(15 downto 0); + DOUT_DATA_OUT : out std_logic_vector(63 downto 0); + DOUT_SOP_OUT : out std_logic; + DOUT_EOP_OUT : out std_logic; + DOUT_DWEN_OUT : out std_logic; + DOUT_WEN_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; + + + +component wb_tlc_cpld_fifo is + port( + WB_CLK_IN : in std_logic; + CLK_125_IN : in std_logic; + RSTN_IN : in std_logic; + + DIN_DATA_IN : in std_logic_vector(63 downto 0); + DIN_SOP_IN : in std_logic; + DIN_EOP_IN : in std_logic; + DIN_DWEN_IN : in std_logic; + DIN_WEN_IN : in std_logic; + + TX_DATA_OUT : out std_logic_vector(63 downto 0); + TX_ST_OUT : out std_logic; + TX_END_OUT : out std_logic; + TX_DWEN_OUT : out std_logic; + TX_REQ_OUT : out std_logic; + TX_RDY_OUT : out std_logic; + TX_VAL_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; + + + +end package; diff --git a/pexor.p2t b/pexor.p2t new file mode 100644 index 0000000..9ce01fc --- /dev/null +++ b/pexor.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 1 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + diff --git a/pexor.prj b/pexor.prj new file mode 100644 index 0000000..5c99309 --- /dev/null +++ b/pexor.prj @@ -0,0 +1,159 @@ + +#add_file options +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "pcie_components.vhd" + + +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/pulse_stretch.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint.vhd" +add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_apl.vhd" + +#Lattice SCM files +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out100.vhd" + +############################# +add_file -vhdl -lib work "../trbnet/lattice/scm/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_200.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_100.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_100_ext.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd" +############################# + +add_file -verilog "/d/sugar/lattice/diamond/1.1/cae_library/synthesis/verilog/scm.v" +add_file -vhdl -lib work "design/pci_core.vhd" +add_file -verilog "vcode/pci_exp_ddefines.v" +add_file -verilog "vcode/pci_exp_params.v" +add_file -verilog "vcode/ip_crpr_arb.v" +add_file -verilog "vcode/ip_rx_crpr.v" +add_file -verilog "vcode/ip_tx_arbiter.v" +add_file -verilog "vcode/wb_tlc_cpld_fifo.v" +add_file -verilog "vcode/wb_tlc_cpld.v" +add_file -verilog "vcode/wb_tlc_cr.v" +add_file -verilog "vcode/wb_tlc_dec.v" +add_file -verilog "vcode/wb_tlc_req_fifo.v" +add_file -verilog "vcode/wb_tlc.v" +add_file -verilog "vcode/UR_gen.v" +add_file -verilog "vcode/dma_adapter.v" +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out150.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out50_250.vhd" +add_file -verilog "vcode/tlc_fifo.v" +add_file -verilog "vcode/wb_intf.v" +add_file -verilog "vcode/cpld_fifo.v" +add_file -verilog "vcode/pciexp2_bb.v" + + +add_file -vhdl -lib work "pexor.vhd" + +#################### + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-SCM +set_option -part LFSCM3GA40EP1 +set_option -package FF1020C +set_option -speed_grade -5 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "pexor" + +# map options +set_option -frequency 100 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +# set_option -force_gsr auto +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/pexor.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + diff --git a/size.txt b/size.txt new file mode 100644 index 0000000..820a6c6 --- /dev/null +++ b/size.txt @@ -0,0 +1,21 @@ +17.01.2011 + + IO 77/788 9% used + LOGIC 10392/20952 49% used + SPECIAL 58/462 12% used + + PIO (prelim) 77/696 11% used + 77/562 13% bonded + + SLICE 10388/20256 51% used + IOLOGIC 4/696 0% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 49/216 22% used + PCS 2/4 50% used + MACO 2/10 20% used + + + -- 2.43.0