From 087d41ff0de5326c842008f74909540562e1405f Mon Sep 17 00:00:00 2001 From: hades Date: Sat, 11 Nov 2000 11:32:33 +0000 Subject: [PATCH] Readout changed for conc board --- hadaq/hwtip.c | 67 +++++++--------------- hadaq/tof_defs.h | 143 ++++++++++++++++++++++++++++++++++++----------- 2 files changed, 128 insertions(+), 82 deletions(-) diff --git a/hadaq/hwtip.c b/hadaq/hwtip.c index c7e77d9..927840c 100644 --- a/hadaq/hwtip.c +++ b/hadaq/hwtip.c @@ -119,7 +119,7 @@ int conHwTip(HwTip * my, const char *name, const Param *param) } my->lvme = allocMem(sizeof(LVme)); - if (0 > conLVme(my->lvme, cardBase, 0x2000000UL, 0x09UL, 0, 0)) { + if (0 > conLVme(my->lvme, cardBase, 0x4000000UL, 0x09UL, 0, 0)) { msglog(LOG_ERR, "HwTip on %p not found\n", cardBase); return -1; } @@ -127,10 +127,10 @@ int conHwTip(HwTip * my, const char *name, const Param *param) my->currAddr = 0xffffffff; /* start at the end */ my->bankRequested = 1; /* of the empty bank */ - my->pipeFull = LVL2_PIPE2_FULL; - my->daqRq = LVL2_DAQ2_RQ; - my->daqGr = LVL2_DAQ2_GR; - my->fifo = LVL2_PIPE2_BASE; + my->pipeFull = _LVL2_PIPE2_FULL; + my->daqRq = _LVL2_PIPE2_RQ; + my->daqGr = _LVL2_PIPE2_GR; + my->fifo = MEMBASE + 0x40000; return 0; } @@ -144,14 +144,9 @@ void desHwTip(HwTip * my) void HwTip_requestBuffer(HwTip * my) { - { - LVme_L v; + LVme_clrBitL(my->lvme, CONFIG1BASE + CFG_MASTER_CONTROL, my->daqRq); - v = berrGetL(my->lvme, EXT_DAQ); - berrSetL(my->lvme, EXT_DAQ, v & ~my->daqRq); - } - - while (berrGetL(my->lvme, EXT_STATUS) & my->daqGr) { + while (LVme_tstBitL(my->lvme, CONFIG1BASE + CFG_MASTER_STATUS, my->daqGr)) { #if 1 struct timespec tS, *t = &tS; t->tv_sec = 0; @@ -161,19 +156,19 @@ void HwTip_requestBuffer(HwTip * my) } if (my->bankRequested == 0) { my->bankRequested = 1; - my->pipeFull = LVL2_PIPE2_FULL; - my->daqRq = LVL2_DAQ2_RQ; - my->daqGr = LVL2_DAQ2_GR; - my->fifo = LVL2_PIPE2_BASE; + my->pipeFull = _LVL2_PIPE2_FULL; + my->daqRq = _LVL2_PIPE2_RQ; + my->daqGr = _LVL2_PIPE2_GR; + my->fifo = MEMBASE + 0x40000; } else { my->bankRequested = 0; - my->pipeFull = LVL2_PIPE1_FULL; - my->daqRq = LVL2_DAQ1_RQ; - my->daqGr = LVL2_DAQ1_GR; - my->fifo = LVL2_PIPE1_BASE; + my->pipeFull = _LVL2_PIPE1_FULL; + my->daqRq = _LVL2_PIPE1_RQ; + my->daqGr = _LVL2_PIPE1_GR; + my->fifo = MEMBASE; } msglog(LOG_DEBUG, "wait for data\n"); - while (!(berrGetL(my->lvme, EXT_STATUS) & my->pipeFull)) { + while (!LVme_tstBitL(my->lvme, CONFIG1BASE + CFG_MASTER_STATUS, my->pipeFull)) { #if 1 struct timespec tS, *t = &tS; t->tv_sec = 0; @@ -182,32 +177,14 @@ void HwTip_requestBuffer(HwTip * my) #endif } msglog(LOG_DEBUG, "data available\n"); - { - LVme_L v; - - v = berrGetL(my->lvme, EXT_DAQ); - berrSetL(my->lvme, EXT_DAQ, v | my->daqRq); - } - -#if 0 - { - int i; - unsigned size; - - size = berrGetL(my->lvme, my->fifo); - msglog(LOG_DEBUG, "fifo size: 0x%08x\n", size); - for (i = 0; i < size; i += 4) { - msglog(LOG_DEBUG, "fifo data: 0x%08x\n", berrGetL(my->lvme, my->fifo + i)); - } - } -#endif + LVme_setBitL(my->lvme, CONFIG1BASE + CFG_MASTER_CONTROL, my->daqRq); - my->currAddr = my->fifo + 0x8; + my->currAddr = my->fifo + 0x4; } int HwTip_isBusy(HwTip * my) { - return !(berrGetL(my->lvme, EXT_STATUS) & my->daqGr); + return !LVme_tstBitL(my->lvme, CONFIG1BASE + CFG_MASTER_STATUS, my->daqGr); } int HwTip_isEmpty(HwTip * my) @@ -227,12 +204,6 @@ int HwTip_readSubEvt(HwTip * my, void *subEvt) msglog(LOG_DEBUG, "size: 0x%08x\n", size); } while(size > 2250); -#if 0 - if (size > 2400) { - msglog(LOG_ERR, "size too large: 0x%08x on 0x%08x\n", size, my->currAddr); - } -#endif - /* copy one sub evt from RC to memory */ firstAddr = my->currAddr; /* take the size from above to use the check */ diff --git a/hadaq/tof_defs.h b/hadaq/tof_defs.h index a096733..c7ddf5e 100644 --- a/hadaq/tof_defs.h +++ b/hadaq/tof_defs.h @@ -1,55 +1,130 @@ -/**** Headerfile for TOF-RTU registers */ -/**** E.Lins 13-Jan-2000 */ +/**** Headerfile for TOF-IPU registers */ +/**** created: E.Lins 13-Jan-2000 */ -/* $Id: tof_defs.h,v 1.2 2000-05-09 13:36:08 hades Exp $ */ +/* $Id: tof_defs.h,v 1.3 2000-11-11 11:32:33 hades Exp $ */ /* $Source: /misc/hadesprojects/daq/cvsroot/eventbuilder/hadaq/Attic/tof_defs.h,v $ */ +/****************************************************************/ + /* Onboard components base addresses... */ -#define MEMBASE 0x01000000 +/* the DSPs */ +#define SHARC1BASE 0x01000000 +#define SHARC2BASE 0x01200000 +#define SHARC3BASE 0x01400000 +#define SHARC4BASE 0x01600000 +#define SHARC5BASE 0x01800000 +#define SHARC6BASE 0x01a00000 + +/* the other stuff */ +#define MEMBASE 0x02000000 +#define MEMTOP 0x020f9fff + +#define SCV64BASE 0x02400000 +#define DISPBASE 0x02500000 +#define STATUSBASE 0x02600000 +#define FIFOBASE 0x02700000 +#define LINKBASE 0x02800000 + + + +/****************************************************************/ + +/* special purpose area in internal memory */ +/* DSP#1 */ +#define CONFIG1BASE (SHARC1BASE + 0x000a0000) +#define CONFIG2BASE (SHARC2BASE + 0x000a0000) +#define CONFIG3BASE (SHARC3BASE + 0x000a0000) +#define CONFIG4BASE (SHARC4BASE + 0x000a0000) +#define CONFIG5BASE (SHARC5BASE + 0x000a0000) +#define CONFIG6BASE (SHARC5BASE + 0x000a0000) + +/* register offsets (32bit words) in configbase area */ +#define CFG_MASTER_CONTROL 0x0000 +#define _START_TIP 0 +#define _LVL2_TRIG_ACTIVE 1 +#define _LVL2_LINK_ACTIVE 2 +#define _MU_LINK_ACTIVE 3 +#define _LVL2_PIPE1_RQ 4 +#define _LVL2_PIPE2_RQ 5 + +#define CFG_MASTER_STATUS 0x0004 +#define _LVL1_PIPE_FULL 0 +#define _LVL2_PIPE1_FULL 1 +#define _LVL2_PIPE2_FULL 2 +#define _LVL2_PIPE 3 +#define _LVL2_PIPE1_GR 4 +#define _LVL2_PIPE2_GR 5 + +#define CFG_DEBUG_CONTROL 0x0008 +#define _DEBUG_DUMP 3 + +#define CFG_LVL1_PIPE_SIZE 0x000c + +#define CFG_T_BEGIN_RUN 0x0010 +#define CFG_T_END_RUN 0x0014 +#define CFG_T_SPILL_ON 0x0018 +#define CFG_T_SPILL_OFF 0x001c + +#define CFG_TOTAL_EVENTS 0x0020 + + +/* number of vme modules to be rout */ +#define CFG_NOF_MODULES 0x002c + +/* declaration of vme modules toread out starts here */ +#define CFG_VME_MODULES 0x0030 +/* one vme module is described with ... words */ +#define CFG_SOURCE_ADDRESS 0x0 +#define CFG_BLT_FLAG 0x4 +#define CFG_CYCLE_COUNT 0x8 +#define CFG_DUMMY_WORD 0xc + +/* special purpose areas in external memory */ + +#define SNIFF1BASE (MEMBASE + 0x000fa000) +#define SNIFF1TOP (MEMBASE + 0x000faf00) +#define SNIFF2BASE (MEMBASE + 0x000fb000) +#define SNIFF2TOP (MEMBASE + 0x000fbf00) +#define SNIFF3BASE (MEMBASE + 0x000fc000) +#define SNIFF3TOP (MEMBASE + 0x000fcf00) +#define SNIFF4BASE (MEMBASE + 0x000fd000) +#define SNIFF4TOP (MEMBASE + 0x000fdf00) +#define SNIFF5BASE (MEMBASE + 0x000fe000) +#define SNIFF5TOP (MEMBASE + 0x000fef00) +#define SNIFF6BASE (MEMBASE + 0x000ff000) +#define SNIFF6TOP (MEMBASE + 0x000fff00) + +/****************************************************************/ -#define SCV64BASE 0x01400000 -#define DISPBASE 0x01500000 -#define STATUSBASE 0x01600000 -#define SHARC1BASE 0x00000000 -#define SHARC2BASE 0x00200000 -#define SHARC3BASE 0x00400000 -#define SHARC4BASE 0x00600000 -#define SHARC5BASE 0x00800000 -#define SHARC6BASE 0x00a00000 -#define LVL2_PIPE1_BASE 0x01000000 -#define LVL2_PIPE2_BASE 0x01008000 +#define LVL1_PIPE_BASE 0x00000000 -/* registers in external memory */ -#define EXT_DAQ 0x010fffe0 -#define EXT_STATUS 0x010ffff0 -#define EXT_MISC1 0x010ffff4 -#define EXT_MISC2 0x010ffff8 +/* define bits of the XILINX internal status register STATUSBASE */ -/* define some bits of the internal status register */ +#define _KBERR 0 +#define _KHALT 1 +#define _VMEINT 2 -#define LVL1_PIPE_FULL 0x00000001U -#define LVL2_PIPE1_FULL 0x00000002U -#define LVL2_PIPE2_FULL 0x00000004U -#define LVL2_PIPE 0x00000008U +#define _XGP1 4 +#define _XGP2 5 +#define _XGP3 6 +#define _XGSR 7 -#define LVL1_BUSY 0x00000010U -#define LVL2_BUSY 0x00000020U +#define _START_MU 8 +#define _FIFOFULL 9 +#define _ADDRESSMATCH 10 +#define _KSIZE1 11 -#define LVL2_DAQ1_BSY 0x00000100U -#define LVL2_DAQ2_BSY 0x00000200U -#define LVL2_DAQ1_GR 0x00001000U -#define LVL2_DAQ2_GR 0x00002000U -/* bits in the daq register */ +/* define the BUSYs */ +#define _LVL1_BUSY 4 +#define _LVL2_BUSY 5 -#define LVL2_DAQ1_RQ 0x00000001U -#define LVL2_DAQ2_RQ 0x00000002U /* TUNDRA internal registers */ -- 2.43.0