From 08d7e6781009afc6813a339fe433ef69a558de9c Mon Sep 17 00:00:00 2001 From: hadaq Date: Tue, 17 Jan 2012 12:03:03 +0000 Subject: [PATCH] *** empty log message *** --- cts_fpga1_test.vhd | 27 ++++++++++----------------- cts_simulation_tb.mpf | 2 +- version.vhd | 2 +- 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/cts_fpga1_test.vhd b/cts_fpga1_test.vhd index 719209f..c487585 100644 --- a/cts_fpga1_test.vhd +++ b/cts_fpga1_test.vhd @@ -2,17 +2,10 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_1164.all; use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; -use work.version.all; -use work.cts_components.all; -library SC; -use SC.COMPONENTS.all; +--use IEEE.STD_LOGIC_ARITH.ALL; use ieee.std_logic_arith.all; + entity cts_fpga1_test is generic( RW_REGISTERS_NUMBER : integer range 0 to 26 := 26; @@ -253,7 +246,7 @@ begin - GENERATE_SIGNALS: for i in 0 to 32 generate + GENERATE_SIGNALS: for i in 0 to 31 generate --registers are organized in a way that there is 8 bits forseen for each cnfiguration --each register has 32 bit @@ -272,8 +265,8 @@ begin port map ( clock => CLK_200_IN, en_clk => '1', - -- signal_in => hit_cntr(conv_integer(rw_register_i(i/4)(((i mod 4)+1)*8-1 downto (i mod 4)*8))), - signal_in => hit_cntr(4), + signal_in => hit_cntr(conv_integer (rw_register_i(i/4) ( (((i mod 4)+1)*8-1) downto (i mod 4)*8))), + -- signal_in => hit_cntr(4), pulse => start_pulses(i)); start_pulses_in_array(i)(0) <= start_pulses(i); @@ -287,7 +280,7 @@ begin port map ( RESET => reset_i_100, CLK => CLK_200_IN, - DELAY_IN => rw_register_i(i/4+8)(((i mod 4)+1)*8-1 downto (i mod 4)*8), + DELAY_IN => rw_register_i(i/4+8)( (((i mod 4)+1)*8-1) downto (i mod 4)*8), DELAY_VECTOR_IN => start_pulses_in_array(i), DELAY_VECTOR_OUT => start_pulses_out_array(i)); --for each pulse you can set the width @@ -297,8 +290,8 @@ begin port map ( RESET => reset_i_100, CLK => CLK_200_IN, - SIGNAL_WIDTH => rw_register_i(i/4+16)(((i mod 4)+1)*8-1 downto (i mod 4)*8), - SIGNAL_IN => start_pulses_out_array(i/4)(0), + SIGNAL_WIDTH => rw_register_i(i/4+16)( (((i mod 4)+1)*8-1) downto (i mod 4)*8), + SIGNAL_IN => start_pulses_out_array(i)(0), SIGNAL_OUT => start_out_buf(i)); @@ -314,8 +307,8 @@ begin port map ( clock => CLK_200_IN, en_clk => '1', - -- signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))), - signal_in => hit_cntr(8), + signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))), + -- signal_in => hit_cntr(8), pulse => beam_inhibit_pulse); BEAM_INHIBIT_SET_WIDTH: cts_fpga1_test_set_width diff --git a/cts_simulation_tb.mpf b/cts_simulation_tb.mpf index d40da45..a1aab4a 100644 --- a/cts_simulation_tb.mpf +++ b/cts_simulation_tb.mpf @@ -1819,7 +1819,7 @@ Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_135 = /home/marek/ctsaddon/simulation/cts_set_width.vhd -Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 133 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_136 = /home/marek/trbnet/trb_net16_addresses.vhd Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_137 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd diff --git a/version.vhd b/version.vhd index 913b9c2..0bfb352 100644 --- a/version.vhd +++ b/version.vhd @@ -8,6 +8,6 @@ use ieee.numeric_std.all; package version is - constant VERSION_NUMBER_TIME : integer := 1325773800; + constant VERSION_NUMBER_TIME : integer := 1326799917; end package version; -- 2.43.0