From 09703d1fa42ab150582a101bc66896ab00a2669e Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Mon, 26 Nov 2018 15:33:15 +0100 Subject: [PATCH] added Hub with CTS for mRICH --- hub_cts/code/mbs_vulom_recv.vhd | 428 +++++++++++ hub_cts/compile.pl | 1 + hub_cts/config.vhd | 221 ++++++ hub_cts/config_compile_frankfurt.pl | 21 + hub_cts/config_compile_gsi.pl | 20 + hub_cts/par.p2t | 31 + hub_cts/trb3sc_hubcts.lpf | 114 +++ hub_cts/trb3sc_hubcts.prj | 320 ++++++++ hub_cts/trb3sc_hubcts.vhd | 1079 +++++++++++++++++++++++++++ 9 files changed, 2235 insertions(+) create mode 100644 hub_cts/code/mbs_vulom_recv.vhd create mode 120000 hub_cts/compile.pl create mode 100644 hub_cts/config.vhd create mode 100644 hub_cts/config_compile_frankfurt.pl create mode 100644 hub_cts/config_compile_gsi.pl create mode 100644 hub_cts/par.p2t create mode 100644 hub_cts/trb3sc_hubcts.lpf create mode 100644 hub_cts/trb3sc_hubcts.prj create mode 100644 hub_cts/trb3sc_hubcts.vhd diff --git a/hub_cts/code/mbs_vulom_recv.vhd b/hub_cts/code/mbs_vulom_recv.vhd new file mode 100644 index 0000000..7eabe3f --- /dev/null +++ b/hub_cts/code/mbs_vulom_recv.vhd @@ -0,0 +1,428 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + + +entity mbs_recv is + generic ( + INCL_RDO_TIMESTAMP : integer range c_NO to c_YES := c_NO; -- will yield an unexpected rdo length (2 words instead the signalled 1 word) + -- if used as an ETM for the CTS + INCL_REGIO : integer range c_NO to c_YES := c_NO; + USE_40MHz : integer range c_NO to c_YES := c_YES + ); + port( + CLK : in std_logic; -- e.g. 100 MHz + RESET_IN : in std_logic; -- could be used after busy_release to make sure entity is in correct state + + --Module inputs + MBS_IN : in std_logic; -- raw input + CLK_200 : in std_logic; -- internal sampling clock + + --trigger outputs + TRG_ASYNC_OUT : out std_logic; -- asynchronous rising edge, length varying, here: approx. 110 ns + TRG_SYNC_OUT : out std_logic; -- sync. to CLK + + --data output for read-out + TRIGGER_IN : in std_logic; + TRG_NUMBER_IN : in std_logic_vector (15 downto 0); + TRG_CODE_IN : in std_logic_vector (7 downto 0); + TIMING_TRG_IN : in std_logic := '0'; + + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_OUT : out std_logic; + STATUSBIT_OUT: out std_logic_vector(31 downto 0) := (others => '0'); + FINISHED_OUT : out std_logic; + + --Registers / Debug + REGIO_IN : in CTRLBUS_RX := (data => x"00000000", addr => x"0000", others => '0'); + REGIO_OUT : out CTRLBUS_TX; + + + -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode) + CONTROL_REG_IN : in std_logic_vector(31 downto 0); + STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0'); + HEADER_REG_OUT : out std_logic_vector(1 downto 0); + DEBUG : out std_logic_vector(31 downto 0) + ); + + attribute syn_useioff : boolean; + --no IO-FF for MBS input + attribute syn_useioff of MBS_IN : signal is false; +end entity; + +--MBS format +--Startbit (0): “0“ +--Preamb. (1): “1010“ +--Trig.nr. (2) :24bit +--Status (3): unused (2 bits) +--Paritybit (4): “0“ or “1“ (positive?) +--Postam. (5):“1010“ +--Stopbit (0): “1“ +--Parity check over counter & status bit + +--Data Format: +-- Bit 23 - 0 : Trigger Number +-- Bit 30 - 29 : Status +-- Bit 31 : Error flag + +--statusbit 23 will be set in case of a data error from MBS + +architecture mbs_recv_arch of mbs_recv is + + + signal bitcnt : integer range 0 to 37; + signal shift_reg : std_logic_vector(36 downto 0); + + signal first_bits_fast : std_logic; + signal first_bits_slow : std_logic; + signal reg_MBS_IN : std_logic; + signal reg_MBS_DELAY : std_logic; + signal done : std_logic; + signal done_slow : std_logic; + + signal number_reg : std_logic_vector(23 downto 0); + signal status_reg : std_logic_vector(1 downto 0); + signal error_reg : std_logic; + + signal trg_async : std_logic; + signal trg_sync : std_logic; + signal trg_sync200 : std_logic; + + type state_t is (IDLE, WAIT1,WAIT2,WAIT3,WAIT4,WAIT5, FINISH); + signal state : state_t; + + type rdo_state_t is (RDO_IDLE, RDO_WAIT, RDO_WRITE, RDO_TIMESTAMP, RDO_LVL1_ID, RDO_FINISH); + signal rdostate : rdo_state_t; + + signal config_rdo_disable_i : std_logic; + signal config_invert_input_i : std_logic; + + signal rec_counter_i : unsigned(31 downto 0) := (others => '0'); + signal act_counter_i : unsigned(31 downto 0) := (others => '0'); + signal high_counter_i : unsigned(31 downto 0) := (others => '0'); + +-- timestamp + signal timing_trg_i : std_logic; + signal lvl1_trg_i : std_logic; + + signal timestamp_i : unsigned(31 downto 0); -- time since last timing trigger with lvl1 received (200 MHz) + signal timestamp_fresh_i : unsigned(31 downto 0); -- time since last timing trigger (200 MHz) + signal lvl1_id_i : std_logic_vector(23 downto 0); -- TRG-NUM + CODE + + signal rec_timestamp_i : std_logic_vector(31 downto 0); -- time trg_sync200 was asserted + signal rec_lvl1_id_i : std_logic_vector(23 downto 0); -- lvl1 info for timestamp + + signal rdo_buf_rec_timestamp_i : std_logic_vector(31 downto 0); -- read-out buffer for the above + signal rdo_buf_rec_lvl1_id_i : std_logic_vector(23 downto 0); -- read-out buffer for the above + + signal trig_async_cond,trig_async_cond_0 : std_logic; +begin + HEADER_REG_OUT <= b"01"; -- we tell the CTS that we send one word of over DATA_OUT + + reg_MBS_IN <= MBS_IN xor config_invert_input_i when rising_edge(CLK_200); + reg_MBS_DELAY <= reg_MBS_IN when rising_edge(CLK_200); + + PROC_FIRST_BITS : process begin + wait until rising_edge(CLK_200); + if bitcnt > 32 and RESET_IN = '0' then + first_bits_fast <= '1'; + else + first_bits_fast <= '0'; + end if; + end process; + + first_bits_slow <= first_bits_fast when rising_edge(CLK); + trig_async_cond_0 <= '1' when (bitcnt = 37) else '0'; + trig_async_cond <= (trig_async_cond_0 and (not MBS_IN)) or trig_async_cond; + + trg_async <= (not MBS_IN or trg_async) when trig_async_cond = '1' else '0'; + trg_sync <= (not reg_MBS_IN or trg_sync) and first_bits_slow when rising_edge(CLK); + + TRG_ASYNC_OUT <= trg_async; + TRG_SYNC_OUT <= trg_sync when rising_edge(CLK); + + PROC_FSM: process begin + wait until rising_edge(CLK_200); + + case state is + when IDLE => + bitcnt <= 37; + done <= '1'; + if reg_MBS_IN = '0' then + done <= '0'; + state <= WAIT1; + end if; + + when WAIT1 => + state <= WAIT2; + + when WAIT2 => + bitcnt <= bitcnt - 1; + shift_reg <= shift_reg(shift_reg'high - 1 downto 0) & reg_MBS_IN; + state <= WAIT3; + + when WAIT3 => + if bitcnt = 0 then + state <= FINISH; + else + if USE_40MHz = c_YES then + state <= WAIT4; + else --run with 50MHz + state <= WAIT5; + end if; + end if; + + when WAIT4 => + state <= WAIT5; + + when WAIT5 => + state <= WAIT1; + + when FINISH => + if reg_MBS_IN = '1' then + state <= IDLE; + end if; + done <= '1'; + end case; + if RESET_IN = '1' then + state <= IDLE; + done <= '0'; + end if; + end process; + + done_slow <= done when rising_edge(CLK); + + PROC_REG_INFO : process begin + wait until rising_edge(CLK); + if done_slow = '1' then + number_reg <= shift_reg(31 downto 8); + status_reg <= shift_reg(7 downto 6); + + if shift_reg(36 downto 32) = "01010" and shift_reg(4 downto 0) = "10101" and xor_all(shift_reg(31 downto 5)) = '0' then + error_reg <= '0'; + else + error_reg <= '1'; + end if; + end if; + end process; + + + PROC_RDO : process + variable incl_timestamp_v : std_logic; + begin + wait until rising_edge(CLK); + WRITE_OUT <= '0'; + FINISHED_OUT <= config_rdo_disable_i; + incl_timestamp_v := '0'; + case rdostate is + when RDO_IDLE => + if TRIGGER_IN = '1' and config_rdo_disable_i = '0' then + if done_slow = '0' then + rdostate <= RDO_WAIT; + else + rdostate <= RDO_WRITE; + end if; + end if; + when RDO_WAIT => + if done_slow = '1' then + rdostate <= RDO_WRITE; + end if; + + when RDO_WRITE => + if INCL_RDO_TIMESTAMP=c_YES then + rdostate <= RDO_TIMESTAMP; + incl_timestamp_v := '1'; + else + rdostate <= RDO_FINISH; + end if; + + DATA_OUT <= error_reg & status_reg & "0000" & incl_timestamp_v & number_reg; + WRITE_OUT <= '1'; + + when RDO_TIMESTAMP => + DATA_OUT <= rdo_buf_rec_timestamp_i; + WRITE_OUT <= '1'; + rdostate <= RDO_LVL1_ID; + + when RDO_LVL1_ID => + DATA_OUT <= x"00" & rdo_buf_rec_lvl1_id_i; + WRITE_OUT <= '1'; + rdostate <= RDO_FINISH; + + when RDO_FINISH => + FINISHED_OUT <= '1'; + rdostate <= RDO_IDLE; + end case; + end process; + + STATUSBIT_OUT(23) <= error_reg when rising_edge(CLK); + STATUS_REG_OUT <= error_reg & MBS_IN & "000000" & number_reg; + DEBUG <= x"00000000"; -- & done & '0' & shift_reg(13 downto 0); + + + -- when timing trigger arives first we reset a temporary timestamp, that will + -- be not used until we know the corresponding lvl1 id ... + PROC_TIME_BASE: process is + variable timing_trg_delay : std_logic; + variable lvl1_trg_delay : std_logic; + begin + wait until rising_edge(CLK_200); + + timestamp_fresh_i <= timestamp_fresh_i + 1; + if timing_trg_i='1' and timing_trg_delay='0' then + timestamp_fresh_i <= (others => '0'); + end if; + + timestamp_i <= timestamp_i + 1; + if lvl1_trg_i='1' and lvl1_trg_delay='0' then + timestamp_i <= timestamp_fresh_i + 1; + lvl1_id_i <= TRG_CODE_IN & TRG_NUMBER_IN; -- no sync necessary, as signal should be stable until now + end if; + + lvl1_trg_delay := lvl1_trg_i; + timing_trg_delay := timing_trg_i; + end process; + + + PROC_TIMESTAMP_EVENT: process is + variable trg_sync200_delay : std_logic; + variable lvl1_trg_delay : std_logic; + begin + wait until rising_edge(CLK_200); + + if trg_sync200='1' and trg_sync200_delay='0' then + rec_timestamp_i <= timestamp_i; + rec_lvl1_id_i <= lvl1_id_i; + end if; + + if lvl1_trg_i='1' and lvl1_trg_delay='0' then + rdo_buf_rec_timestamp_i <= rec_timestamp_i; + rdo_buf_rec_lvl1_id_i <= rec_lvl1_id_i; + end if; + + lvl1_trg_delay := lvl1_trg_i; + trg_sync200_delay := trg_sync200; + end process; + + -- SYNC EXTERNAL SIGNALS FOR TIMESTAMPING + THE_TMG_TRG_SYNC: signal_sync + generic map (WIDTH => 1, DEPTH => 3) + port map ( + RESET => RESET_IN, + CLK0 => CLK, + CLK1 => CLK_200, + D_IN(0) => TIMING_TRG_IN, + D_OUT(0) => timing_trg_i + ); + + THE_LVL1_SYNC: signal_sync + generic map (WIDTH => 1, DEPTH => 3) + port map ( + RESET => RESET_IN, + CLK0 => CLK, + CLK1 => CLK_200, + D_IN(0) => TRIGGER_IN, + D_OUT(0) => lvl1_trg_i + ); + + THE_REC_SYNC: signal_sync + generic map (WIDTH => 1, DEPTH => 3) + port map ( + RESET => RESET_IN, + CLK0 => CLK_200, + CLK1 => CLK_200, + D_IN(0) => trg_async, + D_OUT(0) => trg_sync200 + ); + +-- REGIO + GEN_REGIO: if INCL_REGIO = c_YES generate + proc_regio: process is + variable addr : integer range 0 to 3; + begin + wait until rising_edge(CLK); + + addr := to_integer(UNSIGNED(REGIO_IN.addr(1 downto 0))); + REGIO_OUT.rack <= REGIO_IN.read; + REGIO_OUT.wack <= REGIO_IN.write; + REGIO_OUT.nack <= '0'; + REGIO_OUT.unknown <= '0'; + REGIO_OUT.data <= (others => '0'); + + case addr is + when 0 => + REGIO_OUT.data(1 downto 0) <= config_invert_input_i & (not config_rdo_disable_i); + if INCL_RDO_TIMESTAMP=c_YES then + REGIO_OUT.data(2) <= '1'; + end if; + REGIO_OUT.data(7) <= error_reg; + REGIO_OUT.data(31 downto 8) <= number_reg; + + when 1 => + REGIO_OUT.data <= std_logic_vector(rec_counter_i); + + when 2 => + REGIO_OUT.data <= std_logic_vector(act_counter_i); + + when 3 => + REGIO_OUT.data <= std_logic_vector(high_counter_i); + + end case; + + if REGIO_IN.write='1' then + if addr=0 then + config_rdo_disable_i <= not REGIO_IN.data(0); + config_invert_input_i <= REGIO_IN.data(1); + else + REGIO_OUT.unknown <= '1'; + end if; + end if; + + if RESET_IN = '1' then + config_rdo_disable_i <= '0'; + config_invert_input_i <= '0'; + end if; + end process; + + proc_stats: process is + variable this_mbs : std_logic; + variable last_mbs : std_logic; + variable last_trg_sync : std_logic; + begin + wait until rising_edge(CLK); + + this_mbs := reg_MBS_IN or reg_MBS_DELAY; + + if this_mbs = '1' then + high_counter_i <= high_counter_i + 1; + end if; + + if trg_sync = '1' and last_trg_sync='0' then + rec_counter_i <= rec_counter_i + 1; + end if; + + if this_mbs /= last_mbs then + act_counter_i <= act_counter_i + 1; + end if; + + if RESET_IN='1' then + high_counter_i <= (others => '0'); + rec_counter_i <= (others => '0'); + act_counter_i <= (others => '0'); + end if; + + last_trg_sync := trg_sync; + last_mbs := this_mbs; + end process; + end generate; + + GEN_NO_REGIO: if INCL_REGIO /= c_YES generate + config_rdo_disable_i <= CONTROL_REG_IN(0); + REGIO_OUT.unknown <= REGIO_IN.read or REGIO_IN.write; + end generate; +end architecture; diff --git a/hub_cts/compile.pl b/hub_cts/compile.pl new file mode 120000 index 0000000..4456748 --- /dev/null +++ b/hub_cts/compile.pl @@ -0,0 +1 @@ +../scripts/compile.pl \ No newline at end of file diff --git a/hub_cts/config.vhd b/hub_cts/config.vhd new file mode 100644 index 0000000..aecb74a --- /dev/null +++ b/hub_cts/config.vhd @@ -0,0 +1,221 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--design options: backplane or front SFP, with or without GBE + constant USE_BACKPLANE : integer := c_NO; + constant USE_ADDON : integer := c_YES; + constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3C0"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62"; --62 for SFP, 63 for backplane + + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + + --input monitor and trigger generation logic + constant INCLUDE_TDC : integer := c_YES; + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 32; + + + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + constant PINOUT : integer := 2; + -- 0: KEL on board + -- 1: Canadian + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 1023; --maximum event size. Should not exceed + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 1; + constant TRIGGER_PULSER_COUNT : integer := 3; + constant TRIGGER_RAND_PULSER : integer := 1; + constant TRIGGER_ADDON_COUNT : integer := 2; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 18; + constant CTS_OUTPUT_MULTIPLEXERS : integer := 1; +--TODO: + -- constant INCLUDE_MBS_REC : integer range c_NO to c_YES := c_NO; + --Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + --constant ETM_ID : std_logic_vector(7 downto 0); + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"48", x"75", x"62", x"41", x"64", x"64", x"4f", x"6e", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + others => x"00"); + + + type hub_mii_t is array(0 to 3) of integer; + type hub_ct is array(0 to 16) of integer; + type hub_cfg_t is array(0 to 3) of hub_ct; + type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0); + type intlist_t is array(0 to 7) of integer; +-- 0 opt. link opt. link +-- 1-8 SFP 1-4 +-- 1(9) CTS read-out internal 0 1 - X X O --downlink only +-- 2(10) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only + + --Order: + -- no backplane, no AddOn, 1x SFP, 1x GBE + -- no backplane, 4x AddOn, 1x SFP, 1x GBE +-- -- -- -- no backplane, 8x AddOn, 1x SFP, 1x GBE + -- backplane, 9x backplane, 1x GBE + constant SFP_NUM_ARR : hub_mii_t := (1,8,0,0); + constant INTERFACE_NUM_ARR : hub_mii_t := (1,8,9,10); +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), +-- (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0), +-- (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), +-- (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); + + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct; + constant IS_DOWNLINK : hub_ct; + constant IS_UPLINK_ONLY : hub_ct; + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_ETM; --for TDC + + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + constant CFG_MODE : integer := USE_ADDON;--*2 + USE_BACKPLANE; + + constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); + constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); + constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); + constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(3 downto 0) := std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15 downto 15) := std_logic_vector(to_unsigned(INCLUDE_TDC,1)); --TDC + t(16 downto 16) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --data via GbE + t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE + t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); + t(26 downto 24) := std_logic_vector(to_unsigned(SFP_NUM_ARR(CFG_MODE),3)); --num SFPs with TrbNet + t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/hub_cts/config_compile_frankfurt.pl b/hub_cts/config_compile_frankfurt.pl new file mode 100644 index 0000000..01ea7d8 --- /dev/null +++ b/hub_cts/config_compile_frankfurt.pl @@ -0,0 +1,21 @@ +TOPNAME => "trb3sc_cts", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodes_cts_frankfurt.txt', +pinout_file => 'trb3sc_hub', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 1, +include_GBE => 1, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, + diff --git a/hub_cts/config_compile_gsi.pl b/hub_cts/config_compile_gsi.pl new file mode 100644 index 0000000..5929040 --- /dev/null +++ b/hub_cts/config_compile_gsi.pl @@ -0,0 +1,20 @@ +TOPNAME => "trb3sc_hubcts", +lm_license_file_for_synplify => "27000\@lxcad03.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.4_x64/', +synplify_path => '/opt/synplicity/J-2014.09-SP2', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => 'nodes_gsi_template.txt', +pinout_file => 'trb3sc_hub', + +firefox_open => 0, + + +#pinout_file => 'trb3sc_richSensor', + +include_TDC => 1, +include_GBE => 1, + +twr_number_of_errors => 20, diff --git a/hub_cts/par.p2t b/hub_cts/par.p2t new file mode 100644 index 0000000..2be9006 --- /dev/null +++ b/hub_cts/par.p2t @@ -0,0 +1,31 @@ +# -w +# -i 15 +# -l 5 +# -y +# -s 12 +# -t 26 +# -c 1 +# -e 2 +# #-g guidefile.ncd +# #-m nodelist.txt +# # -w +# # -i 6 +# # -l 5 +# # -n 1 +# # -t 1 +# # -s 1 +# # -c 0 +# # -e 0 +# # +# +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 3 +-c 0 +-e 0 +-i 6 +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:parHold=ON:parHoldLimit=10000:parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1:parHold=2 diff --git a/hub_cts/trb3sc_hubcts.lpf b/hub_cts/trb3sc_hubcts.lpf new file mode 100644 index 0000000..70d4b84 --- /dev/null +++ b/hub_cts/trb3sc_hubcts.lpf @@ -0,0 +1,114 @@ +# LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ; +# LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ; +# LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ; +# LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC" ; +# LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ; + +LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC"; +LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; + +BLOCK PATH FROM CELL THE_TDC/calibration_o*; +BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; + +REGION "MEDIA_DOWN1" "R102C40D" 13 100; +#LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; + + +FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; + +#MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns; +#MULTICYCLE FROM CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns; +#MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i"; +#BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i"; +#BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i"; +#BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i"; +# +MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; +# +MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; +#MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +#MULTICYCLE FROM CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +#MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i"; +#BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i"; +#BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i"; +#BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i"; +# +#MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/sci*" 20 ns; +#MULTICYCLE FROM CELL "THE_MEDIA_4_PCSC/sci*" 20 ns; +#MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_write_i"; +#BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_write_i"; +#BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_read_i"; +#BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_read_i"; +# +#MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns; +#MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns; +#MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i"; +#BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i"; +#BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i"; +#BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i"; + + +#MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +# +MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +# +MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +#MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +# +#MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +# +#MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + + + +# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ; +# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps +# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps diff --git a/hub_cts/trb3sc_hubcts.prj b/hub_cts/trb3sc_hubcts.prj new file mode 100644 index 0000000..436e2be --- /dev/null +++ b/hub_cts/trb3sc_hubcts.prj @@ -0,0 +1,320 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_hubcts" +set_option -resource_sharing false + +# map options +set_option -frequency 100 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_hubcts.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" + +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" + + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/m26_sensor_etm.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd" +add_file -vhdl -lib work "./code/mbs_vulom_recv.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" + +#TDC +add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd" +# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" + + +# TDC online calibration +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/Calibration.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/Cal_Limits_v2.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/cnt_val.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/default_val.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/LUT.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/Memory.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/Memory_curr.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/read_cnt.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/compare_old.vhd" +add_file -vhdl -lib work "../../dirich/combiner_calib/code_EBR/Calc_output.vhd" + +add_file -vhdl -lib work "../../dirich/combiner_calib/core/RAM_pseudo_DP_wReg_36x1k.vhd" + + +add_file -vhdl -lib work "./trb3sc_hubcts.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/hub_cts/trb3sc_hubcts.vhd b/hub_cts/trb3sc_hubcts.vhd new file mode 100644 index 0000000..38b875c --- /dev/null +++ b/hub_cts/trb3sc_hubcts.vhd @@ -0,0 +1,1079 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; +use work.cts_pkg.all; + +entity trb3sc_hubcts is + port( + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + + --Additional IO + HDR_IO : inout std_logic_vector(10 downto 1); + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_GPIO : inout std_logic_vector( 3 downto 0); + + SPARE_IN : in std_logic_vector( 1 downto 0); + INP : in std_logic_vector(95 downto 64); + RJ_IO : out std_logic_vector( 3 downto 0); --0, inner RJ trigger output + + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + + LED_HUB_LINKOK : out std_logic_vector(8 downto 1); + LED_HUB_RX : out std_logic_vector(8 downto 1); + LED_HUB_TX : out std_logic_vector(8 downto 1); + HUB_MOD0 : in std_logic_vector(8 downto 1); + HUB_MOD1 : inout std_logic_vector(8 downto 1); + HUB_MOD2 : inout std_logic_vector(8 downto 1); + HUB_TXDIS : out std_logic_vector(8 downto 1); + HUB_LOS : in std_logic_vector(8 downto 1); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --SPI + DAC_OUT_SDO : out std_logic_vector(6 downto 5); + DAC_OUT_SCK : out std_logic_vector(6 downto 5); + DAC_OUT_CS : out std_logic_vector(6 downto 5); + DAC_IN_SDI : in std_logic_vector(6 downto 5); + + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + + attribute syn_useioff of SPARE_IN : signal is false; + attribute syn_useioff of INP : signal is false; + +end entity; + +architecture trb3sc_arch of trb3sc_hubcts is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + +-- constant CTS_ADDON_LINE_COUNT : integer := 18; +-- constant CTS_OUTPUT_MULTIPLEXERS : integer := 1; +-- constant CTS_OUTPUT_INPUTS : integer := 16; + + + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal do_reboot_i, reboot_from_gbe : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to INTERFACE_NUM-1); + signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); + + signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, buscts_rx, + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx,bustdccal_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, buscts_tx, + bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx,bustdccal_tx : CTRLBUS_TX; + + signal sed_error_i : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal uart_tx, uart_rx : std_logic; + + signal common_ctrl_reg : std_logic_vector (std_COMCTRLREG*32-1 downto 0); + + signal timer : TIMERS; + signal reset_via_gbe : std_logic := '0'; + + signal med_dataready_out : std_logic_vector (8-1 downto 0); + signal med_data_out : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (8-1 downto 0); + signal med_dataready_in : std_logic_vector (8-1 downto 0); + signal med_data_in : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (8-1 downto 0); + signal med_stat_op : std_logic_vector (8*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (8*16-1 downto 0); + signal rdack, wrack : std_logic; + + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + signal cts_ext_trigger : std_logic; + signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_ext_control : std_logic_vector(31 downto 0); + signal cts_ext_debug : std_logic_vector(31 downto 0); + signal cts_ext_header : std_logic_vector(1 downto 0); + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + signal cts_rdo_additional_TDCcal : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); +-- signal cts_addon_activity_i, +-- cts_addon_selected_i : std_logic_vector(6 downto 0); + +-- signal cts_periph_trigger_i : std_logic_vector(19 downto 0); +-- signal cts_output_multiplexers_i : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS - 1 downto 0); + +-- signal cts_periph_lines_i : std_logic_vector(CTS_OUTPUT_INPUTS - 1 downto 0); + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + + signal hit_in_i : std_logic_vector(64 downto 1); + + signal async_ext_trig : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci1_rx : signal is true; + attribute syn_preserve of bussci1_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + +begin + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => '0', + NET_CLK_HALF_IN => '0', + RESET_FROM_NET => make_reset, + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + + make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + + pll_calibration : entity work.pll_in125_out33 + port map ( + CLK => CLK_SUPPL_PCLK, + CLKOP => clk_cal, + LOCK => open); + +--------------------------------------------------------------------------- +-- PCSA +--------------------------------------------------------------------------- +bussci1_tx.data <= (others => '0'); +bussci1_tx.ack <= '0'; +bussci1_tx.nack <= '0'; +bussci1_tx.unknown <= '1'; + + +--------------------------------------------------------------------------- +-- PCSB Downlink without backplane is SFP +--------------------------------------------------------------------------- +-- gen_PCSB : if USE_BACKPLANE = c_NO generate +-- THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync +-- generic map( +-- SERDES_NUM => 3, +-- IS_SYNC_SLAVE => c_NO +-- ) +-- port map( +-- CLK_REF_FULL => clk_full_osc, +-- CLK_INTERNAL_FULL => clk_full_osc, +-- SYSCLK => clk_sys, +-- RESET => reset_i, +-- CLEAR => clear_i, +-- --Internal Connection +-- MEDIA_MED2INT => med2int(0), +-- MEDIA_INT2MED => int2med(0), +-- +-- --Sync operation +-- RX_DLM => open, +-- RX_DLM_WORD => open, +-- TX_DLM => open, +-- TX_DLM_WORD => open, +-- +-- --SFP Connection +-- SD_PRSNT_N_IN => SFP_MOD0(1), +-- SD_LOS_IN => SFP_LOS(1), +-- SD_TXDIS_OUT => SFP_TX_DIS(1), +-- --Control Interface +-- BUS_RX => bussci2_rx, +-- BUS_TX => bussci2_tx, +-- -- Status and control port +-- STAT_DEBUG => open, +-- CTRL_DEBUG => open +-- ); +-- end generate; + +--------------------------------------------------------------------------- +-- PCSB 4 downlinks +--------------------------------------------------------------------------- +-- bussci3_tx.data <= (others => '0'); +-- bussci3_tx.ack <= '0'; +-- bussci3_tx.nack <= '0'; +-- bussci3_tx.unknown <= '1'; +gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate + THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(5), + MEDIA_MED2INT(1) => med2int(6), + MEDIA_MED2INT(2) => med2int(7), + MEDIA_MED2INT(3) => med2int(0), + MEDIA_INT2MED(0) => int2med(5), + MEDIA_INT2MED(1) => int2med(6), + MEDIA_INT2MED(2) => int2med(7), + MEDIA_INT2MED(3) => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + +--------------------------------------------------------------------------- +-- PCSC 4 downlinks +--------------------------------------------------------------------------- +-- bussci3_tx.data <= (others => '0'); +-- bussci3_tx.ack <= '0'; +-- bussci3_tx.nack <= '0'; +-- bussci3_tx.unknown <= '1'; +gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate + THE_MEDIA_PCSC : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(3), + MEDIA_MED2INT(1) => med2int(4), + MEDIA_MED2INT(2) => med2int(1), + MEDIA_MED2INT(3) => med2int(2), + MEDIA_INT2MED(0) => int2med(3), + MEDIA_INT2MED(1) => int2med(4), + MEDIA_INT2MED(2) => int2med(1), + MEDIA_INT2MED(3) => int2med(2), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(3), + SD_PRSNT_N_IN(1) => HUB_MOD0(4), + SD_PRSNT_N_IN(2) => HUB_MOD0(1), + SD_PRSNT_N_IN(3) => HUB_MOD0(2), + + SD_LOS_IN(0) => HUB_LOS(3), + SD_LOS_IN(1) => HUB_LOS(4), + SD_LOS_IN(2) => HUB_LOS(1), + SD_LOS_IN(3) => HUB_LOS(2), + + SD_TXDIS_OUT(0) => HUB_TXDIS(3), + SD_TXDIS_OUT(1) => HUB_TXDIS(4), + SD_TXDIS_OUT(2) => HUB_TXDIS(1), + SD_TXDIS_OUT(3) => HUB_TXDIS(2), + + --Control Interface + BUS_RX => bussci3_rx, + BUS_TX => bussci3_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + + +--------------------------------------------------------------------------- +-- GbE (PCSD) +--------------------------------------------------------------------------- + GBE : entity work.gbe_wrapper + generic map( + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 4, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" + ) + + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_SUPPL_PCLK, + RESET => reset_i, + GSR_N => GSR_N, + + TRIGGER_IN => cts_rdo_rx.data_valid, + + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_LOS_IN(0) => SFP_LOS(0), + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + + MAKE_RESET_OUT => reset_via_gbe, + + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => x"F3C0", + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => 100, + USE_ONEWIRE => c_YES, + BROADCAST_SPECIAL_ADDR => x"35", + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_IN => open, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_gbe, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + + end generate; + + gen_media_record : for i in 0 to INTERFACE_NUM-1 generate + med_data_in(i*16+15 downto i*16) <= med2int(i).data; + med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; + med_dataready_in(i) <= med2int(i).dataready; + med_read_in(i) <= med2int(i).tx_read; + med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op; + + int2med(i).data <= med_data_out(i*16+15 downto i*16); + int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); + int2med(i).dataready <= med_dataready_out(i); + int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); + end generate; + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + +--------------------------------------------------------------------------- +-- CTS +--------------------------------------------------------------------------- + THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 2, + ADDON_GROUP_UPPER => (1,17, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => cts_ext_trigger,--'0', + EXT_STATUS_IN => cts_ext_status,--(others => '0'), + EXT_CONTROL_OUT => cts_ext_control,--open, + EXT_HEADER_BITS_IN => cts_ext_header,--(others => '0'), + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => open, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + + cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); + cts_addon_triggers_in(17 downto 2) <= INP(79 downto 64); + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + +--------------------------------------------------------------------------- +-- Add timestamp generator +--------------------------------------------------------------------------- + GEN_TIMESTAMP : if INCLUDE_TIMESTAMP_GENERATOR = c_YES generate + THE_TIMESTAMP : entity work.timestamp_generator + port map( + CLK => clk_sys, + RESET_IN => reset_i, + + TIMER_CLOCK_IN => INP(80), + TIMER_RESET_IN => INP(81), + + TRIGGER_IN => cts_trigger_out, + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(0) + ); + end generate; + + GEN_MBS : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM and INCLUDE_ETM = c_YES generate + THE_MBS : entity work.mbs_recv + port map ( + CLK => clk_sys, + RESET_IN => reset_i, + + MBS_IN => SPARE_IN(0),--CLK_EXT(3), + CLK_200 => clk_full_osc, + + TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1), + TRG_SYNC_OUT => cts_ext_trigger, + + TRIGGER_IN => cts_rdo_rx.data_valid, + TRG_NUMBER_IN => cts_trg_number, + TRG_CODE_IN => cts_trg_code, + TIMING_TRG_IN => cts_trigger_out, + + DATA_OUT => cts_rdo_additional(0).data, + WRITE_OUT => cts_rdo_additional(0).data_write, + FINISHED_OUT => cts_rdo_additional(0).data_finished, + STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + + CONTROL_REG_IN => cts_ext_control, + STATUS_REG_OUT => cts_ext_status, + HEADER_REG_OUT => cts_ext_header, + + DEBUG => cts_ext_debug + ); + end generate; + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 10, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", 9 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, 9 => 12 , others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => handlerbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bustc_rx, --Clock switch + BUS_RX(2) => bussci1_rx, --SCI Serdes + BUS_RX(3) => bussci2_rx, + BUS_RX(4) => bussci3_rx, + BUS_RX(5) => busgbeip_rx, + BUS_RX(6) => busgbereg_rx, + BUS_RX(7) => buscts_rx, + BUS_RX(8) => bustdc_rx, + BUS_RX(9) => bustdccal_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bustc_tx, + BUS_TX(2) => bussci1_tx, + BUS_TX(3) => bussci2_tx, + BUS_TX(4) => bussci3_tx, + BUS_TX(5) => busgbeip_tx, + BUS_TX(6) => busgbereg_tx, + BUS_TX(7) => buscts_tx, + BUS_TX(8) => bustdc_tx, + BUS_TX(9) => bustdccal_tx, + STAT_DEBUG => open + ); + + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => do_reboot_i, + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + --LCD + LCD_DATA_IN => open, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i, + TRIG_GEN_INPUTS => open, + TRIG_GEN_OUTPUTS => open, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + +gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate + do_reboot_i <= common_ctrl_reg(15); +end generate; +gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate + do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; +end generate; + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5); + DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4); + DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4); + DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4); + spi_miso(3 downto 0) <= (others => '0'); + spi_miso(15 downto 7) <= (others => '0'); + + RJ_IO(0) <= cts_trigger_out; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + + +gen_leds_addon : if USE_ADDON = c_YES generate + gen_hub_leds : for i in 1 to 7 generate + LED_HUB_LINKOK(i) <= not med2int(i).stat_op(9); + LED_HUB_TX(i) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); + LED_HUB_RX(i) <= not (med2int(i).stat_op(11)); + end generate; +end generate; + +-- LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = 0 else +-- '1'; +-- LED_HUB_TX(8) <= not (med2int(7).stat_op(10) or not med2int(7).stat_op(9)) when INCLUDE_GBE = 0 else +-- '1'; +-- LED_HUB_RX(8) <= not (med2int(7).stat_op(11)) when INCLUDE_GBE = 0 else +-- + LED_SFP_GREEN(0) <= --not med2int(8).stat_op(9) when INCLUDE_GBE = 0 else + '1'; + LED_SFP_RED(0) <= --not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 0 else + '1'; + + LED_SFP_GREEN(1) <= not med2int(0).stat_op(9) when USE_BACKPLANE = 0 and USE_ADDON = 0 else + '1'; + LED_SFP_RED(1) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11) or not med2int(0).stat_op(9)) when USE_BACKPLANE = 0 and USE_ADDON = 0 else + '1'; + +-- LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else +-- not med2int(8).stat_op(9) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else +-- '1'; +-- LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else +-- not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else +-- '1'; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional_TDCcal(INCLUDE_ETM),--_TDCcal + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); + + THE_TDC_CAL : entity work.TDC_Calibration + generic map( + IS_COMBINER => c_NO, + USE_STAT_BITS => c_YES, + USE_DATA_WRITE => c_YES, + USE_DATA_FINISHED => c_YES, + USE_BUSY_RELEASE => c_YES + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + DIN => cts_rdo_additional_TDCcal(INCLUDE_ETM).data, + DIN_TYPE => x"4", + DIN_info(31 downto 0) => cts_rdo_additional_TDCcal(INCLUDE_ETM).statusbits, + DIN_info(32) => cts_rdo_additional_TDCcal(INCLUDE_ETM).busy_release, + DIN_info(33) => cts_rdo_additional_TDCcal(INCLUDE_ETM).data_write, + DIN_info(34) => cts_rdo_additional_TDCcal(INCLUDE_ETM).data_finished, + DIN_READY => '1', + DIN_STAT => (others=>'0'), + FPGA_in => timer.network_address, + TRIGG_TYPE => cts_rdo_rx.trg_type, + DOUT => cts_rdo_additional(INCLUDE_ETM).data, + DOUT_info(31 downto 0) => cts_rdo_additional(INCLUDE_ETM).statusbits, + DOUT_info(32) => cts_rdo_additional(INCLUDE_ETM).busy_release, + DOUT_info(33) => cts_rdo_additional(INCLUDE_ETM).data_write, + DOUT_info(34) => cts_rdo_additional(INCLUDE_ETM).data_finished, + DOUT_TYPE => open, + DOUT_READY => open, + DOUT_STAT => open, + BUS_RX => bustdccal_rx, + BUS_TX => bustdccal_tx + ); + + + -- For single edge measurements + gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 ) and (INCLUDE_ETM = c_NO) generate + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= SPARE_IN(NUM_TDC_CHANNELS-2 downto 0);--INP(NUM_TDC_CHANNELS-2+64 downto 64); + end generate; + + gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) and ((ETM_CHOICE = ETM_CHOICE_MBS_VULOM) and (INCLUDE_ETM = c_YES)) generate + hit_in_i(1) <= async_ext_trig;--INP(NUM_TDC_CHANNELS-2+64 downto 64); + hit_in_i(2) <= SPARE_IN(0); + end generate; + + + -- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 generate + Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate + hit_in_i(i*2+1) <= INP(i+64); + hit_in_i(i*2+2) <= not INP(i+64); + end generate Gen_Hit_In_Signals; + end generate; + + +end architecture; + + + -- 2.43.0