From 09f205bc2cb677c4a4d8cab3951aa0675726abb9 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 6 Jul 2018 11:31:36 +0200 Subject: [PATCH] this version builds successfully. Needs to be tested. --- base/trb3_periph_mupix8.lpf | 2 +- .../Mupix8/sources/DataMuxWithConversion.vhd | 73 ++++++++++++++++--- mupix/Mupix8/sources/DatasourceSelector.vhd | 6 +- ...FrameGenMux2.vhd => FrameGeneratorMux.vhd} | 9 ++- mupix/Mupix8/sources/MuPixDataLink_new.vhd | 14 ++-- mupix/Mupix8/sources/MupixBoard.vhd | 2 +- mupix/Mupix8/trb3_periph.prj | 2 +- 7 files changed, 80 insertions(+), 28 deletions(-) rename mupix/Mupix8/sources/{FrameGenMux2.vhd => FrameGeneratorMux.vhd} (98%) diff --git a/base/trb3_periph_mupix8.lpf b/base/trb3_periph_mupix8.lpf index 82b9d43..179ceb0 100644 --- a/base/trb3_periph_mupix8.lpf +++ b/base/trb3_periph_mupix8.lpf @@ -112,7 +112,7 @@ IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; ################################################################# #MuPix 8 ################################################################# -LOCATE COMP "MupixBoard8_0/mupix_data_link/the_mupix_serdes/PCSD_INST" SITE "PCSB"; +LOCATE COMP "MupixBoard8_0/mupix_data_link/mupix_serdes_new/PCSD_INST" SITE "PCSB"; LOCATE COMP "led_addon_0" SITE "P1"; LOCATE COMP "led_addon_1" SITE "P2"; diff --git a/mupix/Mupix8/sources/DataMuxWithConversion.vhd b/mupix/Mupix8/sources/DataMuxWithConversion.vhd index 80d5a8c..2f5e702 100644 --- a/mupix/Mupix8/sources/DataMuxWithConversion.vhd +++ b/mupix/Mupix8/sources/DataMuxWithConversion.vhd @@ -39,7 +39,7 @@ end entity FiFoDataMuxWithConversion; architecture RTL of FiFoDataMuxWithConversion is signal ticks_counter : unsigned(f_log2(g_clockspeed) - 1 downto 0) := (others => '0'); - signal inword_counter : t_counter32_array(0 to g_inputs - 1) := (others => (others => '0')); + signal inword_counter : t_counter32_array(0 to g_inputs - 1) := (others => (others => '0')); signal increase_counter : std_logic_vector(g_inputs - 1 downto 0) := (others => '0'); signal fifo_full_i : std_logic; @@ -63,18 +63,20 @@ architecture RTL of FiFoDataMuxWithConversion is end component RoundRobinArbiter; --data width converter signals - constant padding_0 : std_logic_vector(23 downto 0) := (others => '0'); - constant padding_1 : std_logic_vector(15 downto 0) := (others => '0'); - constant padding_2 : std_logic_vector(7 downto 0) := (others => '0'); + constant padding_0 : std_logic_vector(23 downto 0) := (others => '0'); + constant padding_1 : std_logic_vector(15 downto 0) := (others => '0'); + constant padding_2 : std_logic_vector(7 downto 0) := (others => '0'); type convert_mem_type is array (0 to 1) of std_logic_vector(c_mupixhitsize - 1 downto 0); - signal data_shift : convert_mem_type := (others => (others => '0')); - signal conversioncounter : integer range 0 to 6 := 0; - signal empty_delay : std_logic_vector(1 downto 0) := (others => '0'); + signal data_shift : convert_mem_type := (others => (others => '0')); + signal data_select : std_logic_vector(c_mupixhitsize - 1 downto 0) := (others => '0'); + signal conversioncounter : integer range 0 to 6 := 0; + signal empty_delay : std_logic_vector(1 downto 0) := (others => '0'); begin request_i <= not fifo_empty and fifo_mask; + -- arbitration of inputs arbiter_1 : component RoundRobinArbiter generic map( g_num_channels => g_inputs @@ -84,6 +86,7 @@ begin requests => request_i, grant => grant_i); + -- select fifo by grant from arbiter fifo_select_proc : process(grant_i) is variable sel : integer range -1 to g_inputs - 1; begin @@ -106,6 +109,7 @@ begin fifo_full_i <= full; end process full_flag_proc; + -- measure input words per second of arbiter inputs input_freq : process (clk) is begin if rising_edge(clk) then @@ -127,7 +131,59 @@ begin end if; end process input_freq; + -- purpose: select data from fifo data input (assume max of four inputs) + -- type : combinational + data_sel_2 : if g_inputs = 2 generate + data_select_proc : process (fifo_datain, fifo_sel_reg) is + begin -- process data_select + case fifo_sel_reg is + when 0 => + data_select <= fifo_datain(g_datawidthfifo - 1 downto 0); + when 1 => + data_select <= fifo_datain(2 * g_datawidthfifo - 1 downto g_datawidthfifo); + when others => + data_select <= (others => '0'); + end case; + end process data_select_proc; + end generate data_sel_2; + data_sel_3 : if g_inputs = 3 generate + data_select_proc : process (fifo_datain, fifo_sel_reg) is + begin -- process data_select + case fifo_sel_reg is + when 0 => + data_select <= fifo_datain(g_datawidthfifo - 1 downto 0); + when 1 => + data_select <= fifo_datain(2 * g_datawidthfifo - 1 downto g_datawidthfifo); + when 2 => + data_select <= fifo_datain(3 * g_datawidthfifo - 1 downto 2 * g_datawidthfifo); + when others => + data_select <= (others => '0'); + end case; + end process data_select_proc; + end generate data_sel_3; + + data_sel_4 : if g_inputs = 4 generate + data_select_proc : process (fifo_datain, fifo_sel_reg) is + begin -- process data_select + case fifo_sel_reg is + when 0 => + data_select <= fifo_datain(g_datawidthfifo - 1 downto 0); + when 1 => + data_select <= fifo_datain(2 * g_datawidthfifo - 1 downto g_datawidthfifo); + when 2 => + data_select <= fifo_datain(3 * g_datawidthfifo - 1 downto 2 * g_datawidthfifo); + when 3 => + data_select <= fifo_datain(4 * g_datawidthfifo - 1 downto 3 * g_datawidthfifo); + when others => + data_select <= (others => '0'); + end case; + end process data_select_proc; + end generate data_sel_4; + + + -- multiplexing of fifo data inputs into output and width conversion from + -- mupix hit word width to 32 bit mux_proc : process(clk) is begin if rising_edge(clk) then @@ -162,7 +218,7 @@ begin -- width conversion conversioncounter <= conversioncounter + 1; data_shift(1) <= data_shift(0); - data_shift(0) <= fifo_datain((fifo_sel_reg + 1)*g_datawidthfifo - 1 downto g_datawidthfifo*fifo_sel_reg); + data_shift(0) <= data_select; if empty_delay = "11" then mux_fsm <= idle; end if; @@ -213,7 +269,6 @@ begin end if; end process mux_proc; - fifo_full_o <= fifo_full_i; end architecture RTL; diff --git a/mupix/Mupix8/sources/DatasourceSelector.vhd b/mupix/Mupix8/sources/DatasourceSelector.vhd index 7d13510..d62da28 100644 --- a/mupix/Mupix8/sources/DatasourceSelector.vhd +++ b/mupix/Mupix8/sources/DatasourceSelector.vhd @@ -9,7 +9,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -entity DataSel is +entity DataSourceSelector is generic( constant WIDTH : natural := 32; constant DEPTH : natural := 256 @@ -45,9 +45,9 @@ entity DataSel is fifo_full : out std_logic_vector(3 downto 0); fifo_empty: out std_logic_vector(3 downto 0) ); -end DataSel; +end DataSourceSelector; -architecture Behavioral of DataSel is +architecture Behavioral of DataSourceSelector is begin diff --git a/mupix/Mupix8/sources/FrameGenMux2.vhd b/mupix/Mupix8/sources/FrameGeneratorMux.vhd similarity index 98% rename from mupix/Mupix8/sources/FrameGenMux2.vhd rename to mupix/Mupix8/sources/FrameGeneratorMux.vhd index bbbcc4d..13e439f 100644 --- a/mupix/Mupix8/sources/FrameGenMux2.vhd +++ b/mupix/Mupix8/sources/FrameGeneratorMux.vhd @@ -1,6 +1,7 @@ ---------------------------------------------------------------------------------- -- Pseudo Data Generator and Data Source Selector --- René Hagdorn, Ruhr-Universität Bochum +-- René Hagdorn, Ruhr-Universität Bochum +-- TODO: Number of channels as generic ---------------------------------------------------------------------------------- @@ -73,7 +74,7 @@ component STD_FIFO ); end component STD_FIFO; -component DataSel is +component DataSourceSelector is generic( constant WIDTH : natural ); @@ -108,7 +109,7 @@ component DataSel is fifo_full : out std_logic_vector(3 downto 0); fifo_empty: out std_logic_vector(3 downto 0) ); -end component DataSel; +end component DataSourceSelector; -- signal types type chan_type is array (0 to 3) of std_logic_vector(1 downto 0); @@ -168,7 +169,7 @@ begin -- Behavioral ); end generate Frame_Generator; - Mux: DataSel + Mux: DataSourceSelector generic map( WIDTH => DATAWIDTH ) diff --git a/mupix/Mupix8/sources/MuPixDataLink_new.vhd b/mupix/Mupix8/sources/MuPixDataLink_new.vhd index 35d7c04..a180c64 100644 --- a/mupix/Mupix8/sources/MuPixDataLink_new.vhd +++ b/mupix/Mupix8/sources/MuPixDataLink_new.vhd @@ -51,7 +51,7 @@ architecture rtl of MupixDataLinkWithUnpacker is sync_output : out std_logic_vector(width - 1 downto 0)); end component InputSynchronizer; - component serdes_fifo + component serdes_fifo -- regenerate if number of mupix hit bits changes port ( Data : in std_logic_vector(39 downto 0); WrClock : in std_logic; @@ -204,12 +204,8 @@ architecture rtl of MupixDataLinkWithUnpacker is signal rx_komma_sync : std_logic_vector(3 downto 0); -- fifo signals - signal fifo_data_oi : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0); signal fifo_data_ii : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0); - signal fifo_empty_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); - signal fifo_full_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); signal fifo_wren_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); - signal fifo_rden_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); constant fifo_depth : integer := 11; -- fifo depth (change when regenerating FIFO IP core) signal fifo_readcnt_i : std_logic_vector(c_links*fifo_depth - 1 downto 0); @@ -398,13 +394,13 @@ begin WrClock => clkrx(j), RdClock => sysclk, WrEn => fifo_wren_i(j), - RdEn => fifo_rden_i(j), + RdEn => fifo_rden(j), Reset => reset_fifos_i, RPReset => reset_fifos_i, - Q => fifo_data_oi((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize), + Q => fifo_data((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize), RCNT => fifo_readcnt_i((j + 1)*fifo_depth - 1 downto j*fifo_depth), - Empty => fifo_empty_i(j), - Full => fifo_full_i(j)); + Empty => fifo_empty(j), + Full => fifo_full(j)); end generate generate_fifo; -- error counters (using gray counters because of possible clock domain diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 56e7845..3de7ed7 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -515,7 +515,7 @@ begin -- Behavioral mupixreadout1 : entity work.MupixTRBReadout generic map( - g_mupix_links => 4, + g_mupix_links => c_links, g_cyc_mem_address_width => 12, g_datawidthfifo => c_mupixhitsize, g_datawidthtrb => 32 diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj index 2aff52a..1b9a39b 100644 --- a/mupix/Mupix8/trb3_periph.prj +++ b/mupix/Mupix8/trb3_periph.prj @@ -174,7 +174,7 @@ add_file -vhdl -lib "work" "sources/MuPixDataLink_new.vhd" add_file -vhdl -lib "work" "sources/TriggerHandler.vhd" add_file -vhdl -lib "work" "sources/Arbiter.vhd" add_file -vhdl -lib "work" "sources/DatasourceSelector.vhd" -add_file -vhdl -lib "work" "sources/FrameGenMux2.vhd" +add_file -vhdl -lib "work" "sources/FrameGeneratorMux.vhd" add_file -vhdl -lib "work" "sources/Generator3.vhd" add_file -vhdl -lib "work" "sources/DataMuxWithConversion.vhd" add_file -vhdl -lib "work" "sources/GrayCounter2.vhd" -- 2.43.0