From 09fc63b1f1fcb8b6dcb9906b0cd2a8169a7e35bc Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Fri, 6 Feb 2015 19:35:49 +0100 Subject: [PATCH] Take polarity into account for CFD subtraction --- ADC/sim/tb_adcprocessor.vhd | 1 + ADC/source/adc_processor.vhd | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/ADC/sim/tb_adcprocessor.vhd b/ADC/sim/tb_adcprocessor.vhd index da0eaa6..a035a9d 100644 --- a/ADC/sim/tb_adcprocessor.vhd +++ b/ADC/sim/tb_adcprocessor.vhd @@ -101,6 +101,7 @@ config.buffer_depth <= to_unsigned(128 ,11); config.samples_after <= to_unsigned(8 ,11); config.block_count <= to_unsigned(2 , 2); config.trigger_threshold <= to_unsigned(30 ,18); +config.trigger_threshold(16) <= '1'; -- invert polarity config.readout_threshold <= to_unsigned(30 ,18); config.presum <= to_unsigned(0 , 8); config.averaging <= to_unsigned(6 , 4); diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd index 43a3567..21d17dd 100644 --- a/ADC/source/adc_processor.vhd +++ b/ADC/source/adc_processor.vhd @@ -813,8 +813,14 @@ begin begin wait until rising_edge(CLK); - cfd_subtracted(ch) <= signed(resize(reg_ram_data_out(ch)(15 downto 0), cfd_subtracted(ch)'length)) - signed(resize(baseline(ch), cfd_subtracted(ch)'length)); - + if CONF.trigger_threshold(16) = '0' then + cfd_subtracted(ch) <= signed(resize(reg_ram_data_out(ch)(15 downto 0), cfd_subtracted(ch)'length)) + - signed(resize(baseline(ch), cfd_subtracted(ch)'length)); + else + cfd_subtracted(ch) <= signed(resize(baseline(ch), cfd_subtracted(ch)'length)) + - signed(resize(reg_ram_data_out(ch)(15 downto 0), cfd_subtracted(ch)'length)); + end if; + cfd_delay_ram(ch)(0) <= cfd_subtracted(ch); gen_cfd_delay : for i in 0 to cfd_delay_ram(ch)'length - 2 loop cfd_delay_ram(ch)(i + 1) <= cfd_delay_ram(ch)(i); -- 2.43.0