From 0a59ab0fd4e3b804bd007c0e96a28b0e93f88875 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 1 Nov 2022 10:29:22 +0100 Subject: [PATCH] DHCP seems to work now, PING/ARP fails --- gbe_trb/base/gbe_frame_receiver.vhd | 1304 +++++++++-------- gbe_trb/base/gbe_logic_wrapper.vhd | 26 +- gbe_trb/base/gbe_main_control.vhd | 21 +- gbe_trb/base/gbe_protocol_prioritizer.vhd | 4 +- gbe_trb/base/gbe_receive_control.vhd | 334 ++--- gbe_trb/base/gbe_sci_reader.vhd | 5 +- gbe_trb/base/gbe_tx_fifo.vhd | 122 ++ gbe_trb/base/inserter.vhd | 30 +- gbe_trb/base/remover.vhd | 34 +- .../gbe_response_constructor_DHCP.vhd | 4 +- .../gbe_response_constructor_Forward.vhd | 39 +- gbe_trb_ecp3/media/gbe_med_fifo.vhd | 24 +- media_interfaces/sync/gbe_rx_reset.vhd | 250 ++++ trb_net16_regio_bus_handler_record.vhd | 113 +- 14 files changed, 1345 insertions(+), 965 deletions(-) create mode 100644 gbe_trb/base/gbe_tx_fifo.vhd create mode 100644 media_interfaces/sync/gbe_rx_reset.vhd diff --git a/gbe_trb/base/gbe_frame_receiver.vhd b/gbe_trb/base/gbe_frame_receiver.vhd index 099db77..8b5967a 100644 --- a/gbe_trb/base/gbe_frame_receiver.vhd +++ b/gbe_trb/base/gbe_frame_receiver.vhd @@ -5,7 +5,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; -use work.trb_net_components.all; +--use work.trb_net_components.all; use work.gbe_protocols.all; --******** @@ -19,699 +19,737 @@ use work.gbe_protocols.all; -- data by FR_FRAME_VALID_OUT. entity gbe_frame_receiver is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - LINK_OK_IN : in std_logic; - ALLOW_RX_IN : in std_logic; - MY_MAC_IN : in std_logic_vector(47 downto 0); --- killer ping - MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0) := (others => '0'); - ISSUE_REBOOT_OUT : out std_logic; --- input signals from TS_MAC - MAC_RX_EOF_IN : in std_logic; -- End Of Frame - MAC_RX_ER_IN : in std_logic; -- only for statistics - MAC_RXD_IN : in std_logic_vector(7 downto 0); -- RX data - MAC_RX_EN_IN : in std_logic; -- write signal --- output signal to control logic - FR_Q_OUT : out std_logic_vector(8 downto 0); - FR_RD_EN_IN : in std_logic; - FR_FRAME_VALID_OUT : out std_logic; - FR_GET_FRAME_IN : in std_logic; - FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); - FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0); - FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0); - FR_VLAN_ID_IN : in std_logic_vector(31 downto 0); --- - FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); --- - OOB_REGISTER_0_OUT : out std_logic_vector(31 downto 0); - OOB_REGISTER_1_OUT : out std_logic_vector(31 downto 0); - OOB_REGISTER_2_OUT : out std_logic_vector(31 downto 0); - OOB_REGISTER_3_OUT : out std_logic_vector(31 downto 0); --- - MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); - MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) -); + port( + CLK : in std_logic; -- system clock + RESET : in std_logic; + LINK_OK_IN : in std_logic; + ALLOW_RX_IN : in std_logic; + MY_MAC_IN : in std_logic_vector(47 downto 0); + -- killer ping + MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0) := (others => '0'); + ISSUE_REBOOT_OUT : out std_logic; + -- input signals from TS_MAC + MAC_RX_EOF_IN : in std_logic; -- End Of Frame + MAC_RX_ER_IN : in std_logic; -- only for statistics + MAC_RXD_IN : in std_logic_vector(7 downto 0); -- RX data + MAC_RX_EN_IN : in std_logic; -- write signal + -- output signal to control logic + FR_Q_OUT : out std_logic_vector(8 downto 0); -- interconnect to gbe_receive_control + FR_RD_EN_IN : in std_logic; -- interconnect to gbe_receive_control + FR_FRAME_VALID_OUT : out std_logic; -- interconnect to gbe_receive_control + FR_GET_FRAME_IN : in std_logic; -- interconnect to gbe_receive_control + FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control + FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control + FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); -- interconnect to gbe_receive_control + FR_PS_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + -- + FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + -- + OOB_REGISTER_0_OUT : out std_logic_vector(31 downto 0); + OOB_REGISTER_1_OUT : out std_logic_vector(31 downto 0); + OOB_REGISTER_2_OUT : out std_logic_vector(31 downto 0); + OOB_REGISTER_3_OUT : out std_logic_vector(31 downto 0); + -- + MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); end gbe_frame_receiver; -architecture gbe_frame_receiver_arch of gbe_frame_receiver is +-- This entity receives frames from the MAC. The MAC will send the frames once they are received +-- from SGMII core. Start of frame is marked by 'new_frame' signal. The incoming frame will be +-- reviewed, and checked if it should be forwarded to the next level. +-- First check is MAC address: only broadcast frames and frames with the board's MAC address are accepted. +-- VLAN tagged frames are handled, but will be checked later. +-- Second check is done inside gbe_type_validator: IPV4 UDP with correct port number are accepted, +-- as well as ICMP inside IPv4. In addition, in gbe_protocols more accepted combinations can be defined. +-- VLAN tagged frames are accepted, in case of tag == 0x0000, or if the VLAN tag is identical to one of the +-- two stored ones. -attribute syn_encoding : string; -type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, - REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP); -signal filter_current_state, filter_next_state : filter_states; -attribute syn_encoding of filter_current_state : signal is "onehot"; - -signal fifo_wr_en : std_logic; -signal rx_bytes_ctr : std_logic_vector(15 downto 0); -signal frame_valid_q : std_logic; -signal delayed_frame_valid : std_logic; -signal delayed_frame_valid_q : std_logic; - -signal rec_fifo_empty : std_logic; -signal rec_fifo_full : std_logic; -signal sizes_fifo_full : std_logic; -signal sizes_fifo_empty : std_logic; - -signal remove_ctr : unsigned(7 downto 0); -signal new_frame : std_logic; -signal new_frame_lock : std_logic := '0'; -signal saved_frame_type : std_logic_vector(15 downto 0); -signal saved_vid : std_logic_vector(15 downto 0) := (others => '0'); -signal saved_src_mac : std_logic_vector(47 downto 0); -signal saved_dest_mac : std_logic_vector(47 downto 0); -signal frame_type_valid : std_logic; -signal saved_proto : std_logic_vector(7 downto 0); -signal saved_src_ip : std_logic_vector(31 downto 0); -signal saved_dest_ip : std_logic_vector(31 downto 0); -signal saved_src_udp : std_logic_vector(15 downto 0); -signal saved_dest_udp : std_logic_vector(15 downto 0); - -signal error_frames_ctr : unsigned(15 downto 0); -signal dbg_rec_frames : unsigned(31 downto 0); -signal dbg_drp_frames : unsigned(31 downto 0); -signal mon_rec_bytes : unsigned(31 downto 0); - -signal state : std_logic_vector(3 downto 0); - -signal rx_data : std_logic_vector(8 downto 0); -signal fr_q : std_logic_vector(8 downto 0); - -signal fr_src_ip : std_logic_vector(31 downto 0); -signal fr_dest_ip : std_logic_vector(31 downto 0); -signal fr_dest_udp : std_logic_vector(15 downto 0); -signal fr_src_udp : std_logic_vector(15 downto 0); -signal fr_frame_size : std_logic_vector(15 downto 0); -signal fr_frame_proto : std_logic_vector(15 downto 0); -signal fr_dest_mac : std_logic_vector(47 downto 0); -signal fr_src_mac : std_logic_vector(47 downto 0); -signal fr_ip_proto : std_logic_vector(7 downto 0); - -signal xxx0 : std_logic_vector(7 downto 0); -signal xxx1 : std_logic_vector(7 downto 0); - -signal oob_register_0_int : std_logic_vector(31 downto 0); -signal oob_register_1_int : std_logic_vector(31 downto 0); -signal oob_register_2_int : std_logic_vector(31 downto 0); -signal oob_register_3_int : std_logic_vector(31 downto 0); -signal oob_write : std_logic; - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true; -attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true; +-- BUG: MAC_RX_ERROR is not really used. Broken frames will not be discarded! -begin +-- BUG: no protection against overflow of FIFOs! --- new_frame is asserted when first byte of the frame arrives -THE_NEW_FRAME_PROC: process( CLK ) -begin - if( rising_edge(CLK) )then - if ( (LINK_OK_IN = '0') or (MAC_RX_EOF_IN = '1') ) then - new_frame <= '0'; - new_frame_lock <= '0'; - elsif( (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') ) then - new_frame <= '1'; - new_frame_lock <= '1'; - else - new_frame <= '0'; - end if; - end if; -end process THE_NEW_FRAME_PROC; +architecture gbe_frame_receiver_arch of gbe_frame_receiver is -THE_FILTER_MACHINE_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - filter_current_state <= IDLE; - elsif( rising_edge(CLK) ) then - filter_current_state <= filter_next_state; - end if; -end process THE_FILTER_MACHINE_PROC; + attribute syn_encoding : string; + type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, + REMOVE_IP, REMOVE_UDP, DELAY, CLEANUP); + signal filter_current_state, filter_next_state : filter_states; + attribute syn_encoding of filter_current_state : signal is "onehot"; + + signal fifo_wr_en : std_logic; + signal rx_bytes_ctr : std_logic_vector(15 downto 0); + signal frame_valid_q : std_logic; + signal delayed_frame_valid : std_logic; + signal delayed_frame_valid_q : std_logic; + + signal rec_fifo_empty : std_logic; + signal rec_fifo_full : std_logic; + signal sizes_fifo_full : std_logic; + signal sizes_fifo_empty : std_logic; + + signal remove_ctr : unsigned(7 downto 0); + signal new_frame : std_logic; + signal new_frame_lock : std_logic := '0'; + signal saved_frame_type : std_logic_vector(15 downto 0); + signal saved_src_mac : std_logic_vector(47 downto 0); + signal saved_dest_mac : std_logic_vector(47 downto 0); + signal frame_type_valid : std_logic; + signal saved_proto : std_logic_vector(7 downto 0); + signal saved_src_ip : std_logic_vector(31 downto 0); + signal saved_dest_ip : std_logic_vector(31 downto 0); + signal saved_src_udp : std_logic_vector(15 downto 0); + signal saved_dest_udp : std_logic_vector(15 downto 0); + + signal error_frames_ctr : unsigned(15 downto 0); + signal dbg_rec_frames : unsigned(31 downto 0); + signal dbg_drp_frames : unsigned(31 downto 0); + signal mon_rec_bytes : unsigned(31 downto 0); + + signal state : std_logic_vector(3 downto 0); + + signal rx_data : std_logic_vector(8 downto 0); + signal fr_q : std_logic_vector(8 downto 0); + + signal fr_src_ip : std_logic_vector(31 downto 0); + signal fr_dest_ip : std_logic_vector(31 downto 0); + signal fr_dest_udp : std_logic_vector(15 downto 0); + signal fr_src_udp : std_logic_vector(15 downto 0); + signal fr_frame_size : std_logic_vector(15 downto 0); + signal fr_frame_proto : std_logic_vector(15 downto 0); + signal fr_dest_mac : std_logic_vector(47 downto 0); + signal fr_src_mac : std_logic_vector(47 downto 0); + signal fr_ip_proto : std_logic_vector(7 downto 0); + signal fr_ps : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + signal xxx0 : std_logic_vector(7 downto 0); + signal xxx1 : std_logic_vector(7 downto 0); + + signal oob_register_0_int : std_logic_vector(31 downto 0); + signal oob_register_1_int : std_logic_vector(31 downto 0); + signal oob_register_2_int : std_logic_vector(31 downto 0); + signal oob_register_3_int : std_logic_vector(31 downto 0); + signal oob_write : std_logic; + + signal proto_select_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + signal set_proto_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -THE_FILTER_MACHINE : process( filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN, - saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN) begin - case filter_current_state is - when IDLE => - state <= x"1"; - if( (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') ) then - filter_next_state <= REMOVE_DEST; + -- Debug lines + DEBUG_OUT(31 downto 26) <= (others => '0'); + + DEBUG_OUT(15) <= frame_valid_q; + DEBUG_OUT(14) <= fifo_wr_en; + DEBUG_OUT(13) <= frame_type_valid; + DEBUG_OUT(12) <= new_frame_lock; + DEBUG_OUT(11) <= new_frame; + DEBUG_OUT(10) <= MAC_RX_ER_IN; + DEBUG_OUT(9) <= MAC_RX_EOF_IN; + DEBUG_OUT(8) <= MAC_RX_EN_IN; + DEBUG_OUT(7 downto 0) <= MAC_RXD_IN; + + -- new_frame is asserted when first byte of the frame arrives + PROC_NEW_FRAME: process( CLK ) + begin + if( rising_edge(CLK) )then + if ( (LINK_OK_IN = '0') or (MAC_RX_EOF_IN = '1') ) then + new_frame <= '0'; + new_frame_lock <= '0'; + elsif( (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') ) then + new_frame <= '1'; + new_frame_lock <= '1'; else - filter_next_state <= IDLE; + new_frame <= '0'; end if; + end if; + end process PROC_NEW_FRAME; + + PROC_FILTER_FSM: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + filter_current_state <= IDLE; + elsif( rising_edge(CLK) ) then + filter_current_state <= filter_next_state; + end if; + end process PROC_FILTER_FSM; - -- frames arrive without preamble! - when REMOVE_DEST => - state <= x"3"; - if( remove_ctr = x"03" ) then -- counter starts with a delay that's why only 3 - -- destination MAC address filtering here - if( (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") ) then -- must accept broadcasts for ARP - filter_next_state <= REMOVE_SRC; + PROC_FILTER_TRANSITIONS : process( filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN, + saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN) + begin + set_proto_x <= (others => '0'); + + case filter_current_state is + + when IDLE => + state <= x"1"; + if( (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') ) then + filter_next_state <= REMOVE_DEST; else - filter_next_state <= DECIDE; + filter_next_state <= IDLE; end if; - else - filter_next_state <= REMOVE_DEST; - end if; - when REMOVE_SRC => - state <= x"4"; - if( remove_ctr = x"09" ) then - filter_next_state <= REMOVE_TYPE; - else - filter_next_state <= REMOVE_SRC; - end if; - - when REMOVE_TYPE => - state <= x"5"; - if( remove_ctr = x"0b" ) then - if( saved_frame_type = x"8100" ) then -- VLAN tagged frame - filter_next_state <= REMOVE_VID; - else -- no VLAN tag - if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers - filter_next_state <= REMOVE_IP; + -- frames arrive without preamble! + when REMOVE_DEST => + state <= x"3"; + if( remove_ctr = x"03" ) then -- counter starts with a delay that's why only 3 + -- destination MAC address filtering here + if( (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") ) then -- must accept broadcasts for ARP + filter_next_state <= REMOVE_SRC; else - filter_next_state <= DECIDE; + filter_next_state <= DROP_FRAME; -- wrong MAC, were are done + -- could be done in REMOVE_SRC to gain some clock cycles end if; + else + filter_next_state <= REMOVE_DEST; end if; - else - filter_next_state <= REMOVE_TYPE; - end if; - - when REMOVE_VID => - state <= x"a"; - if( remove_ctr = x"0d" ) then - filter_next_state <= REMOVE_VTYPE; - else - filter_next_state <= REMOVE_VID; - end if; - when REMOVE_VTYPE => - state <= x"b"; - if( remove_ctr = x"0f" ) then - if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers - filter_next_state <= REMOVE_IP; + when REMOVE_SRC => + state <= x"4"; + if( remove_ctr = x"09" ) then + filter_next_state <= REMOVE_TYPE; else - filter_next_state <= DECIDE; + filter_next_state <= REMOVE_SRC; end if; - else - filter_next_state <= REMOVE_VTYPE; - end if; - when REMOVE_IP => - state <= x"c"; - if( remove_ctr = x"11" ) then - if( saved_proto = x"11" ) then -- forced to recognize udp only, TODO check all protocols - filter_next_state <= REMOVE_UDP; + when REMOVE_TYPE => + state <= x"5"; + if( remove_ctr = x"0b" ) then + case saved_frame_type is + when x"0800" => + -- IPv4 frame, to be investigated + filter_next_state <= REMOVE_IP; + when x"0806" => + -- ARP frame, to be stored + filter_next_state <= DELAY; + set_proto_x(0) <= '1'; + -- NB: first two bytes of ARP frame are dropped silently + when others => + filter_next_state <= DROP_FRAME; + end case; else - filter_next_state <= DECIDE; -- changed from drop + filter_next_state <= REMOVE_TYPE; end if; - else - filter_next_state <= REMOVE_IP; - end if; - when REMOVE_UDP => - state <= x"d"; - if( remove_ctr = x"19" ) then - filter_next_state <= DECIDE; - else - filter_next_state <= REMOVE_UDP; - end if; + when REMOVE_IP => + state <= x"c"; + if( remove_ctr = x"11" ) then + -- BUG: add check for 0x45 (IP version, header length) here. + -- Drop frames which do not comply with this! + case saved_proto is + when x"11" => + -- UDP, to be investigated + filter_next_state <= REMOVE_UDP; + when x"01" => + -- ICMP, to be stored + filter_next_state <= DELAY; + set_proto_x(4) <= '1'; + when others => + filter_next_state <= DROP_FRAME; + end case; + else + filter_next_state <= REMOVE_IP; + end if; - when DECIDE => - state <= x"6"; - if ( frame_type_valid = '1' ) then - filter_next_state <= SAVE_FRAME; - elsif( saved_frame_type = x"0806" ) then - -- ARP? - filter_next_state <= SAVE_FRAME; - else - filter_next_state <= DROP_FRAME; - end if; + when REMOVE_UDP => + state <= x"d"; + if( remove_ctr = x"19" ) then + case saved_dest_udp is + when x"0044" => + -- DHCP frame, to be stored + filter_next_state <= DELAY; + set_proto_x(1) <= '1'; + when x"6590" => + -- SCTRL frame, to be stored + filter_next_state <= DELAY; + set_proto_x(2) <= '1'; + when others => + filter_next_state <= DROP_FRAME; + end case; + else + filter_next_state <= REMOVE_UDP; + end if; - when SAVE_FRAME => - state <= x"7"; - if( MAC_RX_EOF_IN = '1' ) then - filter_next_state <= CLEANUP; - else + when DELAY => + state <= x"6"; filter_next_state <= SAVE_FRAME; - end if; - when DROP_FRAME => - state <= x"8"; - if( MAC_RX_EOF_IN = '1' ) then - filter_next_state <= CLEANUP; - else - filter_next_state <= DROP_FRAME; - end if; - - when CLEANUP => - state <= x"9"; - filter_next_state <= IDLE; - - when others => null; + when SAVE_FRAME => + state <= x"7"; + if( MAC_RX_EOF_IN = '1' ) then + filter_next_state <= CLEANUP; + else + filter_next_state <= SAVE_FRAME; + end if; - end case; -end process THE_FILTER_MACHINE; + when DROP_FRAME => + state <= x"8"; + if( MAC_RX_EOF_IN = '1' ) then + filter_next_state <= CLEANUP; + else + filter_next_state <= DROP_FRAME; + end if; --- counts the bytes to be removed from the ethernet headers fields -REMOVE_CTR_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (filter_current_state = IDLE) or - ((filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0f")) or - ((filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type /= x"8100")) ) then - remove_ctr <= (others => '1'); - elsif( (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) ) then - remove_ctr <= remove_ctr + 1; - end if; - end if; -end process REMOVE_CTR_PROC; + when CLEANUP => + state <= x"9"; + filter_next_state <= IDLE; -THE_SAVED_PROTO_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_proto <= (others => '0'); - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") ) then - saved_proto <= MAC_RXD_IN; + when others => null; + + end case; + end process PROC_FILTER_TRANSITIONS; + + -- determine the protocol handler for later usage + -- ARP + proto_select_x(0) <= '1' when ( (saved_frame_type = x"0806") ) else '0'; + -- DHCP + proto_select_x(1) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"0044") ) else '0'; + -- SCTRL + proto_select_x(2) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"6590") ) else '0'; + -- ??? + proto_select_x(3) <= '0'; + -- ICMP + proto_select_x(4) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"01") ) else '0'; + -- FWD??? + proto_select_x(5) <= '0'; + -- TO BE INCLUDED INTO FSM!!! + + -- protocol selection + PROC_PROTO_SEL: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + proto_select <= (others => '0'); + elsif( rising_edge(CLK) ) then + for I in c_MAX_PROTOCOLS - 1 downto 0 loop + if ( set_proto_x(I) = '1' ) then + proto_select(I) <= '1'; + elsif( filter_current_state = CLEANUP ) then + proto_select(I) <= '0'; + end if; + end loop; end if; + end process PROC_PROTO_SEL; + + -- counts the bytes to be removed from the ethernet headers fields + PROC_REMOVE_CTR: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( (filter_current_state = IDLE) or + ((filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b")) ) then + remove_ctr <= (others => '1'); + elsif( (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) ) then + remove_ctr <= remove_ctr + 1; + end if; end if; -end process THE_SAVED_PROTO_PROC; - --- saves the destination mac address of the incoming frame -THE_SAVED_DEST_MAC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_dest_mac <= (others => '0'); - elsif( (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') ) then - saved_dest_mac(7 downto 0) <= MAC_RXD_IN; - elsif( (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') ) then - saved_dest_mac(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") ) then - saved_dest_mac(23 downto 16) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") ) then - saved_dest_mac(31 downto 24) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") ) then - saved_dest_mac(39 downto 32) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") ) then - saved_dest_mac(47 downto 40) <= MAC_RXD_IN; + end process PROC_REMOVE_CTR; + + -- saves the IP protocol + PROC_SAVED_PROTO: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_proto <= (others => '0'); + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") ) then + saved_proto <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_DEST_MAC_PROC; - --- saves the source mac address of the incoming frame -THE_SAVED_SRC_MAC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_src_mac <= (others => '0'); - elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") )then - saved_src_mac(7 downto 0) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") ) then - saved_src_mac(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") ) then - saved_src_mac(23 downto 16) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") ) then - saved_src_mac(31 downto 24) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") ) then - saved_src_mac(39 downto 32) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") ) then - saved_src_mac(47 downto 40) <= MAC_RXD_IN; + end process PROC_SAVED_PROTO; + + -- saves the destination mac address of the incoming frame + PROC_SAVED_DEST_MAC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_dest_mac <= (others => '0'); + elsif( (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') ) then + saved_dest_mac(7 downto 0) <= MAC_RXD_IN; + elsif( (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') ) then + saved_dest_mac(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") ) then + saved_dest_mac(23 downto 16) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") ) then + saved_dest_mac(31 downto 24) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") ) then + saved_dest_mac(39 downto 32) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") ) then + saved_dest_mac(47 downto 40) <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_SRC_MAC_PROC; - --- saves the frame type of the incoming frame for futher check -THE_SAVED_FRAME_TYPE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_frame_type <= (others => '0'); - elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") ) then - saved_frame_type(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") ) then - saved_frame_type(7 downto 0) <= MAC_RXD_IN; - -- two more cases for VLAN tagged frame - elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") ) then - saved_frame_type(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") ) then - saved_frame_type(7 downto 0) <= MAC_RXD_IN; + end process PROC_SAVED_DEST_MAC; + + -- saves the source mac address of the incoming frame + PROC_SAVED_SRC_MAC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_src_mac <= (others => '0'); + elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") )then + saved_src_mac(7 downto 0) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") ) then + saved_src_mac(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") ) then + saved_src_mac(23 downto 16) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") ) then + saved_src_mac(31 downto 24) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") ) then + saved_src_mac(39 downto 32) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") ) then + saved_src_mac(47 downto 40) <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_FRAME_TYPE_PROC; - -THE_SAVED_SRC_IP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_src_ip <= (others => '0'); - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") ) then - saved_src_ip(7 downto 0) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") ) then - saved_src_ip(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") ) then - saved_src_ip(23 downto 16) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") ) then - saved_src_ip(31 downto 24) <= MAC_RXD_IN; + end process PROC_SAVED_SRC_MAC; + + -- saves the frame type of the incoming frame for futher check + PROC_SAVED_FRAME_TYPE: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_frame_type <= (others => '0'); + elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") ) then + saved_frame_type(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") ) then + saved_frame_type(7 downto 0) <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_SRC_IP_PROC; - -THE_SAVED_DEST_IP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_dest_ip <= (others => '0'); - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") ) then - saved_dest_ip(7 downto 0) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") ) then - saved_dest_ip(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") ) then - saved_dest_ip(23 downto 16) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") ) then - saved_dest_ip(31 downto 24) <= MAC_RXD_IN; + end process PROC_SAVED_FRAME_TYPE; + + PROC_SAVED_SRC_IP: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_src_ip <= (others => '0'); + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") ) then + saved_src_ip(7 downto 0) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") ) then + saved_src_ip(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") ) then + saved_src_ip(23 downto 16) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") ) then + saved_src_ip(31 downto 24) <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_DEST_IP_PROC; - -THE_SAVED_SRC_UDP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_src_udp <= (others => '0'); - elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") ) then - saved_src_udp(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") ) then - saved_src_udp(7 downto 0) <= MAC_RXD_IN; + end process PROC_SAVED_SRC_IP; + + PROC_SAVED_DEST_IP: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_dest_ip <= (others => '0'); + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") ) then + saved_dest_ip(7 downto 0) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") ) then + saved_dest_ip(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") ) then + saved_dest_ip(23 downto 16) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") ) then + saved_dest_ip(31 downto 24) <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_SRC_UDP_PROC; - -THE_SAVED_DEST_UDP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_dest_udp <= (others => '0'); - elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") ) then - saved_dest_udp(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") ) then - saved_dest_udp(7 downto 0) <= MAC_RXD_IN; + end process PROC_SAVED_DEST_IP; + + PROC_SAVED_SRC_UDP: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_src_udp <= (others => '0'); + elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") ) then + saved_src_udp(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") ) then + saved_src_udp(7 downto 0) <= MAC_RXD_IN; + end if; end if; - end if; -end process THE_SAVED_DEST_UDP_PROC; + end process PROC_SAVED_SRC_UDP; + + PROC_SAVED_DEST_UDP: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( filter_current_state = CLEANUP ) then + saved_dest_udp <= (others => '0'); + elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") ) then + saved_dest_udp(15 downto 8) <= MAC_RXD_IN; + elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") ) then + saved_dest_udp(7 downto 0) <= MAC_RXD_IN; + end if; + end if; + end process PROC_SAVED_DEST_UDP; --- saves VLAN id when tagged frame spotted -THE_SAVED_VID_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( filter_current_state = CLEANUP ) then - saved_vid <= (others => '0'); - elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type = x"8100") ) then - saved_vid(15 downto 8) <= MAC_RXD_IN; - elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0c") ) then - saved_vid(7 downto 0) <= MAC_RXD_IN; + PROC_FRAME_TYPE_VALID: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frame_type_valid <= '0'; + elsif( rising_edge(CLK) ) then + if ( filter_current_state = SAVE_FRAME ) then + frame_type_valid <= '1'; + elsif( filter_current_state = CLEANUP ) then + frame_type_valid <= '0'; + end if; end if; - end if; -end process THE_SAVED_VID_PROC; - -THE_TYPE_VALIDATOR: entity gbe_type_validator -port map( - CLK => CLK, - RESET => RESET, - FRAME_TYPE_IN => saved_frame_type, - ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN, - SAVED_VLAN_ID_IN => saved_vid, - VLAN_ID_IN => FR_VLAN_ID_IN, - -- IP level - IP_PROTOCOLS_IN => saved_proto, - ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN, - -- UDP level - UDP_PROTOCOL_IN => saved_dest_udp, - ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN, - -- - VALID_OUT => frame_type_valid -); - -THE_RECEIVE_FIFO: entity fifo_4096x9 -port map( - Data => rx_data, - WrClock => CLK, - RdClock => CLK, - WrEn => fifo_wr_en, - RdEn => FR_RD_EN_IN, - Reset => RESET, - RPReset => RESET, - Q => fr_q, - Empty => rec_fifo_empty, - Full => rec_fifo_full -); - --- killer ping -THE_KILLER_PING_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( (filter_current_state = SAVE_FRAME) and - (saved_proto = x"01") and - (saved_frame_type = x"0800") and - (rx_bytes_ctr = x"001A") and - (rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0)) and - (MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) ) then - ISSUE_REBOOT_OUT <= '1'; - else - ISSUE_REBOOT_OUT <= '0'; + end process PROC_FRAME_TYPE_VALID; + + THE_RECEIVE_FIFO: entity work.fifo_4096x9 + port map( + Data => rx_data, + WrClock => CLK, + RdClock => CLK, + WrEn => fifo_wr_en, + RdEn => FR_RD_EN_IN, + Reset => RESET, + RPReset => RESET, + Q => fr_q, + Empty => rec_fifo_empty, + Full => rec_fifo_full + ); + + -- killer ping + PROC_KILLER_PING: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( (filter_current_state = SAVE_FRAME) and + (saved_proto = x"01") and + (saved_frame_type = x"0800") and + (rx_bytes_ctr = x"001A") and + (rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0)) and + (MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) ) then + ISSUE_REBOOT_OUT <= '1'; + else + ISSUE_REBOOT_OUT <= '0'; + end if; end if; - end if; -end process THE_KILLER_PING_PROC; - -THE_SECRET_FRAME_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( (filter_current_state = DECIDE) and - (saved_proto = x"11") and - (saved_frame_type = x"0800") and - (saved_dest_udp = x"d903") and - (saved_src_udp = x"2b67") ) then - oob_write <= '1'; - else - oob_write <= '0'; + end process PROC_KILLER_PING; + + PROC_SECRET_FRAME: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( (filter_current_state = DELAY) and + (saved_proto = x"11") and + (saved_frame_type = x"0800") and + (saved_dest_udp = x"d903") and + (saved_src_udp = x"2b67") ) then + oob_write <= '1'; + else + oob_write <= '0'; + end if; end if; - end if; -end process THE_SECRET_FRAME_PROC; - -THE_REGISTERS_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( oob_write = '1' ) then - case saved_src_ip(1 downto 0) is - when b"00" => oob_register_0_int <= saved_dest_ip; - when b"01" => oob_register_1_int <= saved_dest_ip; - when b"10" => oob_register_2_int <= saved_dest_ip; - when others => oob_register_3_int <= saved_dest_ip; - end case; + end process PROC_SECRET_FRAME; + + PROC_SECRET_REGISTERS: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( oob_write = '1' ) then + case saved_src_ip(1 downto 0) is + when b"00" => oob_register_0_int <= saved_dest_ip; + when b"01" => oob_register_1_int <= saved_dest_ip; + when b"10" => oob_register_2_int <= saved_dest_ip; + when others => oob_register_3_int <= saved_dest_ip; + end case; + end if; end if; - end if; -end process THE_REGISTERS_PROC; + end process PROC_SECRET_REGISTERS; -OOB_REGISTER_0_OUT <= oob_register_0_int; -OOB_REGISTER_1_OUT <= oob_register_1_int; -OOB_REGISTER_2_OUT <= oob_register_2_int; -OOB_REGISTER_3_OUT <= oob_register_3_int; + OOB_REGISTER_0_OUT <= oob_register_0_int; + OOB_REGISTER_1_OUT <= oob_register_1_int; + OOB_REGISTER_2_OUT <= oob_register_2_int; + OOB_REGISTER_3_OUT <= oob_register_3_int; -THE_RX_FIFO_SYNC: process( CLK ) -begin - if rising_edge(CLK) then + PROC_RX_FIFO_SYNC: process( CLK ) + begin + if rising_edge(CLK) then - rx_data(8) <= MAC_RX_EOF_IN; - rx_data(7 downto 0) <= MAC_RXD_IN; + rx_data(8) <= MAC_RX_EOF_IN; + rx_data(7 downto 0) <= MAC_RXD_IN; - if( MAC_RX_EN_IN = '1' ) then - if ( filter_current_state = SAVE_FRAME ) then - fifo_wr_en <= '1'; --- elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0f") ) then --- fifo_wr_en <= '1'; - elsif( (filter_current_state = DECIDE) and (frame_type_valid = '1') ) then - fifo_wr_en <= '1'; + if( MAC_RX_EN_IN = '1' ) then + if ( filter_current_state = SAVE_FRAME ) then + fifo_wr_en <= '1'; + elsif( (filter_current_state = DELAY) ) then + fifo_wr_en <= '1'; + else + fifo_wr_en <= '0'; + end if; else fifo_wr_en <= '0'; end if; - else - fifo_wr_en <= '0'; - end if; - - end if; -end process THE_RX_FIFO_SYNC; - -THE_SIZES_FIFO: entity fifo_512x32 -port map( - Data(15 downto 0) => rx_bytes_ctr, - Data(31 downto 16) => saved_frame_type, - WrClock => CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(15 downto 0) => fr_frame_size, - Q(31 downto 16) => fr_frame_proto, - Empty => sizes_fifo_empty, - Full => sizes_fifo_full -); - -THE_MACS_FIFO: entity fifo_512x72 -port map( - Data(47 downto 0) => saved_src_mac, - Data(63 downto 48) => saved_src_udp, - Data(71 downto 64) => (others => '0'), - WrClock => CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(47 downto 0) => fr_src_mac, - Q(63 downto 48) => fr_src_udp, - Q(71 downto 64) => xxx0, --open, - Empty => open, - Full => open -); - -THE_MACD_FIFO: entity fifo_512x72 -port map( - Data(47 downto 0) => saved_dest_mac, - Data(63 downto 48) => saved_dest_udp, - Data(71 downto 64) => (others => '0'), - WrClock => CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(47 downto 0) => fr_dest_mac, - Q(63 downto 48) => fr_dest_udp, - Q(71 downto 64) => xxx1, --open, - Empty => open, - Full => open -); - -THE_IP_FIFO: entity fifo_512x72 -port map( - Data(31 downto 0) => saved_src_ip, - Data(63 downto 32) => saved_dest_ip, - Data(71 downto 64) => saved_proto, - WrClock => CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(31 downto 0) => fr_src_ip, - Q(63 downto 32) => fr_dest_ip, - Q(71 downto 64) => fr_ip_proto, - Empty => open, - Full => open -); - -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - FR_SRC_IP_ADDRESS_OUT <= fr_src_ip; - FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip; - FR_IP_PROTOCOL_OUT <= fr_ip_proto; - FR_DEST_UDP_PORT_OUT <= fr_dest_udp; - FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac; - FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac; - FR_SRC_UDP_PORT_OUT <= fr_src_udp; - FR_FRAME_PROTO_OUT <= fr_frame_proto; - FR_FRAME_SIZE_OUT <= fr_frame_size; - FR_Q_OUT <= fr_q; - -- - delayed_frame_valid <= MAC_RX_EOF_IN; - delayed_frame_valid_q <= delayed_frame_valid; - end if; -end process THE_SYNC_PROC; -THE_FRAME_VALID_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( (MAC_RX_EOF_IN = '1') and (ALLOW_RX_IN = '1') and (frame_type_valid = '1') ) then - frame_valid_q <= '1'; - else - frame_valid_q <= '0'; end if; - end if; -end process THE_FRAME_VALID_PROC; + end process PROC_RX_FIFO_SYNC; + + THE_SIZES_FIFO: entity work.fifo_512x32 + port map( + Data(15 downto 0) => rx_bytes_ctr, + Data(31 downto 16) => saved_frame_type, + WrClock => CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(15 downto 0) => fr_frame_size, + Q(31 downto 16) => fr_frame_proto, + Empty => sizes_fifo_empty, + Full => sizes_fifo_full + ); + + THE_MACS_FIFO: entity work.fifo_512x72 + port map( + Data(47 downto 0) => saved_src_mac, + Data(63 downto 48) => saved_src_udp, + Data(71 downto 64) => (others => '0'), + WrClock => CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(47 downto 0) => fr_src_mac, + Q(63 downto 48) => fr_src_udp, + Q(71 downto 64) => xxx0, --open, + Empty => open, + Full => open + ); + + THE_MACD_FIFO: entity work.fifo_512x72 + port map( + Data(47 downto 0) => saved_dest_mac, + Data(63 downto 48) => saved_dest_udp, +-- Data(71 downto 64) => (others => '0'), + Data(69 downto 64) => proto_select, + Data(71 downto 70) => (others => '0'), + WrClock => CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(47 downto 0) => fr_dest_mac, + Q(63 downto 48) => fr_dest_udp, +-- Q(71 downto 64) => xxx1, --open, + Q(69 downto 64) => fr_ps, --open, + Q(71 downto 70) => xxx1(1 downto 0), --open, + Empty => open, + Full => open + ); + + THE_IP_FIFO: entity work.fifo_512x72 + port map( + Data(31 downto 0) => saved_src_ip, + Data(63 downto 32) => saved_dest_ip, + Data(71 downto 64) => saved_proto, + WrClock => CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(31 downto 0) => fr_src_ip, + Q(63 downto 32) => fr_dest_ip, + Q(71 downto 64) => fr_ip_proto, + Empty => open, + Full => open + ); + + PROC_SYNC: process( CLK ) + begin + if( rising_edge(CLK) ) then + FR_SRC_IP_ADDRESS_OUT <= fr_src_ip; + FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip; + FR_IP_PROTOCOL_OUT <= fr_ip_proto; + FR_DEST_UDP_PORT_OUT <= fr_dest_udp; + FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac; + FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac; + FR_SRC_UDP_PORT_OUT <= fr_src_udp; + FR_FRAME_PROTO_OUT <= fr_frame_proto; + FR_FRAME_SIZE_OUT <= fr_frame_size; + FR_Q_OUT <= fr_q; + FR_PS_OUT <= fr_ps; + -- + delayed_frame_valid <= MAC_RX_EOF_IN; + delayed_frame_valid_q <= delayed_frame_valid; +-- proto_select <= proto_select_x; + end if; + end process PROC_SYNC; + + -- Signal used to store auxiliary FIFO data at the end of frame + PROC_FRAME_VALID: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( (MAC_RX_EOF_IN = '1') and (ALLOW_RX_IN = '1') and (frame_type_valid = '1') ) then + frame_valid_q <= '1'; + else + frame_valid_q <= '0'; + end if; + end if; + end process PROC_FRAME_VALID; -THE_RX_BYTES_CTR_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - rx_bytes_ctr <= x"0001"; - elsif( rising_edge(CLK) ) then - if( delayed_frame_valid_q = '1' ) then + PROC_RX_BYTES_CTR: process( CLK, RESET ) + begin + if ( RESET = '1' ) then rx_bytes_ctr <= x"0001"; - elsif( fifo_wr_en = '1' ) then - rx_bytes_ctr <= rx_bytes_ctr + 1; + elsif( rising_edge(CLK) ) then + if( delayed_frame_valid_q = '1' ) then + rx_bytes_ctr <= x"0001"; + elsif( fifo_wr_en = '1' ) then + rx_bytes_ctr <= rx_bytes_ctr + 1; + end if; end if; - end if; -end process THE_RX_BYTES_CTR_PROC; - -THE_ERROR_FRAMES_CTR_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - error_frames_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - error_frames_ctr <= error_frames_ctr + 1; - end if; -end process THE_ERROR_FRAMES_CTR_PROC; - -FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK); - -THE_RECEIVED_FRAMES_CTR: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - dbg_rec_frames <= (others => '0'); - elsif( rising_edge(CLK) ) then - dbg_rec_frames <= dbg_rec_frames + 1; - end if; -end process THE_RECEIVED_FRAMES_CTR; - -THE_DROPPED_FRAMES_CTR: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - dbg_drp_frames <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( (filter_current_state = DECIDE) and (frame_type_valid = '0') ) then - dbg_drp_frames <= dbg_drp_frames + 1; + end process PROC_RX_BYTES_CTR; + + -- Bullshit counter. Count condition is missing. + PROC_ERROR_FRAMES_CTR: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + error_frames_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + error_frames_ctr <= error_frames_ctr + 1; end if; - end if; -end process THE_DROPPED_FRAMES_CTR; + end process PROC_ERROR_FRAMES_CTR; -MONITOR_DROPPED_OUT <= std_logic_vector(dbg_drp_frames); -MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames); -MONITOR_RX_BYTES_OUT <= std_logic_vector(mon_rec_bytes); + FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK); -THE_MON_REC_BYTES_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - mon_rec_bytes <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( fifo_wr_en = '1' ) then - mon_rec_bytes <= mon_rec_bytes + x"1"; + -- Bullshit counter. Count condition is missing. + PROC_RECEIVED_FRAMES_CTR: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + dbg_rec_frames <= (others => '0'); + elsif( rising_edge(CLK) ) then + dbg_rec_frames <= dbg_rec_frames + 1; end if; - end if; -end process; + end process PROC_RECEIVED_FRAMES_CTR; + + -- Counts dropped frames. + PROC_DROPPED_FRAMES_CTR: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + dbg_drp_frames <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( (filter_current_state = DELAY) and (frame_type_valid = '0') ) then + dbg_drp_frames <= dbg_drp_frames + 1; + end if; + end if; + end process PROC_DROPPED_FRAMES_CTR; + + MONITOR_DROPPED_OUT <= std_logic_vector(dbg_drp_frames); + MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames); + MONITOR_RX_BYTES_OUT <= std_logic_vector(mon_rec_bytes); + + -- Counts received bytes as payload. + PROC_MON_REC_BYTES: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + mon_rec_bytes <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( fifo_wr_en = '1' ) then + mon_rec_bytes <= mon_rec_bytes + x"1"; + end if; + end if; + end process PROC_MON_REC_BYTES; end gbe_frame_receiver_arch; diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index 852f3f0..b16e447 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -104,7 +104,6 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is signal rc_frame_size : std_logic_vector(15 downto 0); signal mc_frame_size : std_logic_vector(15 downto 0); signal rc_bytes_rec : std_logic_vector(31 downto 0); - signal rc_debug : std_logic_vector(63 downto 0); signal mc_transmit_ctrl : std_logic; signal rc_loading_done : std_logic; signal fr_get_frame : std_logic; @@ -169,6 +168,8 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is signal make_reset : std_logic; signal frame_pause : std_logic_vector(31 downto 0); + signal fr_ps_int : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + begin fc_ihl_version <= x"45"; @@ -254,8 +255,8 @@ begin FWD_READY_OUT => FWD_READY_OUT, FWD_FULL_OUT => FWD_FULL_OUT, -- - DEBUG_OUT(31 downto 0) => DEBUG_OUT, - DEBUG_OUT(63 downto 32) => open, + DEBUG_OUT(15 downto 0) => DEBUG_OUT(31 downto 16), + DEBUG_OUT(63 downto 16) => open, -- MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen ); @@ -353,6 +354,7 @@ begin FR_FRAME_SIZE_IN => fr_frame_size, FR_FRAME_PROTO_IN => fr_frame_proto, FR_IP_PROTOCOL_IN => fr_ip_proto, + FR_PS_IN => fr_ps_int, FR_SRC_MAC_ADDRESS_IN => fr_src_mac, FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, FR_SRC_IP_ADDRESS_IN => fr_src_ip, @@ -375,9 +377,9 @@ begin -- statistics FRAMES_RECEIVED_OUT => rc_frames_rec_ctr, BYTES_RECEIVED_OUT => rc_bytes_rec, - DEBUG_OUT => rc_debug + DEBUG_OUT => open ); - + THE_FRAME_RECEIVER: entity work.gbe_frame_receiver port map( CLK => CLK_125_IN, @@ -401,10 +403,11 @@ begin FR_FRAME_SIZE_OUT => fr_frame_size, FR_FRAME_PROTO_OUT => fr_frame_proto, FR_IP_PROTOCOL_OUT => fr_ip_proto, - FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, - FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, - FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, - FR_VLAN_ID_IN => (others => '0'), --vlan_id, + FR_PS_OUT => fr_ps_int, +-- FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, +-- FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, +-- FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, +-- FR_VLAN_ID_IN => (others => '0'), --vlan_id, -- FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, @@ -420,7 +423,10 @@ begin -- MONITOR_RX_BYTES_OUT => monitor_rx_bytes, MONITOR_RX_FRAMES_OUT => monitor_rx_frames, - MONITOR_DROPPED_OUT => monitor_dropped + MONITOR_DROPPED_OUT => monitor_dropped, + -- + DEBUG_OUT(15 downto 0) => DEBUG_OUT(15 downto 0), --open + DEBUG_OUT(31 downto 16) => open ); MONITOR_RX_FRAMES_OUT <= monitor_rx_frames; diff --git a/gbe_trb/base/gbe_main_control.vhd b/gbe_trb/base/gbe_main_control.vhd index 7658760..c364922 100644 --- a/gbe_trb/base/gbe_main_control.vhd +++ b/gbe_trb/base/gbe_main_control.vhd @@ -150,6 +150,15 @@ architecture gbe_main_control_arch of gbe_main_control is signal selector_debug : std_logic_vector(63 downto 0); begin + + DEBUG_OUT(63 downto 16) <= (others => '0'); + + DEBUG_OUT(15 downto 12) <= link_state; + DEBUG_OUT(11 downto 8) <= redirect_state; + DEBUG_OUT(7) <= '0'; + DEBUG_OUT(6) <= disable_redirect; + DEBUG_OUT(5 downto 0) <= RC_FRAME_PROTO_IN; + THE_PROTOCOL_SELECTOR: entity work.gbe_protocol_selector generic map( INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, @@ -231,8 +240,9 @@ begin -- gk 07.11.11 -- do not select any response constructors when dropping a frame - proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); - +-- proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); + proto_select <= RC_FRAME_PROTO_IN; + -- gk 07.11.11 -- we do not answer at all, unless we are in either ACTIVE or GET_ADDRESS state. -- in GET_ADDRESS state, we only answer on DHCP frames. @@ -312,6 +322,7 @@ begin when LOAD => redirect_state <= x"5"; + -- BUG: why not used Q(8) as stop bit? if( loaded_bytes_ctr = unsigned(RC_FRAME_SIZE_IN) - 1 ) then redirect_next_state <= WAIT_ONE; else @@ -371,8 +382,8 @@ begin if rising_edge(CLK) then if ( redirect_current_state = IDLE) then loaded_bytes_ctr <= (others => '0'); - elsif( ((redirect_current_state = LOAD) or (redirect_current_state = DROP)) and (rc_rd_en = '1') )then - loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; + elsif( ((redirect_current_state = LOAD) or (redirect_current_state = DROP)) and (rc_rd_en = '1') ) then -- STUPID HERE! is included already + loaded_bytes_ctr <= loaded_bytes_ctr + 1; end if; end if; end process PROC_LOADED_BYTES_CTR; @@ -586,6 +597,6 @@ begin -- END OF LINK STATE CONTROL --************* - DEBUG_OUT <= selector_debug; + --DEBUG_OUT <= selector_debug; end gbe_main_control_arch; diff --git a/gbe_trb/base/gbe_protocol_prioritizer.vhd b/gbe_trb/base/gbe_protocol_prioritizer.vhd index 612d122..956f725 100644 --- a/gbe_trb/base/gbe_protocol_prioritizer.vhd +++ b/gbe_trb/base/gbe_protocol_prioritizer.vhd @@ -5,7 +5,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; -use work.trb_net_components.all; +--use work.trb_net_components.all; use work.gbe_protocols.all; --******** @@ -53,7 +53,7 @@ begin CODE_OUT <= (others => '0'); end if; -- No. 3 = ICMP - elsif( PROTOCOL_CODE_IN = x"01") then -- ICMP + elsif( PROTOCOL_CODE_IN = x"01" ) then -- ICMP CODE_OUT(4) <= '1'; else CODE_OUT <= (others => '0'); diff --git a/gbe_trb/base/gbe_receive_control.vhd b/gbe_trb/base/gbe_receive_control.vhd index 4620fbf..2e3d504 100644 --- a/gbe_trb/base/gbe_receive_control.vhd +++ b/gbe_trb/base/gbe_receive_control.vhd @@ -5,200 +5,200 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; -use work.trb_net_components.all; use work.gbe_protocols.all; entity gbe_receive_control is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; --- signals to/from frame_receiver - RC_DATA_IN : in std_logic_vector(8 downto 0); - FR_RD_EN_OUT : out std_logic; - FR_FRAME_VALID_IN : in std_logic; - FR_GET_FRAME_OUT : out std_logic; - FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - - FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - -- signals to/from main controller - RC_RD_EN_IN : in std_logic; - RC_Q_OUT : out std_logic_vector(8 downto 0); - RC_FRAME_WAITING_OUT : out std_logic; - RC_LOADING_DONE_IN : in std_logic; - RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - -- statistics - FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - -- - DEBUG_OUT : out std_logic_vector(63 downto 0) -); + port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + -- signals to/from frame_receiver + RC_DATA_IN : in std_logic_vector(8 downto 0); + FR_RD_EN_OUT : out std_logic; + FR_FRAME_VALID_IN : in std_logic; + FR_GET_FRAME_OUT : out std_logic; + FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); + FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + FR_PS_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + -- signals to/from main controller + RC_RD_EN_IN : in std_logic; + RC_Q_OUT : out std_logic_vector(8 downto 0); + RC_FRAME_WAITING_OUT : out std_logic; + RC_LOADING_DONE_IN : in std_logic; + RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + -- statistics + FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + -- + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); end gbe_receive_control; architecture gbe_receive_control_arch of gbe_receive_control is -attribute syn_encoding : string; + attribute syn_encoding : string; -type load_states is (IDLE, PREPARE, WAIT_ONE, READY); -signal load_current_state, load_next_state : load_states; -attribute syn_encoding of load_current_state : signal is "onehot"; + type load_states is (IDLE, PREPARE, WAIT_ONE, READY); + signal load_current_state, load_next_state : load_states; + attribute syn_encoding of load_current_state : signal is "onehot"; -signal frames_received_ctr : unsigned(31 downto 0); -signal frames_readout_ctr : unsigned(31 downto 0); -signal bytes_rec_ctr : unsigned(31 downto 0); + signal frames_received_ctr : unsigned(31 downto 0); + signal frames_readout_ctr : unsigned(31 downto 0); + signal bytes_rec_ctr : unsigned(31 downto 0); -signal state : std_logic_vector(3 downto 0); -signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal reset_prioritizer : std_logic; -signal frame_waiting : std_logic; + signal state : std_logic_vector(3 downto 0); + signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal reset_prioritizer : std_logic; --- debug only -signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + -- debug only + signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); begin -FR_RD_EN_OUT <= RC_RD_EN_IN; -RC_Q_OUT <= RC_DATA_IN; -RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN; -RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN; -RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN; -RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; -RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN; -RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; -RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN; - -protocol_prioritizer: entity gbe_protocol_prioritizer -port map( - CLK => CLK, - RESET => reset_prioritizer, - -- - FRAME_TYPE_IN => FR_FRAME_PROTO_IN, - PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN, - UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN, - -- - CODE_OUT => proto_code -); - -reset_prioritizer <= '1' when load_current_state = IDLE else '0'; - -RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash - -LOAD_MACHINE_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - load_current_state <= IDLE; - elsif( rising_edge(CLK) ) then - load_current_state <= load_next_state; - end if; -end process LOAD_MACHINE_PROC; - -LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN ) -begin - case load_current_state is + FR_RD_EN_OUT <= RC_RD_EN_IN; + RC_Q_OUT <= RC_DATA_IN; + RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN; + RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN; + RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN; + RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; + RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN; + RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; + RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN; + +-- protocol_prioritizer: entity work.gbe_protocol_prioritizer +-- port map( +-- CLK => CLK, +-- RESET => reset_prioritizer, +-- -- +-- FRAME_TYPE_IN => FR_FRAME_PROTO_IN, +-- PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN, +-- UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN, +-- -- +-- CODE_OUT => proto_code +-- ); +-- +-- reset_prioritizer <= '1' when load_current_state = IDLE else '0'; +-- +-- RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash + + RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0'); + + LOAD_MACHINE_PROC: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + load_current_state <= IDLE; + elsif( rising_edge(CLK) ) then + load_current_state <= load_next_state; + end if; + end process LOAD_MACHINE_PROC; + + LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN ) + begin + case load_current_state is + + when IDLE => + state <= x"1"; + if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver + load_next_state <= PREPARE; + else + load_next_state <= IDLE; + end if; + + when PREPARE => -- prepare frame size + state <= x"2"; + load_next_state <= WAIT_ONE; + + when WAIT_ONE => + load_next_state <= READY; - when IDLE => - state <= x"1"; - if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver - load_next_state <= PREPARE; + when READY => -- wait for reading out the whole frame + state <= x"3"; + if( RC_LOADING_DONE_IN = '1' ) then + load_next_state <= IDLE; + else + load_next_state <= READY; + end if; + + end case; + end process LOAD_MACHINE; + + process( CLK ) + begin + if( rising_edge(CLK) ) then + if( load_current_state = PREPARE ) then + FR_GET_FRAME_OUT <= '1'; else - load_next_state <= IDLE; + FR_GET_FRAME_OUT <= '0'; end if; - when PREPARE => -- prepare frame size - state <= x"2"; - load_next_state <= WAIT_ONE; - - when WAIT_ONE => - load_next_state <= READY; - - when READY => -- wait for reading out the whole frame - state <= x"3"; - if( RC_LOADING_DONE_IN = '1' ) then - load_next_state <= IDLE; + if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then + RC_FRAME_WAITING_OUT <= '1'; else - load_next_state <= READY; + RC_FRAME_WAITING_OUT <= '0'; end if; - - end case; -end process LOAD_MACHINE; - -process( CLK ) -begin - if( rising_edge(CLK) ) then - if( load_current_state = PREPARE ) then - FR_GET_FRAME_OUT <= '1'; - else - FR_GET_FRAME_OUT <= '0'; end if; - - if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then - RC_FRAME_WAITING_OUT <= '1'; - else - RC_FRAME_WAITING_OUT <= '0'; + end process; + + FRAMES_REC_CTR_PROC: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frames_received_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( FR_FRAME_VALID_IN = '1' ) then + frames_received_ctr <= frames_received_ctr + 1; + end if; end if; - end if; -end process; + end process FRAMES_REC_CTR_PROC; -FRAMES_REC_CTR_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - frames_received_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( FR_FRAME_VALID_IN = '1' ) then - frames_received_ctr <= frames_received_ctr + 1; + FRAMES_READOUT_CTR_PROC: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frames_readout_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( RC_LOADING_DONE_IN = '1' ) then + frames_readout_ctr <= frames_readout_ctr + 1; + end if; end if; - end if; -end process FRAMES_REC_CTR_PROC; - -FRAMES_READOUT_CTR_PROC: process( CLK, RESET ) -begin - if ( RESET = '1' ) then - frames_readout_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( RC_LOADING_DONE_IN = '1' ) then - frames_readout_ctr <= frames_readout_ctr + 1; - end if; - end if; -end process FRAMES_READOUT_CTR_PROC; - --- debug only -BYTES_REC_CTR_PROC : process( CLK ) -begin - if ( RESET = '1' ) then - bytes_rec_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( FR_FRAME_VALID_IN = '1' ) then - bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN); + end process FRAMES_READOUT_CTR_PROC; + + -- debug only + BYTES_REC_CTR_PROC : process( CLK ) + begin + if ( RESET = '1' ) then + bytes_rec_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( FR_FRAME_VALID_IN = '1' ) then + bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN); + end if; end if; - end if; -end process BYTES_REC_CTR_PROC; - -SAVED_PROTO_PROC : process( CLK ) -begin - if( rising_edge(CLK) ) then - if( load_current_state = READY ) then - if( and_all(proto_code) = '0' ) then - saved_proto <= proto_code; + end process BYTES_REC_CTR_PROC; + + SAVED_PROTO_PROC : process( CLK ) + begin + if( rising_edge(CLK) ) then + if( load_current_state = READY ) then + if( and_all(proto_code) = '0' ) then + saved_proto <= proto_code; + else + saved_proto <= (others => '0'); + end if; else - saved_proto <= (others => '0'); + saved_proto <= saved_proto; end if; - else - saved_proto <= saved_proto; end if; - end if; -end process SAVED_PROTO_PROC; + end process SAVED_PROTO_PROC; end gbe_receive_control_arch; diff --git a/gbe_trb/base/gbe_sci_reader.vhd b/gbe_trb/base/gbe_sci_reader.vhd index f1adca5..22c910a 100644 --- a/gbe_trb/base/gbe_sci_reader.vhd +++ b/gbe_trb/base/gbe_sci_reader.vhd @@ -2,10 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library work; - use work.trb_net_components.all; - use work.trb_net_std.all; - use work.trb3_components.all; +library work; use work.trb_net_std.all; use work.config.all; entity gbe_sci_reader is diff --git a/gbe_trb/base/gbe_tx_fifo.vhd b/gbe_trb/base/gbe_tx_fifo.vhd new file mode 100644 index 0000000..37c0764 --- /dev/null +++ b/gbe_trb/base/gbe_tx_fifo.vhd @@ -0,0 +1,122 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +-- BUG: if no frame is stored in FIFO, and filling the FIFO triggers FIFOFULL, +-- the frame must be written completely but dropped. +-- Otherwise we experience a deadlock in data transfer. + +-- BUG: use dynamic ALMOSTFULL to accommodate for pipelining inside the data +-- multiplexer of hub. +-- FIX: ALMOSTFULL is set at 4092, so we have at least three clocks + +-- OPTIMIZE: we can start transfering data to the MAC once 16bytes (or similar) +-- have been written. +-- The MAC needs a preread and then a continous data stream. + +entity gbe_tx_fifo is + port( + CLK : in std_logic; + RESET : in std_logic; + -- MAC interface + MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); + MAC_TX_READ_IN : in std_logic; + MAC_FIFOEOF_OUT : out std_logic; -- end of frame marker + MAC_FIFOEMPTY_OUT : out std_logic; -- must never happen during TX + MAC_FIFOAVAIL_OUT : out std_logic; -- starts TX process in MAC + MAC_TX_DONE_IN : in std_logic; -- frame sent + -- FIFO interface + FIFO_FULL_OUT : out std_logic; + FIFO_WR_IN : in std_logic; + FIFO_D_IN : in std_logic_vector(8 downto 0); + -- Link stuff + FRAME_START_IN : in std_logic; + LINK_ACTIVE_IN : in std_logic + ); +end entity gbe_tx_fifo; + +architecture gbe_tx_fifo_arch of gbe_tx_fifo is + +-- state machine signals + +-- Signals + signal frames_avail : unsigned(7 downto 0); + signal frame_written_x : std_logic; + signal frame_written : std_logic; + signal frame_read : std_logic; + signal mac_fifoeof : std_logic; + signal mac_tx_read : std_logic; + signal frame_active : std_logic; + signal fifo_wr : std_logic; + signal no_frames_x : std_logic; + +begin + + -- FrameActice signal - used to inhibit acceptance of runt frames + PROC_FRAME_ACTIVE: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frame_active <= '0'; + elsif( rising_edge(CLK) ) then + if ( FRAME_START_IN = '1' ) then + frame_active <= LINK_ACTIVE_IN; + elsif( frame_written = '1' ) then + frame_active <= '0'; + end if; + end if; + end process PROC_FRAME_ACTIVE; + + fifo_wr <= FIFO_WR_IN and frame_active; + + -- TX FIFO storing full outgoing frames + THE_TX_FIFO: entity work.fifo_4k_9 + port map( + DATA => FIFO_D_IN, + CLOCK => CLK, + WREN => fifo_wr, + RDEN => MAC_TX_READ_IN, + RESET => RESET, + Q(8) => mac_fifoeof, -- potential bug!!!! + Q(7 downto 0) => MAC_TX_DATA_OUT, + EMPTY => MAC_FIFOEMPTY_OUT, + FULL => open, + ALMOSTFULL => FIFO_FULL_OUT + ); + + MAC_FIFOEOF_OUT <= mac_fifoeof; + + mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK); + + -- one frame written to FIFO + frame_written_x <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0'; -- HERE + + frame_written <= frame_written_x when rising_edge(CLK); + + -- one frame read from FIFO + frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0'; + + -- FramesAvailable counter + PROC_FRAMES_AVAIL: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + frames_avail <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( (frame_written = '1') and (frame_read = '0') ) then + -- one frame written successfully + frames_avail <= frames_avail + 1; + elsif( (frame_written = '0') and (frame_read = '1') ) then + -- one frame read successfully + frames_avail <= frames_avail - 1; + end if; + end if; + end process PROC_FRAMES_AVAIL; + + MAC_FIFOAVAIL_OUT <= '1' when (frames_avail /= x"00") else '0'; + + -- Bugfix: dropped partially stored frame, if it is the only frame and we run into FIFO full condition + no_frames_x <= '1' when (frames_avail = x"00") else '0'; + + +end architecture; diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd index c93874d..f2098be 100644 --- a/gbe_trb/base/inserter.vhd +++ b/gbe_trb/base/inserter.vhd @@ -27,22 +27,6 @@ end entity inserter; architecture inserter_arch of inserter is --- Components - component fifo_inserter - port( - DATA : in std_logic_vector(9 downto 0); - CLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; - WCNT : out std_logic_vector(4 downto 0); - Q : out std_logic_vector(9 downto 0); - EMPTY : out std_logic; - FULL : out std_logic; - ALMOSTEMPTY : out std_logic - ); - end component fifo_inserter; - -- Signals signal tx_cd_int : std_logic; signal tx_k_int : std_logic; @@ -92,7 +76,7 @@ begin DEBUG_OUT(15 downto 9) <= (others => '0'); -- Syncing and delaying signals for /I/ recognition - THE_SYNC_PROC: process( CLK ) + PROC_SYNC: process( CLK ) begin if( rising_edge(CLK) ) then -- synced active signal @@ -109,7 +93,7 @@ begin idle_int <= idle_x; remove_int <= remove_x; end if; - end process THE_SYNC_PROC; + end process PROC_SYNC; -- sync reset rst_n_int <= active_int(2); @@ -121,7 +105,7 @@ begin else '0'; -- insert counter - THE_INSERT_COUNTER_PROC: process( CLK ) + PROC_INSERT_COUNTER: process( CLK ) begin if( rising_edge(CLK) ) then if ( rst_int = '1' ) then @@ -132,10 +116,10 @@ begin ins_cnt <= ins_cnt - 1; end if; end if; - end process THE_INSERT_COUNTER_PROC; + end process PROC_INSERT_COUNTER; -- store the payload - THE_PAYLOAD_PROC: process( CLK ) + PROC_PAYLOAD: process( CLK ) begin if( rising_edge(CLK) ) then if ( rst_int = '1' ) then @@ -144,7 +128,7 @@ begin payload <= DLM_DATA_IN; end if; end if; - end process THE_PAYLOAD_PROC; + end process PROC_PAYLOAD; -- we need to drop at least one /I/ drop_req_x <= '1' when (ins_cnt /= b"000") else '0'; @@ -154,7 +138,7 @@ begin fifo_wr_x <= '0' when ((remove_x = '1') or (remove_int = '1')) else '1'; -- FIFO - THE_FIFO: fifo_inserter + THE_FIFO: entity work.fifo_inserter port map( DATA => delay_qqq, CLOCK => CLK, diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd index 3fc1678..8c1996b 100644 --- a/gbe_trb/base/remover.vhd +++ b/gbe_trb/base/remover.vhd @@ -25,22 +25,6 @@ end entity remover; architecture remover_arch of remover is --- Components - component fifo_remover - port( - DATA : in std_logic_vector(8 downto 0); - CLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(4 downto 0); - EMPTY : out std_logic; - FULL : out std_logic; - ALMOSTFULL : out std_logic - ); - end component fifo_remover; - -- state machine signals type state_t is (FILL, IDLE, ONE, TWO, THREE); signal STATE, NEXT_STATE : state_t; @@ -81,13 +65,13 @@ begin DEBUG_OUT(15 downto 6) <= (others => '0'); -- Syncing - THE_SYNC_PROC: process( CLK ) + PROC_SYNC: process( CLK ) begin if( rising_edge(CLK) ) then -- synced active signal active_int <= active_int(1 downto 0) & ACTIVE_IN; end if; - end process THE_SYNC_PROC; + end process PROC_SYNC; -- sync reset rst_n_int <= active_int(2); @@ -104,7 +88,7 @@ begin DLM_FOUND_OUT <= dlm_found when rising_edge(CLK); -- needed to have valid data - THE_STORE_PROC: process( CLK ) + PROC_STORE: process( CLK ) begin if( rising_edge(CLK) ) then if ( rst_int = '1' ) then @@ -113,7 +97,7 @@ begin dlm_data_int <= rx_d_int; end if; end if; - end process THE_STORE_PROC; + end process PROC_STORE; DLM_DATA_OUT <= dlm_data_int; @@ -121,7 +105,7 @@ begin fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1'; -- FIFO - THE_FIFO: fifo_remover + THE_FIFO: entity work.fifo_remover port map( DATA(8) => rx_k_int, DATA(7 downto 0) => rx_d_int, @@ -158,7 +142,7 @@ begin ----------------------------------------------------------- -- statemachine: clocked process ----------------------------------------------------------- - THE_FSM: process( CLK ) + PROC_FSM: process( CLK ) begin if( rising_edge(CLK) ) then if( rst_int = '1' ) then @@ -171,12 +155,12 @@ begin replace_d <= replace_d_x; end if; end if; - end process THE_FSM; + end process PROC_FSM; ----------------------------------------------------------- -- staemachine: transitions ----------------------------------------------------------- - THE_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull ) + PROC_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull ) begin replace_k_x <= '0'; replace_d_x <= '0'; @@ -219,6 +203,6 @@ begin when others => NEXT_STATE <= IDLE; end case; - end process THE_STATE_TRANSITIONS; + end process PROC_STATE_TRANSITIONS; end architecture; diff --git a/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd b/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd index a9ffaf9..c5291f1 100644 --- a/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd @@ -128,8 +128,8 @@ begin vendor_values(79 downto 56) <= x"01073d"; -- client identifier vendor_values(127 downto 80) <= MY_MAC_IN; -- client identifier vendor_values(143 downto 128) <= x"040c"; -- client name - --vendor_values(175 downto 144) <= x"33425254"; -- client name (TRB3) - vendor_values(175 downto 144) <= x"6f72694b"; -- client name (Kiro) + vendor_values(175 downto 144) <= x"33425254"; -- client name (TRB3) + --vendor_values(175 downto 144) <= x"6f72694b"; -- client name (Kiro) vendor_values2(15 downto 0) <= x"0436"; -- server identifier vendor_values2(47 downto 16) <= saved_server_ip; diff --git a/gbe_trb/protocols/gbe_response_constructor_Forward.vhd b/gbe_trb/protocols/gbe_response_constructor_Forward.vhd index 0ed6aa4..04459c2 100644 --- a/gbe_trb/protocols/gbe_response_constructor_Forward.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_Forward.vhd @@ -86,16 +86,16 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F begin - DISSECT_MACHINE_PROC: process( CLK, RESET ) + PROC_DISSECT_FSM: process( CLK, RESET ) begin - if( RESET = '1' ) then + if ( RESET = '1' ) then dissect_current_state <= IDLE; elsif( rising_edge(CLK) ) then dissect_current_state <= dissect_next_state; end if; - end process DISSECT_MACHINE_PROC; + end process PROC_DISSECT_FSM; - DISSECT_MACHINE: process(dissect_current_state, FWD_SOP_IN, FWD_EOP_IN, ff_q, ff_rd_lock, PS_SELECTED_IN) + PROC_DISSECT_TRANSITIONS: process( dissect_current_state, FWD_SOP_IN, FWD_EOP_IN, ff_q, ff_rd_lock, PS_SELECTED_IN ) begin case dissect_current_state is @@ -136,15 +136,13 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F dissect_next_state <= IDLE; end case; - end process DISSECT_MACHINE; + end process PROC_DISSECT_TRANSITIONS; PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; + ff_wr_en <= '1' when (FWD_DATA_VALID_IN = '1') else '0'; + local_eop <= '1' when (dissect_current_state = SAVE and FWD_EOP_IN = '1' and FWD_DATA_VALID_IN = '1') else '0'; - ff_wr_en <= '1' when (FWD_DATA_VALID_IN = '1') else '0'; - - local_eop <= '1' when (dissect_current_state = SAVE and FWD_EOP_IN = '1' and FWD_DATA_VALID_IN = '1') else '0'; - - FF_RD_LOCK_PROC: process( CLK, RESET ) + PROC_FF_RD_LOCK: process( CLK, RESET ) begin if ( RESET = '1' ) then ff_rd_lock <= '1'; @@ -155,9 +153,9 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F ff_rd_lock <= '1'; end if; end if; - end process FF_RD_LOCK_PROC; + end process PROC_FF_RD_LOCK; - FRAME_FIFO: entity fifo_4096x9 + THE_FRAME_FIFO: entity fifo_4096x9 port map( Data(7 downto 0) => FWD_DATA_IN, Data(8) => local_eop, @@ -174,14 +172,11 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0'; - --TC_DATA_OUT <= ff_q; -- BUG?!? TC_DATA_OUT <= ff_q when rising_edge(CLK); PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0'; - --TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1"; -- BUG?!? - TC_FRAME_SIZE_OUT <= resp_bytes_ctr; - + TC_FRAME_SIZE_OUT <= resp_bytes_ctr; TC_FRAME_TYPE_OUT <= x"0008"; TC_DEST_MAC_OUT <= FWD_DST_MAC_IN; TC_DEST_IP_OUT <= FWD_DST_IP_IN; @@ -192,7 +187,7 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F TC_IP_PROTOCOL_OUT <= x"11"; TC_IDENT_OUT <= x"6" & sent_frames(11 downto 0); - RESP_BYTES_CTR_PROC: process( CLK, RESET ) + PROC_RESP_BYTES_CTR: process( CLK, RESET ) begin if ( RESET = '1' ) then resp_bytes_ctr <= (others => '0'); @@ -212,9 +207,9 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F end if; end if; - end process RESP_BYTES_CTR_PROC; + end process PROC_RESP_BYTES_CTR; - REC_FRAMES_PROC: process( CLK, RESET ) + PROC_REC_FRAMES: process( CLK, RESET ) begin if ( RESET = '1' ) then rec_frames <= (others => '0'); @@ -223,9 +218,9 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F rec_frames <= rec_frames + x"1"; end if; end if; - end process REC_FRAMES_PROC; + end process PROC_REC_FRAMES; - SENT_FRAMES_PROC: process( CLK, RESET ) + PROC_SENT_FRAMES: process( CLK, RESET ) begin if ( RESET = '1' ) then sent_frames <= (others => '0'); @@ -234,7 +229,7 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F sent_frames <= sent_frames + x"1"; end if; end if; - end process SENT_FRAMES_PROC; + end process PROC_SENT_FRAMES; RECEIVED_FRAMES_OUT <= rec_frames; SENT_FRAMES_OUT <= sent_frames; diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd index 4054fb4..d10a697 100644 --- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd @@ -363,7 +363,7 @@ begin ------------------------------------------------- -- SerDes quad ------------------------------------------------- - gbe_serdes: entity serdes_gbe_4ch_ds + THE_GBE_SERDES: entity work.serdes_gbe_4ch_ds port map( -- CH0 -- hdinp_ch0 => SD_RXD_P_IN(0), @@ -524,7 +524,7 @@ begin WAP_OUT <= wa_position_i; -- in case we have no uplink port, no local port is generated - NO_LOCAL_GEN: if (quad_mode < 8) generate + NO_LOCAL_GEN: if( quad_mode < 8 ) generate MAC_RX_DATA_OUT <= (others => '0'); MAC_RX_WRITE_OUT <= '0'; MAC_RX_EOF_OUT <= '0'; @@ -532,9 +532,9 @@ begin end generate NO_LOCAL_GEN; -- generate master and slave channel, i.e. active SerDes connections - CHANNEL_GEN : for i in 0 to 3 generate + CHANNEL_GEN: for i in 0 to 3 generate - CHANNEL_ACTIVE_GEN : if ((LINK_MODE(i) = c_IS_SLAVE) or (LINK_MODE(i) = c_IS_MASTER)) generate + CHANNEL_ACTIVE_GEN: if( (LINK_MODE(i) = c_IS_SLAVE) or (LINK_MODE(i) = c_IS_MASTER) ) generate -- Debug signals, MSB to LSB DEBUG_OUT(i * 32 + 31) <= '0'; -- (31) @@ -575,7 +575,7 @@ begin -- RSL for RX of SerDes, based on extRSL logic -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock! - THE_MAIN_RX_RST: main_rx_reset_RS + THE_GBE_RX_RST: entity work.gbe_rx_reset port map( CLEAR => CLEAR, CLK_REF => CLK_125, -- needs always to run on local clock @@ -611,7 +611,7 @@ begin --- Trudy and Eve ------------------------------------------ ------------------------------------------------------------ TRUDY_AND_EVE: if INCLUDE_DLM(i) = 1 generate - THE_TRUDY: entity inserter + THE_TRUDY: entity work.inserter port map( CLK => MASTER_CLK_IN, CLEAR => CLEAR, -- MUST NOT BE RESET! @@ -631,7 +631,7 @@ begin DEBUG_OUT => open ); - THE_EVE: entity remover + THE_EVE: entity work.remover port map( CLK => sd_rx_clk(i), CLEAR => CLEAR, -- MUST NOT BE RESET! @@ -659,7 +659,7 @@ begin end generate NO_TRUDY_AND_EVE; -- SGMII core - SGMII_GBE_PCS : sgmii_gbe_pcs42 + THE_SGMII_GBE_PCS: sgmii_gbe_pcs42 port map( rst_n => CLEAR_N, --RESET_N, -- CHECKIFWORKS signal_detect => serdes_active(i), @@ -712,7 +712,7 @@ begin ); -- TSMAC core - MAC: tsmac41 + THE_MAC: tsmac41 port map( ----------------- clock and reset port declarations ------------------ hclk => MASTER_CLK_IN, @@ -766,7 +766,7 @@ begin ); -- responsible for loading the TSMAC registers - THE_GBE_MAC_CONTROL: entity gbe_mac_control + THE_GBE_MAC_CONTROL: entity work.gbe_mac_control port map( CLK => MASTER_CLK_IN, RESET => CLEAR, --RESET, -- CHECKIFWORKS @@ -787,7 +787,7 @@ begin ); -- initializes MAC after AN is complete - THE_FW_GBE_LSM: entity gbe_lsm + THE_FW_GBE_LSM: entity work.gbe_lsm port map( CLK => MASTER_CLK_IN, RESET => CLEAR, --RESET, -- CHECKIFWORKS @@ -825,7 +825,7 @@ begin ); -- TX FIFO - THE_FW_FIFO: entity tx_fifo + THE_FW_FIFO: entity work.gbe_tx_fifo port map( CLK => MASTER_CLK_IN, RESET => CLEAR, --RESET, -- CHECKIFWORKS diff --git a/media_interfaces/sync/gbe_rx_reset.vhd b/media_interfaces/sync/gbe_rx_reset.vhd new file mode 100644 index 0000000..7e947d1 --- /dev/null +++ b/media_interfaces/sync/gbe_rx_reset.vhd @@ -0,0 +1,250 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.all; + +entity gbe_rx_reset is + port ( + CLEAR : in std_logic; -- do not use + CLK_REF : in std_logic; -- usually local oscillator sourced + CDR_LOL_IN : in std_logic; + CV_IN : in std_logic; + LSM_IN : in std_logic; + LOS_IN : in std_logic; + WAP_ZERO_IN : in std_logic; + -- outputs + WAP_REQ_OUT : out std_logic; + RX_SERDES_RST_OUT : out std_logic; + RX_PCS_RST_OUT : out std_logic; + LINK_RX_READY_OUT : out std_logic; + STATE_OUT : out std_logic_vector(3 downto 0) + ); +end entity gbe_rx_reset; + +architecture gbe_rx_reset_arch of gbe_rx_reset is + + attribute syn_keep : boolean; + +-- Remark: work of Christian Michel. Just re-edited to reflect necessary changes for ECP3. +-- Without this piece of code, many things would have been a real pain. + + constant Tshort_bit : integer := 4; -- count up to 2^4 = 16 + constant Tplol_bit : integer := 22; + constant Tcdr_bit : integer := 22; + constant Tviol_bit : integer := 22; + + signal cdr_lol_s : std_logic; + signal cv_s : std_logic; + signal lsm_s : std_logic; + signal los_s : std_logic; + signal wap_zero_s : std_logic; + + signal cnt : unsigned(31 downto 0); + + type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, + APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, + CHECK_WAP, NORMAL_OP); + + signal rx_sm : rx_sm_state; + + attribute syn_keep of rx_sm : signal is true; + +begin + +-- Remark: on ECP3, rx_serdes_rst sets RX_CDR_LOL. Deadlocks on POWERUP. +-- Remark: syncing is done here by one FF only. Might be dangerous. + +------------------------------------------------------------------ + PROC_RX_RESET: process( CLEAR, CLK_REF ) + begin + if( CLEAR = '1' ) then + cdr_lol_s <= '1'; + cv_s <= '1'; + lsm_s <= '0'; + los_s <= '1'; + wap_zero_s <= '0'; + + RX_SERDES_RST_OUT <= '1'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + + rx_sm <= POWERUP; + STATE_OUT <= x"f"; + cnt <= (others => '0'); + elsif( rising_edge(CLK_REF) ) then + cdr_lol_s <= CDR_LOL_IN; + cv_s <= CV_IN; + lsm_s <= LSM_IN; + los_s <= LOS_IN; + wap_zero_s <= WAP_ZERO_IN; + + case rx_sm is + when POWERUP => + STATE_OUT <= x"0"; + RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + if( (los_s = '1') ) then -- seems to work + cnt <= (others => '0'); + else + if( cnt(Tplol_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= APPLY_CDR_RST; + else + cnt <= cnt + 1; + end if; + end if; + + when APPLY_CDR_RST => + STATE_OUT <= x"1"; + RX_SERDES_RST_OUT <= '1'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + if( cnt(Tshort_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= WAIT_CDR_LOCK; + else + cnt <= cnt + 1; + end if; + + when WAIT_CDR_LOCK => + STATE_OUT <= x"2"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + if( cnt(Tcdr_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= TEST_CDR; + else + cnt <= cnt + 1; + end if; + + when TEST_CDR => + STATE_OUT <= x"3"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cdr_lol_s = '1' ) then + cnt <= (others => '0'); + rx_sm <= APPLY_CDR_RST; + else + if( cnt(Tcdr_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= APPLY_RXPCS_RST; + else + cnt <= cnt + 1; + end if; + end if; + + when APPLY_RXPCS_RST => + STATE_OUT <= x"4"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cnt(Tshort_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= WAIT_RXPCS_LOCK; + else + cnt <= cnt + 1; + end if; + + when WAIT_RXPCS_LOCK => + STATE_OUT <= x"5"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cnt(Tviol_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= TEST_RXPCS; + else + cnt <= cnt + 1; + end if; + + when TEST_RXPCS => + STATE_OUT <= x"6"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '1'; + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( (lsm_s = '0') or (cv_s = '1') ) then + cnt <= (others => '0'); + rx_sm <= APPLY_RXPCS_RST; + else + if( cnt(Tviol_bit) = '1' ) then + cnt <= (others => '0'); + rx_sm <= CHECK_WAP; + else + cnt <= cnt + 1; + end if; + end if; + + when CHECK_WAP => + STATE_OUT <= x"7"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + cnt <= (others => '0'); + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cnt(Tshort_bit) = '1' ) then + cnt <= (others => '0'); + if( wap_zero_s = '1' ) then + rx_sm <= NORMAL_OP; + else + rx_sm <= APPLY_CDR_RST; + end if; + else + cnt <= cnt + 1; + rx_sm <= CHECK_WAP; + end if; + + when NORMAL_OP => + STATE_OUT <= x"8"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '1'; + WAP_REQ_OUT <= '0'; + cnt <= (others => '0'); + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( (lsm_s = '0') or (cv_s = '1') ) then -- DANGEROUS + rx_sm <= APPLY_RXPCS_RST; + end if; + + when others => + -- just in case + STATE_OUT <= x"f"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + WAP_REQ_OUT <= '0'; + rx_sm <= POWERUP; + cnt <= (others => '0'); + + end case; + + end if; + end process PROC_RX_RESET; + +end architecture gbe_rx_reset_arch; diff --git a/trb_net16_regio_bus_handler_record.vhd b/trb_net16_regio_bus_handler_record.vhd index 2f47e92..6d9a3d0 100644 --- a/trb_net16_regio_bus_handler_record.vhd +++ b/trb_net16_regio_bus_handler_record.vhd @@ -11,7 +11,7 @@ entity trb_net16_regio_bus_handler_record is PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0); PORT_MASK_ENABLE : integer range 0 to 1 := 0 - ); + ); port( CLK : in std_logic; RESET : in std_logic; @@ -23,8 +23,8 @@ entity trb_net16_regio_bus_handler_record is BUS_TX : in ctrlbus_tx_array_t(0 to PORT_NUMBER-1); STAT_DEBUG : out std_logic_vector(31 downto 0) - ); -end entity; + ); +end entity trb_net16_regio_bus_handler_record; -- type CTRLBUS_TX is record @@ -75,84 +75,78 @@ begin --Decode Addresses --------------------------------------------------------------------- - proc_port_select : process(REGIO_RX.addr) - begin - next_port_select_int <= PORT_NUMBER; - gen_port_select : for i in 0 to PORT_NUMBER-1 loop - if (PORT_ADDR_MASK(i) = 16 or - (REGIO_RX.addr(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)))) then - next_port_select_int <= i; - end if; - end loop; - end process; + PROC_PORT_SELECT: process( REGIO_RX.addr ) + begin + next_port_select_int <= PORT_NUMBER; + GEN_PORT_SELECT : for i in 0 to PORT_NUMBER-1 loop + if (PORT_ADDR_MASK(i) = 16 or + (REGIO_RX.addr(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)))) then + next_port_select_int <= i; + end if; + end loop; + end process PROC_PORT_SELECT; --------------------------------------------------------------------- --Generate R/W strobes --------------------------------------------------------------------- - proc_rw_signals : process(CLK) - begin - if rising_edge(CLK) then --- if RESET = '1' then --- buf_BUS_READ_OUT <= (others => '0'); --- buf_BUS_WRITE_OUT <= (others => '0'); --- port_select_int <= PORT_NUMBER; --- else - buf_BUS_READ_OUT <= (others => '0'); - buf_BUS_WRITE_OUT <= (others => '0'); - if REGIO_RX.write = '1' or REGIO_RX.read = '1' then - buf_BUS_DATA_OUT <= REGIO_RX.data; - buf_BUS_ADDR_OUT <= REGIO_RX.addr; - port_select_int <= next_port_select_int; - end if; - if REGIO_RX.read = '1' then - buf_BUS_READ_OUT(next_port_select_int) <= '1'; - end if; - if REGIO_RX.write = '1' then - buf_BUS_WRITE_OUT(next_port_select_int) <= '1'; - end if; - if (buf_BUS_DATAREADY_IN(port_select_int) or - buf_BUS_WRITE_ACK_IN(port_select_int) or - buf_BUS_UNKNOWN_ADDR_IN(port_select_int) or - buf_BUS_NO_MORE_DATA_IN(port_select_int)) = '1' then - port_select_int <= PORT_NUMBER; - end if; - end if; --- end if; - end process; + PROC_RW_SIGNALS: process( CLK ) + begin + if( rising_edge(CLK) ) then + buf_BUS_READ_OUT <= (others => '0'); + buf_BUS_WRITE_OUT <= (others => '0'); + if REGIO_RX.write = '1' or REGIO_RX.read = '1' then + buf_BUS_DATA_OUT <= REGIO_RX.data; + buf_BUS_ADDR_OUT <= REGIO_RX.addr; + port_select_int <= next_port_select_int; + end if; + if REGIO_RX.read = '1' then + buf_BUS_READ_OUT(next_port_select_int) <= '1'; + end if; + if REGIO_RX.write = '1' then + buf_BUS_WRITE_OUT(next_port_select_int) <= '1'; + end if; + if (buf_BUS_DATAREADY_IN(port_select_int) or + buf_BUS_WRITE_ACK_IN(port_select_int) or + buf_BUS_UNKNOWN_ADDR_IN(port_select_int) or + buf_BUS_NO_MORE_DATA_IN(port_select_int)) = '1' then + port_select_int <= PORT_NUMBER; + end if; + end if; + end process PROC_RW_SIGNALS; --------------------------------------------------------------------- --Map Data Outputs --------------------------------------------------------------------- - gen_outputs : for i in 0 to PORT_NUMBER-1 generate + GEN_OUTPUTS: for i in 0 to PORT_NUMBER-1 generate BUS_RX(i).read <= buf_BUS_READ_OUT(i); BUS_RX(i).write <= buf_BUS_WRITE_OUT(i); BUS_RX(i).data <= buf_BUS_DATA_OUT; BUS_RX(i).timeout <= REGIO_RX.timeout; - port_mask_disabled : if PORT_MASK_ENABLE = 0 generate + PORT_MASK_DISABLED: if PORT_MASK_ENABLE = 0 generate BUS_RX(i).addr <= buf_BUS_ADDR_OUT; end generate; - port_mask_enabled : if PORT_MASK_ENABLE = 1 and PORT_ADDR_MASK(i) /= 0 generate + PORT_MASK_ENABLED: if PORT_MASK_ENABLE = 1 and PORT_ADDR_MASK(i) /= 0 generate BUS_RX(i).addr(PORT_ADDR_MASK(i)-1 downto 0) <= buf_BUS_ADDR_OUT(PORT_ADDR_MASK(i)-1 downto 0); BUS_RX(i).addr(15 downto PORT_ADDR_MASK(i)) <= (others => '0'); end generate; - port_mask_enabled_2 : if PORT_MASK_ENABLE = 1 and PORT_ADDR_MASK(i) = 0 generate + PORT_MASK_ENABLED_2 : if PORT_MASK_ENABLE = 1 and PORT_ADDR_MASK(i) = 0 generate BUS_RX(i).addr(15 downto 0) <= (others => '0'); end generate; - end generate; + end generate GEN_OUTPUTS; --------------------------------------------------------------------- --Pack Data Inputs and Dummy Input --------------------------------------------------------------------- - gen_inputs : for i in 0 to PORT_NUMBER-1 generate + GEN_INPUTS: for i in 0 to PORT_NUMBER-1 generate buf_BUS_DATA_IN(i*32+31 downto i*32) <= BUS_TX(i).data; buf_BUS_DATAREADY_IN(i) <= BUS_TX(i).ack or BUS_TX(i).rack; buf_BUS_WRITE_ACK_IN(i) <= BUS_TX(i).ack or BUS_TX(i).wack; buf_BUS_NO_MORE_DATA_IN(i) <= BUS_TX(i).nack; buf_BUS_UNKNOWN_ADDR_IN(i) <= BUS_TX(i).unknown; - end generate; + end generate GEN_INPUTS; buf_BUS_DATA_IN(PORT_NUMBER*32+31 downto PORT_NUMBER*32) <= (others => '0'); buf_BUS_DATAREADY_IN(PORT_NUMBER) <= '0'; @@ -160,20 +154,19 @@ begin buf_BUS_NO_MORE_DATA_IN(PORT_NUMBER) <= '0'; buf_BUS_UNKNOWN_ADDR_IN(PORT_NUMBER) <= buf_BUS_READ_OUT(PORT_NUMBER) or buf_BUS_WRITE_OUT(PORT_NUMBER); - --------------------------------------------------------------------- --Multiplex Data Output --------------------------------------------------------------------- - proc_reg_output_signals : process(CLK) - begin - if rising_edge(CLK) then - REGIO_TX.data <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32); - REGIO_TX.ack <= buf_BUS_DATAREADY_IN(port_select_int) or buf_BUS_WRITE_ACK_IN(port_select_int); - REGIO_TX.nack <= buf_BUS_NO_MORE_DATA_IN(port_select_int); - REGIO_TX.unknown <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int); - end if; - end process; + PROC_REG_OUTPUT_SIGNALS: process( CLK ) + begin + if rising_edge(CLK) then + REGIO_TX.data <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32); + REGIO_TX.ack <= buf_BUS_DATAREADY_IN(port_select_int) or buf_BUS_WRITE_ACK_IN(port_select_int); + REGIO_TX.nack <= buf_BUS_NO_MORE_DATA_IN(port_select_int); + REGIO_TX.unknown <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int); + end if; + end process PROC_REG_OUTPUT_SIGNALS; --------------------------------------------------------------------- --Debugging -- 2.43.0