From 0a5eed2dfb39d3186d0e486da6d9660aa1657ca3 Mon Sep 17 00:00:00 2001 From: local account Date: Mon, 24 Apr 2017 15:32:28 +0200 Subject: [PATCH] threshold-fpga design with spi connection and preparation for FLASH connection --- thresholds/thresholds.prj | 10 +- thresholds/thresholds.vhd | 367 +++++++++++++++++++++++++++----------- 2 files changed, 271 insertions(+), 106 deletions(-) diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj index 0bb55f3..b2787ad 100644 --- a/thresholds/thresholds.prj +++ b/thresholds/thresholds.prj @@ -11,11 +11,15 @@ add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd" add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" add_file -vhdl -lib work "../code/pwm_machxo.vhd" +add_file -vhdl -lib work "../../logicbox/UFM_control/UFM_control.vhd" +add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" +add_file -vhdl -lib work "cores/flash.vhd" + #add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" -#add_file -vhdl -lib work "../../logicbox/cores/efb.vhd" -#add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v" -#add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" +#add_file -vhdl -lib work "cores/efb.vhd" +#add_file -verilog -lib work "cores/efb_define_def.v" +add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" add_file -vhdl -lib work "thresholds.vhd" diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index b0de791..2a00fa1 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -20,6 +20,8 @@ entity thresholds is end entity; architecture arch of thresholds is + type ram_t is array (15 downto 0) of std_logic_vector(15 downto 0); + signal clk_osc, clk_i : std_logic; signal spi_rx_data : std_logic_vector(15 downto 0); @@ -28,7 +30,7 @@ architecture arch of thresholds is signal bus_read : std_logic := '0'; signal bus_write : std_logic := '0'; signal bus_ready : std_logic; - signal spi_busy : std_logic; + --signal spi_busy : std_logic; signal sed_error : std_logic; signal sed_debug : std_logic_vector(31 downto 0); @@ -37,60 +39,46 @@ architecture arch of thresholds is signal pwm_data_i : std_logic_vector(15 downto 0); signal pwm_write_i : std_logic; signal pwm_addr_i : std_logic_vector(4 downto 0); + signal pwm_data_ii : std_logic_vector(15 downto 0); + signal pwm_write_ii : std_logic; + signal pwm_addr_ii : std_logic_vector(4 downto 0); - signal ram_write_i : std_logic; - signal ram_data_i: std_logic_vector(7 downto 0); - signal ram_data_o: std_logic_vector(7 downto 0); - signal ram_addr_i: std_logic_vector(3 downto 0); - - signal flashram_addr_i : std_logic_vector(3 downto 0); - signal flashram_cen_i : std_logic; - signal flashram_reset : std_logic; - signal flashram_write_i: std_logic; +-- signal flashram_reset : std_logic; + --signal flashram_write_i: std_logic; signal flashram_data_i : std_logic_vector(7 downto 0); signal flashram_data_o : std_logic_vector(7 downto 0); + signal ram_data : ram_t := (others =>("0000000000000000"));--: std_logic_vector(15 downto 0); + --signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0); - signal flash_command : std_logic_vector(2 downto 0); - signal flash_page : std_logic_vector(12 downto 0); + signal flash_command : std_logic; + --signal flash_page : std_logic_vector(12 downto 0); signal flash_go : std_logic; signal flash_busy : std_logic; signal flash_err : std_logic; signal compensate_i : signed(15 downto 0); signal pwm_i : std_logic_vector(15 downto 0); - signal dummy_register : std_logic_vector(15 downto 0); + signal ufm_bus_ready_in : std_logic; + signal ufm_bus_ready_out : std_logic; + signal ufm_databyte_counter : unsigned(14 downto 0); + + signal ram_data_f_spi_addr : std_logic_vector( 7 downto 0); + signal ram_data_f_spi_data : std_logic_vector(15 downto 0); + signal ram_data_f_spi_write : std_logic; + component OSCH generic (NOM_FREQ: string := "33.25"); port ( - STDBY :IN std_logic; - OSC :OUT std_logic; - SEDSTDBY :OUT std_logic + STDBY : IN std_logic; + OSC : OUT std_logic; + SEDSTDBY : OUT std_logic ); end component; - - component UFM_WB - port( - clk_i : in std_logic; - rst_n : in std_logic; - cmd : in std_logic_vector(2 downto 0); - ufm_page : in std_logic_vector(12 downto 0); - GO : in std_logic; - BUSY : out std_logic; - ERR : out std_logic; - mem_clk : out std_logic; - mem_we : out std_logic; - mem_ce : out std_logic; - mem_addr : out std_logic_vector(3 downto 0); - mem_wr_data : out std_logic_vector(7 downto 0); - mem_rd_data : in std_logic_vector(7 downto 0) - ); - end component; + begin - -LED <= dummy_register(7 downto 0); --------------------------------------------------------------------------- -- Clock --------------------------------------------------------------------------- @@ -105,15 +93,15 @@ clk_source: OSCH clk_i <= clk_osc; --------------------------------------------------------------------------- --- UART +-- SPI --------------------------------------------------------------------------- THE_SPI : entity work.spi_slave port map( - CLK => clk_i, - SPI_CLK => SCLK_IN, - SPI_CS => CS_IN , - SPI_IN => MOSI_IN, - SPI_OUT => MISO_OUT, + CLK => clk_i, + SPI_CLK => SCLK_IN, + SPI_CS => CS_IN , + SPI_IN => MOSI_IN, + SPI_OUT => MISO_OUT, DATA_OUT => spi_rx_data, DATA_IN => spi_tx_data, @@ -123,32 +111,52 @@ THE_SPI : entity work.spi_slave READY_IN => bus_ready, DEBUG => open - ); + ); PROC_REGS : process begin wait until rising_edge(clk_i); - bus_ready <= '0'; - pwm_write_i<= '0'; - if bus_read = '1' then + bus_ready <= '0'; + pwm_write_i <= '0'; + flash_go <= '0'; + ram_data_f_spi_write <= '0'; + + if pwm_write_ii = '1' then + pwm_data_i <= pwm_data_ii; + pwm_addr_i <= pwm_addr_ii; + pwm_write_i <= pwm_write_ii; + + elsif bus_read = '1' then bus_ready <= '1'; - case spi_addr is - when x"10" => uart_tx_data <= std_logic_vector(compensate_i); - when x"ee" => spi_tx_data <= sed_debug(15 downto 0); - when x"ef" => spi_tx_data <= sed_debug(31 downto 16); - when x"e4" => spi_tx_data <= dummy_register; - end case; + if spi_addr >= x"10" and spi_addr < x"20" then + spi_tx_data <= ram_data(to_integer(unsigned(spi_addr))); + else + case spi_addr is + when x"30" => spi_tx_data <= std_logic_vector(compensate_i); + when x"ee" => spi_tx_data <= sed_debug(15 downto 0); + when x"ef" => spi_tx_data <= sed_debug(31 downto 16); + when others => null; + end case; + end if; + elsif bus_write = '1' then - if spi_addr < x"10" then - pwm_data_i <= spi_rx_data(15 downto 0); - pwm_addr_i <= spi_addr(4 downto 0); - pwm_write_i<= '1'; + if spi_addr < x"10" then -- 0 to 15 0x00 to 0x10 -- write directly to pwm + if flash_busy = '0' or flash_command = '0' then -- avoid conflict with writing from flash + pwm_data_i <= spi_rx_data(15 downto 0); + pwm_addr_i <= spi_addr(4 downto 0); + pwm_write_i <= '1'; + end if; + elsif spi_addr >= x"10" and spi_addr < x"20" then -- write to ram + --ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; + ram_data_f_spi_write <= '1'; + ram_data_f_spi_addr <= spi_addr; + ram_data_f_spi_data <= spi_rx_data; else - case spi_addr is - when x"10" => compensate_i <= signed(uart_rx_data(15 downto 0); - when x"ee" => controlsed_i <= uart_rx_data(3 downto 0); - when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); - when x"e4" => dummy_register <= spi_rx_data ; + case spi_addr is + -- when x"20" => flash_command <= spi_rx_data(0); --read/write to flash; + -- flash_go <= '1'; + when x"30" => compensate_i <= spi_rx_data(15 downto 0);--signed(uart_rx_data(15 downto 0); + when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); end case; end if; end if; @@ -173,61 +181,214 @@ THE_PWM_GEN : entity work.pwm_generator ) port map( CLK => clk_i, - DATA_IN => pwm_data_i, + DATA_IN => pwm_data_i, -- 16 Bits DATA_OUT => open, - COMP_IN => compensate_i, - WRITE_IN => pwm_write_i, - ADDR_IN => pwm_addr_i, - PWM => pwm_i + COMP_IN => compensate_i, -- 16 Bits + WRITE_IN => pwm_write_i, -- 16 Bits + ADDR_IN => pwm_addr_i, -- 5 Bits + PWM => pwm_i -- 16 Bits ); --TODO connect to output according to ID OUTPUT <= pwm_i; + + --------------------------------------------------------------------------- -- Flash Controller --------------------------------------------------------------------------- --- THE_FLASH_RAM : entity work.flashram --- port map( --- DataInA => ram_data_i, --- AddressA => ram_addr_i, --- ClockA => clk_i, --- ClockEnA => '1', --- WrA => ram_write_i, --- ResetA => '0', --- QA => ram_data_o, --- --- DataInB => flashram_data_i, --- AddressB => flashram_addr_i, --- ClockB => clk_i, --- ClockEnB => flashram_cen_i, --- WrB => flashram_write_i, --- ResetB => flashram_reset, --- QB => flashram_data_o --- ); --- --- --- --- THE_FLASH : UFM_WB --- port map( --- clk_i => clk_i, --- rst_n => '1', --- cmd => flash_command, --- ufm_page => flash_page, --- GO => flash_go, --- BUSY => flash_busy, --- ERR => flash_err, --- mem_clk => open, --- mem_we => flashram_write_i, --- mem_ce => flashram_cen_i, --- mem_addr => flashram_addr_i, --- mem_wr_data => flashram_data_i, --- mem_rd_data => flashram_data_o --- ); +--THE_UFM : entity work.UFM_control +-- generic map( +-- NO_DATAPAGES => 2, +-- UFM_STARTPAGE => "00"&x"00" +-- ) +-- port map( +-- CLK => clk_i, +-- CMD => flash_command, +-- GO => flash_go, +-- BUSY => flash_busy, +-- RESET => '0', +-- DATA_IN => flashram_data_i, +-- DATA_OUT => flashram_data_o, +-- DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte +-- BUS_READY_IN => ufm_bus_ready_in, +-- BUS_READY_OUT => ufm_bus_ready_out, +-- FLASH_ERROR => flash_err +-- ); + + +--PROC_REGS_FLASH: process begin +--wait until rising_edge( clk_i ); +-- ufm_bus_ready_in <= '0'; +-- pwm_write_ii <= '0'; +-- if flash_command = '0' and ufm_bus_ready_out = '1' then +-- -- copy data from UFM to registers +-- ufm_bus_ready_in <= '1'; +-- case to_integer ( ufm_databyte_counter ) is +-- when 0 => ram_data( 0)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 1 => ram_data( 0)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00000"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 2 => ram_data( 1)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 3 => ram_data( 1)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00001"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 4 => ram_data( 2)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 5 => ram_data( 2)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00010"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 6 => ram_data( 3)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 7 => ram_data( 3)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00011"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 8 => ram_data( 4)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 9 => ram_data( 4)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00100"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 10 => ram_data( 5)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 11 => ram_data( 5)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00101"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 12 => ram_data( 6)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 13 => ram_data( 6)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00110"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 14 => ram_data( 7)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 15 => ram_data( 7)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "00111"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 16 => ram_data( 8)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 17 => ram_data( 8)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01000"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 18 => ram_data( 9)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 19 => ram_data( 9)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01001"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 20 => ram_data(10)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 21 => ram_data(10)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01010"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 22 => ram_data(11)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 23 => ram_data(11)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01011"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 24 => ram_data(12)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 25 => ram_data(12)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01100"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 26 => ram_data(13)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 27 => ram_data(13)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01101"; +-- pwm_data_ii( 15 downto 8) <= flashram_data_o; +-- when 28 => ram_data(14)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 29 => ram_data(14)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01110"; +-- pwm_data_ii(15 downto 8) <= flashram_data_o; +-- when 30 => ram_data(15)( 7 downto 0) <= flashram_data_o; +-- pwm_write_ii <= '0'; +-- pwm_data_ii( 7 downto 0) <= flashram_data_o; +-- when 31 => ram_data(15)(15 downto 8) <= flashram_data_o; +-- pwm_write_ii <= '1'; +-- pwm_addr_ii <= "01111"; +-- pwm_data_ii(15 downto 8) <= flashram_data_o; +-- when others => null; +-- end case ; +-- +-- elsif flash_command = '1' and ufm_bus_ready_out = '1' then +-- -- save data from registers to UFM +-- ufm_bus_ready_in <= '1'; +-- case to_integer ( ufm_databyte_counter ) is +-- when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0); +-- when 1 => flashram_data_i <= ram_data( 0)(15 downto 8); +-- when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0); +-- when 3 => flashram_data_i <= ram_data( 1)(15 downto 8); +-- when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0); +-- when 5 => flashram_data_i <= ram_data( 2)(15 downto 8); +-- when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0); +-- when 7 => flashram_data_i <= ram_data( 3)(15 downto 8); +-- when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0); +-- when 9 => flashram_data_i <= ram_data( 4)(15 downto 8); +-- when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0); +-- when 11 => flashram_data_i <= ram_data( 5)(15 downto 8); +-- when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0); +-- when 13 => flashram_data_i <= ram_data( 6)(15 downto 8); +-- when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0); +-- when 15 => flashram_data_i <= ram_data( 7)(15 downto 8); +-- when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0); +-- when 17 => flashram_data_i <= ram_data( 8)(15 downto 8); +-- when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0); +-- when 19 => flashram_data_i <= ram_data( 9)(15 downto 8); +-- when 20 => flashram_data_i <= ram_data(10)( 7 downto 0); +-- when 21 => flashram_data_i <= ram_data(10)(15 downto 8); +-- when 22 => flashram_data_i <= ram_data(11)( 7 downto 0); +-- when 23 => flashram_data_i <= ram_data(11)(15 downto 8); +-- when 24 => flashram_data_i <= ram_data(12)( 7 downto 0); +-- when 25 => flashram_data_i <= ram_data(12)(15 downto 8); +-- when 26 => flashram_data_i <= ram_data(13)( 7 downto 0); +-- when 27 => flashram_data_i <= ram_data(13)(15 downto 8); +-- when 28 => flashram_data_i <= ram_data(14)( 7 downto 0); +-- when 29 => flashram_data_i <= ram_data(14)(15 downto 8); +-- when 30 => flashram_data_i <= ram_data(15)( 7 downto 0); +-- when 31 => flashram_data_i <= ram_data(15)(15 downto 8); +-- when others => null ; +-- end case ; +-- +-- elsif ram_data_f_spi_write = '1' then +-- ram_data(to_integer(unsigned(ram_data_f_spi_addr))) <= ram_data_f_spi_data; +-- end if ; +-- end process ; + end architecture; + -- 2.43.0