From 0a66d499678c0891a92531a0e8ff09c3926e990a Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Thu, 8 Mar 2018 11:45:51 +0100 Subject: [PATCH] digital part working, IF --- amps2/padiwa_amps2.prj | 6 +-- amps2/padiwa_amps2.vhd | 84 ++++++++++++++++----------------- amps2/par.p2t | 22 ++------- pinout/padiwa_amps2.lpf | 9 ++-- source/Amps2_TempSensor_UID.vhd | 1 + source/i2c_master.vhd | 3 +- 6 files changed, 57 insertions(+), 68 deletions(-) diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj index 1ac8a31..00d0b62 100644 --- a/amps2/padiwa_amps2.prj +++ b/amps2/padiwa_amps2.prj @@ -7,14 +7,14 @@ add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.9_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "workdir/version.vhd" -#add_file -vhdl -lib work "../source/spi_slave.vhd" -add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave_async.vhd" +#add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd" add_file -vhdl -lib work "../source/Stretcher.vhd" add_file -vhdl -lib work "../source/Stretcher_A.vhd" add_file -vhdl -lib work "../source/Stretcher_B.vhd" add_file -vhdl -lib work "../source/pwm.vhd" -add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd" +add_file -vhdl -lib work "../cores/pll_in133_out33_133_66.vhd" add_file -vhdl -lib work "padiwa_amps2.vhd" add_file -vhdl -lib work "../source/timer.vhd" diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd index 9d40c33..4fabdd7 100644 --- a/amps2/padiwa_amps2.vhd +++ b/amps2/padiwa_amps2.vhd @@ -46,16 +46,12 @@ architecture arch of padiwa_amps2 is attribute NOM_FREQ : string; attribute NOM_FREQ of clk_source : label is "133.00"; - signal clk_i, clk_osc, clk_33,clk_266 : std_logic; + signal clk_i, clk_osc, clk_33,clk_66 : std_logic; type led_timer_t is array(1 to 8) of unsigned(24 downto 0); signal led_timer : led_timer_t; signal led_state : std_logic_vector(8 downto 1); --- signal ram_write_i : std_logic; --- signal ram_data_i: std_logic_vector(7 downto 0); --- signal ram_data_o: std_logic_vector(7 downto 0); --- signal ram_addr_i: std_logic_vector(3 downto 0); signal temperature_i : std_logic_vector(11 downto 0); signal ID_OUT : std_logic_vector(31 downto 0); @@ -63,17 +59,7 @@ architecture arch of padiwa_amps2 is signal INP_i : std_logic_vector(15 downto 0); signal fast_input : std_logic_vector(8 downto 1); signal slow_input : std_logic_vector(8 downto 1); --- signal spi_reg00_i : std_logic_vector(15 downto 0); --- signal spi_reg10_i : std_logic_vector(15 downto 0); --- signal spi_reg20_i : std_logic_vector(15 downto 0); --- signal spi_reg40_i : std_logic_vector(15 downto 0); --- signal spi_data_i : std_logic_vector(15 downto 0); --- signal spi_operation_i : std_logic_vector(3 downto 0); --- signal spi_channel_i : std_logic_vector(7 downto 0); --- signal spi_write_i : std_logic_vector(15 downto 0); --- signal buf_SPI_OUT : std_logic; --- signal spi_debug_i : std_logic_vector(15 downto 0); --- signal last_spi_channel: std_logic_vector(7 downto 0); + signal spi_rx_data : std_logic_vector(15 downto 0); signal spi_tx_data : std_logic_vector(15 downto 0); signal spi_addr : std_logic_vector(7 downto 0); @@ -91,8 +77,6 @@ architecture arch of padiwa_amps2 is signal spi_ready_in : std_logic; signal spi_busy_out : std_logic; - - signal inp_select : integer range 0 to 31 := 0; signal inp_invert : std_logic_vector(15 downto 0) := x"aaaa"; --invert slow inputs only signal input_enable : std_logic_vector(15 downto 0); @@ -133,7 +117,6 @@ architecture arch of padiwa_amps2 is signal delayed_inputs : std_logic_vector(511 downto 0); signal selected_delay : std_logic_vector(8 downto 1); signal delayselect : integer range 0 to 63; - component OSCH generic (NOM_FREQ: string := "133.00"); @@ -158,12 +141,12 @@ clk_source: OSCH SEDSTDBY => open ); -THE_PLL : entity work.pll_in133_out33_133_266 +THE_PLL : entity work.pll_in133_out33_133_66 port map ( CLKI => clk_osc, CLKOP => clk_i, --133 CLKOS => clk_33, --33 - CLKOS2=> clk_266 --266 + CLKOS2=> clk_66 --66 ); @@ -177,9 +160,10 @@ THE_PLL : entity work.pll_in133_out33_133_266 PWM <= pwm_i(16 downto 1); - inp_status <= INP_i when rising_edge(clk_i); - last_inp <= inp_status(15 downto 0) when rising_edge(clk_i); - + --inp_status <= INP_i when rising_edge(clk_i); + inp_status <= INP_i when rising_edge(clk_66); + --last_inp <= inp_status(15 downto 0) when rising_edge(clk_i); + last_inp <= inp_status(15 downto 0) when rising_edge(clk_66); --------------------------------------------------------------------------- -- SPI Interface @@ -187,7 +171,9 @@ THE_PLL : entity work.pll_in133_out33_133_266 THE_SPI : entity work.spi_slave port map( - CLK => clk_i, + CLK_ext => clk_i, + CLK_int => clk_66, +-- CLK => clk_66, SPI_CLK => SPI_CLK, SPI_CS => SPI_CS, SPI_IN => SPI_IN, @@ -210,7 +196,7 @@ THE_SPI : entity work.spi_slave THE_FLASH_CONTROLLER : entity generic_flash_ctrl port map( - CLK_l => clk_i, + CLK_l => clk_66, CLK_f => clk_33, RESET => '0', @@ -220,7 +206,7 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl SPI_WRITE_IN => spi_write_out, SPI_READ_IN => spi_read_out, SPI_READY_OUT => spi_ready_in, - SPI_BUSY_IN => spi_busy_out, + SPI_BUSY_IN => '0', LOC_DATA_OUT => spi_rx_data, LOC_DATA_IN => spi_tx_data, @@ -231,6 +217,13 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl LOC_BUSY_OUT => bus_busy ); +--spi_rx_data <= spi_data_out; +--spi_data_in <= spi_tx_data; +--spi_addr <= spi_addr_out; +--bus_write <= spi_write_out; +--bus_read <= spi_read_out; +--spi_ready_in <= bus_ready; +--bus_busy <= spi_busy_out; --------------------------------------------------------------------------- -- Temperature and UID reader @@ -238,24 +231,27 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl TEMP_SENSOR_AND_UID: entity Amps2_TempSensor_UID port map( - clk => clk_i, +-- clk => clk_i, + clk => clk_66, temperature => temperature_i, ID_OUT => ID_OUT, sda => I2C_SDA, scl => I2C_SCL ); +--temperature_i <= "000000000000"; +--ID_OUT <= x"00000000"; --------------------------------------------------------------------------- -- Temperature Compensation --------------------------------------------------------------------------- -temperature_i_s <= temperature_i when rising_edge(clk_33); -comp_setting_s <= comp_setting when rising_edge(clk_33); -temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_33); +temperature_i_s <= temperature_i when rising_edge(clk_66); +comp_setting_s <= comp_setting when rising_edge(clk_66); +temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_66); gen_comp: if TEMP_CORRECTION = 1 generate - compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_33); + compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_66); end generate; gen_no_comp: if TEMP_CORRECTION = 0 generate @@ -267,31 +263,28 @@ end generate; --------------------------------------------------------------------------- THE_IO_REG : process begin - wait until rising_edge(clk_i); +-- wait until rising_edge(clk_i); + wait until rising_edge(clk_66); bus_ready <= '0'; pwm_write_i <= '0'; spi_tx_data <= x"0000"; if delayed_bus_ready = "01" then - --bus_ready <= '1'; - spi_tx_data <= pwm_data_o; delayed_bus_ready <= "10"; elsif delayed_bus_ready = "10" then bus_ready <= '1'; spi_tx_data <= pwm_data_o; - delayed_bus_ready <= "00"; + delayed_bus_ready <= "11"; else delayed_bus_ready <= "00"; end if; if bus_read = '1' then - bus_ready <= '1'; - if (spi_addr >= x"00") and (spi_addr < x"10") and delayed_bus_ready = "00"then - bus_ready <= '0'; + if spi_addr(7 downto 4) = x"0" and delayed_bus_ready = "00" then delayed_bus_ready <= "01"; - spi_tx_data <= pwm_data_o; pwm_addr_i <= spi_addr(3 downto 0); - else + elsif delayed_bus_ready = "00" then + bus_ready <= '1'; case spi_addr is when x"10" => spi_tx_data <= ID_OUT(7 downto 0) & "00000000" ; when x"11" => spi_tx_data <= "00000000" & ID_OUT(31 downto 24); @@ -314,11 +307,12 @@ THE_IO_REG : process begin when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); when x"32" => spi_tx_data <= x"0000"; + when x"ff" => spi_tx_data <= x"0200"; --version when others => null; end case; end if; - elsif bus_write = '1' then + elsif bus_write = '1' then if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM pwm_data_i <= spi_rx_data; pwm_addr_i <= spi_addr(3 downto 0); @@ -350,6 +344,7 @@ end process; THE_PWM_GEN : entity work.pwm_generator port map( CLK => clk_i, +-- CLK => clk_66, DATA_IN => pwm_data_i, DATA_OUT => pwm_data_o, COMP_IN => compensate_i, @@ -364,7 +359,8 @@ THE_PWM_GEN : entity work.pwm_generator --------------------------------------------------------------------------- PROC_LED_STATE : process begin - wait until rising_edge(clk_i); +-- wait until rising_edge(clk_i); + wait until rising_edge(clk_66); for i in 1 to 8 loop if (last_inp(i/2+1) xor inp_status(i/2+1)) = '1' and (led_timer(i)(23 downto 21) > 0) then led_state(i) <= not led_state(i); @@ -391,6 +387,8 @@ CON <= inp_gated or (inp_stretched and inp_stretch); inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg; inp_hold_reg <= inp_hold when rising_edge(clk_i); last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i); +-- inp_hold_reg <= inp_hold when rising_edge(clk_66); +-- last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_66); inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold; fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0); diff --git a/amps2/par.p2t b/amps2/par.p2t index 39a0684..e30e228 100644 --- a/amps2/par.p2t +++ b/amps2/par.p2t @@ -1,21 +1,9 @@ -w --i 15 -l 5 +-i 6 -n 1 --y --s 12 -t 1 --c 1 --e 2 -#-g guidefile.ncd -#-m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=0 \ No newline at end of file diff --git a/pinout/padiwa_amps2.lpf b/pinout/padiwa_amps2.lpf index 92b1ef4..f60a7ef 100644 --- a/pinout/padiwa_amps2.lpf +++ b/pinout/padiwa_amps2.lpf @@ -148,12 +148,13 @@ LOCATE COMP "TMP_ALERT" SITE "A8"; IOBUF PORT "TMP_ALERT" IO_TYPE=LVTTL33 PULLMODE=UP; -UGROUP "StretchA" BBOX 1 32 +UGROUP "StretchA" BBOX 4 39 BLKNAME THE_STRETCHER/Stretcher_A_1 ; -LOCATE UGROUP "StretchA" SITE "R25C6"; +LOCATE UGROUP "StretchA" SITE "R22C2"; -UGROUP "StretchB" BBOX 1 32 +UGROUP "StretchB" BBOX 4 39 BLKNAME THE_STRETCHER/Stretcher_B_1 ; -LOCATE UGROUP "StretchB" SITE "R2C6"; +LOCATE UGROUP "StretchB" SITE "R2C2"; +#LOCATE UGROUP "StretchB" SITE "R18C2"; \ No newline at end of file diff --git a/source/Amps2_TempSensor_UID.vhd b/source/Amps2_TempSensor_UID.vhd index f6678eb..dcc26b9 100644 --- a/source/Amps2_TempSensor_UID.vhd +++ b/source/Amps2_TempSensor_UID.vhd @@ -39,6 +39,7 @@ begin scl => scl ); + process begin wait until rising_edge(clk); count <= count + 1; diff --git a/source/i2c_master.vhd b/source/i2c_master.vhd index f63a6c6..173c384 100644 --- a/source/i2c_master.vhd +++ b/source/i2c_master.vhd @@ -5,7 +5,8 @@ USE ieee.std_logic_unsigned.all; ENTITY i2c_master IS GENERIC( - input_clk : INTEGER := 133_000_000; --input clock speed from user logic in Hz + --input_clk : INTEGER := 133_000_000; --input clock speed from user logic in Hz + input_clk : INTEGER := 66_500_000; bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz PORT( clk : IN STD_LOGIC; --system clock -- 2.43.0