From 0ab3c14bef62e880c2f840040a3c4f54fc9d7c0b Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Mon, 28 Jul 2014 11:50:39 +0200 Subject: [PATCH] Monitoring and Debug features added to CBM-Readout Chain --- cbmnet/code/cbmnet_interface_pkg.vhd | 7 +- cbmnet/code/cbmnet_phy_ecp3.vhd | 56 +- cbmnet/code/cbmnet_phy_rx_gear.vhd | 16 +- cbmnet/code/cbmnet_readout.vhd | 205 +++- cbmnet/code/cbmnet_readout_trbnet_decoder.vhd | 4 +- cbmnet/code/cbmnet_readout_tx_fsm.vhd | 20 +- .../lattice_ecp3_fifo_16x16_dualport.vhd | 909 ++++++++++++++++++ 7 files changed, 1152 insertions(+), 65 deletions(-) create mode 100644 cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index 10c15ab..7f9bced 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -320,7 +320,10 @@ package cbmnet_interface_pkg is CBMNET_STOP_IN : in std_logic; CBMNET_START_OUT : out std_logic; CBMNET_END_OUT : out std_logic; - CBMNET_DATA_OUT : out std_logic_vector(15 downto 0) + CBMNET_DATA_OUT : out std_logic_vector(15 downto 0); + + -- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end component; @@ -418,10 +421,10 @@ package cbmnet_interface_pkg is -- TrbNet CLK_IN : in std_logic; RESET_IN : in std_logic; + ENABLED_IN : in std_logic; -- connect to hub HUB_CTS_START_READOUT_IN : in std_logic; - HUB_CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM HUB_FEE_DATA_IN : in std_logic_vector (15 downto 0); HUB_FEE_DATAREADY_IN : in std_logic; GBE_FEE_READ_IN : in std_logic; diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index a5b626e..6965a10 100755 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -35,7 +35,6 @@ entity cbmnet_phy_ecp3 is CLK_RX_FULL_OUT : out std_logic := '0'; -- recovered 250 MHz CLK_RX_RESET_OUT : out std_logic := '1'; - LINK_ACTIVE_OUT : out std_logic; -- link is active and can send and receive data SERDES_ready : out std_logic; --SFP Connection @@ -612,7 +611,9 @@ begin end if; end process; - + + LED_RX_OUT <= '0' when rx_data_i /= "10" & x"fcc3" and rx_data_i /= "00" & x"0000" else '1'; + LED_TX_OUT <= '0' when tx_data_i /= "10" & x"fcc3" and tx_data_i /= "00" & x"0000" else '1'; GEN_DEBUG: if INCL_DEBUG_AIDS = c_YES generate proc_stat: process is @@ -710,16 +711,7 @@ begin DEBUG_OUT(403 downto 332) <= tx_data_sp_i3(17 downto 0) & tx_data_sp_i2(17 downto 0) & tx_data_sp_i1(17 downto 0) & tx_data_sp_i0(17 downto 0); DEBUG_OUT(421 downto 404) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0); - - - -- & tx_data_sp_i7(17 downto 0) & tx_data_sp_i6(17 downto 0) & tx_data_sp_i5(17 downto 0) & tx_data_sp_i4(17 downto 0) & tx_data_sp_i8(17 downto 0) & tx_data_sp_i9(17 downto 0); - - --DEBUG_OUT(341 downto 334) <= stat_sync_dlm_inv_counter_i(7 downto 0) when rising_edge(rclk_125_i); - --DEBUG_OUT(349 downto 342) <= stat_sync_dlm_counter_i(7 downto 0) when rising_edge(rclk_125_i); - - - --DEBUG_OUT(255 downto 170) <= (others => '0'); -- DEBUG_OUT_END @@ -755,30 +747,30 @@ begin end process; - process is - variable detect_first_v : std_logic := '0'; - begin - wait until rising_edge(rclk_250_i); - - if rx_data_from_serdes_i = "1" & K277 and detect_first_v = '1' then - detect_dlm_250_i <= not detect_dlm_250_i; - end if; - - detect_first_v := '0'; - if rx_data_from_serdes_i = "0" & EBTB_D_ENCODE(14, 6) then - detect_first_v := '1'; - end if; - end process; +-- process is +-- variable detect_first_v : std_logic := '0'; +-- begin +-- wait until rising_edge(rclk_250_i); +-- +-- if rx_data_from_serdes_i = "1" & K277 and detect_first_v = '1' then +-- detect_dlm_250_i <= not detect_dlm_250_i; +-- end if; +-- +-- detect_first_v := '0'; +-- if rx_data_from_serdes_i = "0" & EBTB_D_ENCODE(14, 6) then +-- detect_first_v := '1'; +-- end if; +-- end process; process is begin wait until rising_edge(rclk_125_i); - if detect_dlm_250_i /= detect_dlm_125_i then - dlm_counter_i <= dlm_counter_i + 1; - end if; - - detect_dlm_125_i <= detect_dlm_250_i; +-- if detect_dlm_250_i /= detect_dlm_125_i then +-- dlm_counter_i <= dlm_counter_i + 1; +-- end if; +-- +-- detect_dlm_125_i <= detect_dlm_250_i; STAT_OP(0)<= '0'; @@ -788,7 +780,7 @@ begin end process; - STAT_OP(2 downto 1) <= detect_dlm_125_i & detect_dlm_250_i; +-- STAT_OP(2 downto 1) <= detect_dlm_125_i; --PROC_SEE_FAST_DLM: process is @@ -850,7 +842,5 @@ begin --see_dlm_lb_i(15)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 5, 3) else '0'; --see_dlm_lb_buf_i <= see_dlm_lb_i when rising_edge(rclk_250_i); - - end generate; end architecture; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_phy_rx_gear.vhd b/cbmnet/code/cbmnet_phy_rx_gear.vhd index 07508d0..f0f0166 100644 --- a/cbmnet/code/cbmnet_phy_rx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_rx_gear.vhd @@ -36,7 +36,7 @@ architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is attribute HGROUP of CBMNET_PHY_RX_GEAR_ARCH : architecture is "cbmnet_phy_rx_gear"; - type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_RESET, FSM_LOCKED); + type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_LOCK_WAIT1, FSM_LOCK_WAIT2, FSM_LOCK_WAIT3, FSM_RESET, FSM_LOCKED); signal fsm_i : FSM_STATES_T; signal fsm_state_i : std_logic_vector(3 downto 0); @@ -94,13 +94,25 @@ begin elsif indi_misalignment_i = '1' then -- we're off by one word. just wait a single frame delay_clock_i <= '1'; - -- fsm_i <= FSM_LOCKED; + fsm_i <= FSM_LOCK_WAIT1; -- ensure we only have a single delay clock cycle elsif timeout_i = '1' then fsm_i <= FSM_RESET; end if; + + when FSM_LOCK_WAIT1 => + fsm_state_i <= x"7"; + fsm_i <= FSM_LOCK_WAIT2; + + when FSM_LOCK_WAIT2 => + fsm_state_i <= x"7"; + fsm_i <= FSM_LOCK_WAIT3; + when FSM_LOCK_WAIT3 => + fsm_state_i <= x"7"; + fsm_i <= FSM_WAIT_FOR_LOCK; + when FSM_LOCKED => fsm_state_i <= x"2"; RESET_OUT <= '0'; diff --git a/cbmnet/code/cbmnet_readout.vhd b/cbmnet/code/cbmnet_readout.vhd index bf11e89..e84fbae 100644 --- a/cbmnet/code/cbmnet_readout.vhd +++ b/cbmnet/code/cbmnet_readout.vhd @@ -60,6 +60,7 @@ entity CBMNET_READOUT is end entity; architecture cbmnet_readout_arch of CBMNET_READOUT is +-- signals of readout chain (DECODER -> PACKER -> FIFO -> TX) signal fifo_rdata_i : std_logic_vector(17 downto 0); signal fifo_rdequeue_i : std_logic; signal fifo_rpacket_complete_i : std_logic; @@ -84,6 +85,43 @@ architecture cbmnet_readout_arch of CBMNET_READOUT is signal dec_actice_i : std_logic; signal dec_data_ready_i : std_logic; + signal pack_source_i : std_logic_vector(15 downto 0); + +-- cbm strobe buffers + signal cbmnet_data2send_start_i : std_logic; + signal cbmnet_data2send_end_i : std_logic; + signal cbmnet_data2send_data_i : std_logic_vector(15 downto 0); + signal cbmnet_link_active_in_buf_i : std_logic; + +-- stats and monitoring + signal cbm_stat_num_packets_i : unsigned(31 downto 0) := (others => '0'); + signal cbm_stat_num_send_completed_i : unsigned(31 downto 0) := (others => '0'); + signal cbm_stat_clks_dead_i : unsigned(31 downto 0) := (others => '0'); + signal cbm_stat_connections_i : unsigned(31 downto 0) := (others => '0'); + + signal stat_num_packets_i : unsigned(31 downto 0); + signal stat_num_send_completed_i : unsigned(31 downto 0); + + signal stat_num_packets_aborted_i : unsigned(31 downto 0) := (others => '0'); + signal stat_clks_dead_i : unsigned(31 downto 0); + signal stat_connections_i : unsigned(31 downto 0); + + signal stat_num_recv_completed_i : unsigned(31 downto 0); + signal stat_link_inactive_i : unsigned(31 downto 0); + +-- debug + signal debug_decorder_i : std_logic_vector(31 downto 0); + signal debug_packer_i : std_logic_vector(31 downto 0); + signal debug_tx_fsm_i : std_logic_vector(31 downto 0); + +-- slow control and configuration + signal regio_data_status_i : std_logic_vector(31 downto 0); + signal regio_data_ready_i : std_logic; + signal regio_unkown_address_i : std_logic; + + signal cfg_enabled_i : std_logic; + signal cfg_source_i : std_logic_vector(15 downto 0); + signal cfg_source_override_i : std_logic; begin GBE_CTS_NUMBER_OUT <= HUB_CTS_NUMBER_IN; GBE_CTS_CODE_OUT <= HUB_CTS_CODE_IN; @@ -104,10 +142,10 @@ begin -- TrbNet CLK_IN => CLK_IN, -- in std_logic; RESET_IN => dec_reset_i, -- in std_logic; - + ENABLED_IN => cfg_enabled_i, + -- connect to hub HUB_CTS_START_READOUT_IN => HUB_CTS_START_READOUT_IN, -- in std_logic; - HUB_CTS_READOUT_FINISHED_OUT => HUB_CTS_READOUT_FINISHED_OUT, -- out std_logic; --no more data, end transfer, send TRM HUB_FEE_DATA_IN => HUB_FEE_DATA_IN, -- in std_logic_vector (15 downto 0); HUB_FEE_DATAREADY_IN => HUB_FEE_DATAREADY_IN, -- in std_logic; GBE_FEE_READ_IN => GBE_FEE_READ_IN, -- in std_logic; @@ -123,7 +161,7 @@ begin DEC_ACTIVE_OUT => dec_actice_i, -- out std_logic; DEC_ERROR_OUT => dec_error_i, -- out std_logic; - DEBUG_OUT => open -- out std_logic_vector(31 downto 0); + DEBUG_OUT => debug_decorder_i -- out std_logic_vector(31 downto 0); ); dec_reset_i <= RESET_IN or dec_issue_reset_i; @@ -140,17 +178,16 @@ begin HUB_CTS_READOUT_TYPE_IN => HUB_CTS_READOUT_TYPE_IN, -- in std_logic_vector (3 downto 0); GBE_CTS_STATUS_BITS_IN => GBE_CTS_STATUS_BITS_IN, -- in std_logic_vector (31 downto 0); - -- connect to decoder - DEC_EVT_INFO_IN => dec_evt_info_i, -- in std_logic_vector(31 downto 0); - DEC_LENGTH_IN => dec_length_i, -- in std_logic_vector(15 downto 0); - DEC_SOURCE_IN => dec_source_i, -- in std_logic_vector(15 downto 0); - DEC_DATA_IN => dec_data_i, -- in std_logic_vector(15 downto 0); - DEC_DATA_READY_IN => dec_data_ready_i, -- in std_logic; - DEC_ACTIVE_IN => dec_actice_i, -- in std_logic; - DEC_ERROR_IN => dec_error_i, -- in std_logic; - - DEC_DATA_READ_OUT => dec_data_read_i, -- out std_logic; + DEC_EVT_INFO_IN => dec_evt_info_i, -- in std_logic_vector(31 downto 0); + DEC_LENGTH_IN => dec_length_i, -- in std_logic_vector(15 downto 0); + DEC_SOURCE_IN => pack_source_i, -- in std_logic_vector(15 downto 0); + DEC_DATA_IN => dec_data_i, -- in std_logic_vector(15 downto 0); + DEC_DATA_READY_IN => dec_data_ready_i, -- in std_logic; + DEC_ACTIVE_IN => dec_actice_i, -- in std_logic; + DEC_ERROR_IN => dec_error_i, -- in std_logic; + + DEC_DATA_READ_OUT => dec_data_read_i, -- out std_logic; DEC_RESET_OUT => dec_issue_reset_i, -- out std_logic; -- connect to fifo @@ -161,8 +198,10 @@ begin WPACKET_COMPLETE_OUT=> fifo_wpacket_complete_i, -- out std_logic; WFULL_IN => fifo_wfull_i, -- in std_logic; - DEBUG_OUT => open -- out std_logic_vector(31 downto 0) + DEBUG_OUT => debug_packer_i -- out std_logic_vector(31 downto 0) ); + pack_source_i <= cfg_source_i when cfg_source_override_i = '1' else dec_source_i; + THE_READOUT_FIFO: CBMNET_READOUT_FIFO generic map ( @@ -170,27 +209,27 @@ begin WATERMARK => 2 ) port map ( -- write port - WCLK_IN => CLK_IN, -- in std_logic; -- not faster than rclk_in + WCLK_IN => CLK_IN, -- in std_logic; -- not faster than rclk_in WRESET_IN => RESET_IN, -- in std_logic; - WADDR_STORE_IN => fifo_waddr_store_i, -- in std_logic; + WADDR_STORE_IN => fifo_waddr_store_i, -- in std_logic; WADDR_RESTORE_IN => fifo_waddr_restore_i, -- in std_logic; - WDATA_IN => fifo_wdata_i, -- in std_logic_vector(17 downto 0); + WDATA_IN => fifo_wdata_i, -- in std_logic_vector(17 downto 0); WENQUEUE_IN => fifo_wenqueue_i, -- in std_logic; WPACKET_COMPLETE_IN => fifo_wpacket_complete_i, -- in std_logic; - WALMOST_FULL_OUT => open, -- out std_logic; + WALMOST_FULL_OUT => open, -- out std_logic; WFULL_OUT => fifo_wfull_i, -- out std_logic; -- read port - RCLK_IN => CBMNET_CLK_IN, -- in std_logic; + RCLK_IN => CBMNET_CLK_IN, -- in std_logic; RRESET_IN => CBMNET_RESET_IN, -- in std_logic; -- has to active at least two clocks AFTER (or while) write port was (is being) initialised - RDATA_OUT => fifo_rdata_i, -- out std_logic_vector(17 downto 0); + RDATA_OUT => fifo_rdata_i, -- out std_logic_vector(17 downto 0); RDEQUEUE_IN => fifo_rdequeue_i, -- in std_logic; - RPACKET_COMPLETE_OUT => fifo_rpacket_complete_i, -- out std_logic; -- atleast one packet is completed in fifo + RPACKET_COMPLETE_OUT => fifo_rpacket_complete_i, -- out std_logic; -- atleast one packet is completed in fifo RPACKET_COMPLETE_ACK_IN => fifo_rpacket_complete_ack_i -- in std_logic -- mark one event as dealt with (effectively decrease number of completed packets by one) ); @@ -207,10 +246,128 @@ begin -- cbmnet CBMNET_STOP_IN => CBMNET_DATA2SEND_STOP_IN, -- in std_logic; - CBMNET_START_OUT => CBMNET_DATA2SEND_START_OUT, -- out std_logic; - CBMNET_END_OUT => CBMNET_DATA2SEND_END_OUT, -- out std_logic; - CBMNET_DATA_OUT => CBMNET_DATA2SEND_DATA_OUT -- out std_logic_vector(15 downto 0) + CBMNET_START_OUT => cbmnet_data2send_start_i, -- out std_logic; + CBMNET_END_OUT => cbmnet_data2send_end_i, -- out std_logic; + CBMNET_DATA_OUT => cbmnet_data2send_data_i, -- out std_logic_vector(15 downto 0) + + DEBUG_OUT => debug_tx_fsm_i ); + CBMNET_DATA2SEND_DATA_OUT <= cbmnet_data2send_data_i; + CBMNET_DATA2SEND_START_OUT <= cbmnet_data2send_start_i; + CBMNET_DATA2SEND_END_OUT <= cbmnet_data2send_end_i; + +---------------------------------------- +-- Slow control and monitoring +---------------------------------------- + -- gather stats in CBMNet clock domain + PROC_CBM_STATS: process is + variable last_link_active_v, last_end_v : std_logic; + begin + wait until rising_edge(CBMNET_CLK_IN); + + if CBMNET_LINK_ACTIVE_IN = '1' and last_link_active_v = '0' then + cbm_stat_connections_i <= cbm_stat_connections_i + 1; + end if; + + if cbmnet_data2send_end_i = '1' and last_end_v = '0' then + cbm_stat_num_packets_i <= cbm_stat_num_packets_i + 1; + end if; + + if CBMNET_DATA2SEND_STOP_IN = '1' then + cbm_stat_clks_dead_i <= cbm_stat_clks_dead_i + 1; + end if; + + if fifo_rpacket_complete_ack_i = '1' then + cbm_stat_num_send_completed_i <= cbm_stat_num_send_completed_i + 1; + end if; + + last_link_active_v := CBMNET_LINK_ACTIVE_IN; + last_end_v := cbmnet_data2send_end_i; + end process; + + -- and cross over to TrbNet clock domain + stat_connections_i <= cbm_stat_connections_i when rising_edge(CLK_IN); + stat_num_packets_i <= cbm_stat_num_packets_i when rising_edge(CLK_IN); + stat_clks_dead_i <= cbm_stat_clks_dead_i when rising_edge(CLK_IN); + stat_num_send_completed_i <= cbm_stat_num_send_completed_i when rising_edge(CLK_IN); + + PROC_STATS: process is + begin + wait until rising_edge(CLK_IN); + + if cbmnet_link_active_in_buf_i = '0' then + stat_link_inactive_i <= stat_link_inactive_i + 1; + end if; + cbmnet_link_active_in_buf_i <= CBMNET_LINK_ACTIVE_IN; + + if fifo_wpacket_complete_i = '1' then + stat_num_recv_completed_i <= stat_num_recv_completed_i + 1; + end if; + + if fifo_waddr_restore_i = '1' then + stat_num_packets_aborted_i <= stat_num_packets_aborted_i + 1; + end if; + end process; + + PROC_READOUT_MUX: process is + variable addr : integer; + begin + wait until rising_edge(CLK_IN); + + regio_data_ready_i <= REGIO_READ_ENABLE_IN; + regio_unkown_address_i <= '0'; + regio_data_status_i <= x"00000000"; + + addr := to_integer(UNSIGNED(REGIO_ADDR_IN(6 downto 0))); + + -- read + case addr is + when 16#0# => regio_data_status_i(0) <= cfg_enabled_i; + when 16#1# => regio_data_status_i(16 downto 0) <= cfg_source_override_i & cfg_source_i; + + when 16#2# => regio_data_status_i <= stat_connections_i; + when 16#3# => regio_data_status_i <= stat_clks_dead_i; + when 16#4# => regio_data_status_i <= stat_num_send_completed_i; + when 16#5# => regio_data_status_i <= stat_num_packets_i; + when 16#6# => regio_data_status_i <= stat_num_recv_completed_i; + when 16#7# => regio_data_status_i <= stat_link_inactive_i; + when 16#8# => regio_data_status_i <= stat_num_packets_aborted_i; + + -- debug only ports + when 16#9# => regio_data_status_i <= debug_decorder_i; + when 16#a# => regio_data_status_i <= debug_packer_i; + when 16#b# => regio_data_status_i <= debug_tx_fsm_i; + when 16#c# => regio_data_status_i(1 downto 0) <= fifo_wfull_i & fifo_rpacket_complete_i; + when 16#d# => regio_data_status_i <= HUB_CTS_INFORMATION_IN & HUB_CTS_CODE_IN & HUB_CTS_NUMBER_IN; + when 16#e# => regio_data_status_i <= dec_evt_info_i; + when 16#f# => regio_data_status_i <= dec_source_i & dec_length_i; + + when others => regio_unkown_address_i <= REGIO_READ_ENABLE_IN; + end case; + + -- write + if REGIO_WRITE_ENABLE_IN = '1' then + case addr is + when 16#0# => + cfg_enabled_i <= REGIO_DATA_IN(0); + + when 16#1# => + cfg_source_i <= REGIO_DATA_IN(15 downto 0); + cfg_source_override_i <= REGIO_DATA_IN(16); + + when others => + regio_unkown_address_i <= '1'; + end case; + end if; + end process; + + + REGIO_DATA_OUT <= regio_data_status_i; + REGIO_UNKNOWN_ADDR_OUT <= regio_unkown_address_i; + + REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN when rising_edge(CLK_IN); + REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN when rising_edge(CLK_IN); + end architecture; diff --git a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd index 2c99ef4..a819fbb 100644 --- a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd +++ b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd @@ -14,10 +14,10 @@ entity CBMNET_READOUT_TRBNET_DECODER is -- TrbNet CLK_IN : in std_logic; RESET_IN : in std_logic; + ENABLED_IN : in std_logic; -- connect to hub HUB_CTS_START_READOUT_IN : in std_logic; - HUB_CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM HUB_FEE_DATA_IN : in std_logic_vector (15 downto 0); HUB_FEE_DATAREADY_IN : in std_logic; GBE_FEE_READ_IN : in std_logic; @@ -95,7 +95,7 @@ begin case(fsm_i) is when WAIT_FOR_IDLE => DEBUG_OUT(3 downto 0) <= x"0"; - if HUB_CTS_START_READOUT_IN = '0' then + if HUB_CTS_START_READOUT_IN = '0' and ENABLED_IN = '1' then fsm_i <= IDLE; end if; diff --git a/cbmnet/code/cbmnet_readout_tx_fsm.vhd b/cbmnet/code/cbmnet_readout_tx_fsm.vhd index 6526c5a..34cf8e2 100644 --- a/cbmnet/code/cbmnet_readout_tx_fsm.vhd +++ b/cbmnet/code/cbmnet_readout_tx_fsm.vhd @@ -18,7 +18,10 @@ entity CBMNET_READOUT_TX_FSM is CBMNET_STOP_IN : in std_logic; CBMNET_START_OUT : out std_logic; CBMNET_END_OUT : out std_logic; - CBMNET_DATA_OUT : out std_logic_vector(15 downto 0) + CBMNET_DATA_OUT : out std_logic_vector(15 downto 0); + + -- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; @@ -28,7 +31,8 @@ architecture cbmnet_readout_tx_fsm_arch of CBMNET_READOUT_TX_FSM is type FSM_STATES_T is (WAIT_FOR_COMPL_PACKET, SETUP_TRANSACTION, SEND_HEADER, SEND_PAYLOAD, SEND_PACKET_GAP, FINISH_TRANSACTION, FINISH_WAIT1, FINISH_WAIT2); signal fsm_i : FSM_STATES_T; - + signal fsm_state_i : unsigned(3 downto 0); + signal trans_num_i : unsigned(5 downto 0); signal trans_bytes_length_i : unsigned(15 downto 0) := x"0000"; @@ -42,6 +46,7 @@ architecture cbmnet_readout_tx_fsm_arch of CBMNET_READOUT_TX_FSM is signal trans_complete_i : std_logic; + begin PROC_TX_CNTL: process is begin @@ -57,15 +62,18 @@ begin if RESET_IN = '1' then fsm_i <= WAIT_FOR_COMPL_PACKET; trans_num_i <= (others => '0'); + fsm_state_i <= x"0"; else case(fsm_i) is when WAIT_FOR_COMPL_PACKET => + fsm_state_i <= x"1"; if FIFO_PACKET_COMPLETE_IN = '1' then fsm_i <= SETUP_TRANSACTION; end if; when SETUP_TRANSACTION => + fsm_state_i <= x"2"; trans_bytes_send_i <= (others => '0'); pack_num_i <= (others => '0'); pack_start_i <= '1'; @@ -74,6 +82,7 @@ begin fsm_i <= SEND_HEADER; when SEND_HEADER => + fsm_state_i <= x"3"; if CBMNET_STOP_IN = '0' then CBMNET_DATA_OUT <= (others => '0'); CBMNET_DATA_OUT( 5 downto 0) <= STD_LOGIC_VECTOR(pack_num_i); @@ -89,6 +98,7 @@ begin end if; when SEND_PAYLOAD => + fsm_state_i <= x"4"; if pack_payload_words_i = 30 or trans_complete_i = '1' then CBMNET_END_OUT <= '1'; pack_num_i <= pack_num_i + 1; @@ -113,17 +123,21 @@ begin when SEND_PACKET_GAP => + fsm_state_i <= x"5"; fsm_i <= SEND_HEADER; when FINISH_TRANSACTION => + fsm_state_i <= x"6"; FIFO_PACKET_COMPLETE_ACK_OUT <= '1'; trans_num_i <= trans_num_i + 1; fsm_i <= FINISH_WAIT1; when FINISH_WAIT1 => + fsm_state_i <= x"6"; fsm_i <= FINISH_WAIT2; when FINISH_WAIT2 => + fsm_state_i <= x"6"; fsm_i <= WAIT_FOR_COMPL_PACKET; end case; @@ -132,5 +146,7 @@ begin pack_stop_i <= '1' when trans_bytes_length_i - trans_bytes_send_i < PAYLOAD_PER_PACKET_C else '0'; trans_complete_i <= '1' when trans_bytes_length_i = trans_bytes_send_i else '0'; + + DEBUG_OUT(3 downto 0) <= fsm_state_i; end architecture; diff --git a/cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd b/cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd new file mode 100644 index 0000000..314681e --- /dev/null +++ b/cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd @@ -0,0 +1,909 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 16 -width 16 -depth 16 -rdata_width 16 -no_enable -pe -1 -pf 7 -e + +-- Mon Sep 12 17:39:25 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity lattice_ecp3_fifo_16x16_dualport is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end lattice_ecp3_fifo_16x16_dualport; + +architecture Structure of lattice_ecp3_fifo_16x16_dualport is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal co2_2: std_logic; + signal af_setcount_4: std_logic; + signal co1_4: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rptr_3: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal rptr_0: std_logic; + signal dec0_wre3: std_logic; + signal wptr_3: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal wptr_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "lattice_ecp3_fifo_16x16_dualport.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "lattice_ecp3_fifo_16x16_dualport.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-11)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "lattice_ecp3_fifo_16x16_dualport.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(12-15)"; + attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "lattice_ecp3_fifo_16x16_dualport.lpc"; + attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_14: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_5: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_clr); + + FF_73: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_72: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_71: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_70: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_69: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_68: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_67: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_66: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_65: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_64: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_63: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_62: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_61: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_60: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_59: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_58: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_57: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_56: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_55: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_54: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_53: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_52: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_51: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_50: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_49: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_48: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_47: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_46: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_45: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_44: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_43: FD1P3DX + port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(0)); + + FF_42: FD1P3DX + port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(1)); + + FF_41: FD1P3DX + port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(2)); + + FF_40: FD1P3DX + port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(3)); + + FF_39: FD1P3DX + port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(4)); + + FF_38: FD1P3DX + port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(5)); + + FF_37: FD1P3DX + port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(6)); + + FF_36: FD1P3DX + port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(7)); + + FF_35: FD1P3DX + port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(8)); + + FF_34: FD1P3DX + port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(9)); + + FF_33: FD1P3DX + port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_32: FD1P3DX + port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_31: FD1P3DX + port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_30: FD1P3DX + port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_29: FD1P3DX + port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_28: FD1P3DX + port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_27: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_26: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_25: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_24: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_23: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_22: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_21: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_20: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_19: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_18: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_17: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_16: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_15: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_14: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_13: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_12: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_6: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_5: FD1P3DX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_0); + + FF_4: FD1P3BX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_1); + + FF_3: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_2: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_1: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>scuba_vlo, + CO=>co2_2, NC0=>iaf_setcount_4, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co1_5, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + fifo_pfu_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, + DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15); + + fifo_pfu_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, + DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11); + + fifo_pfu_0_2: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, + DO2=>rdataout6, DO3=>rdataout7); + + fifo_pfu_0_3: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, + DO2=>rdataout2, DO3=>rdataout3); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of lattice_ecp3_fifo_16x16_dualport is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on -- 2.43.0