From 0b1f1a7444b42f69bdb9e94b635c1df587378f4f Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Wed, 30 Sep 2020 08:59:24 +0200 Subject: [PATCH] hub_test: Change downlinks to 2.4 Gbps --- hub_test/constrs/hub_test.xdc | 2 +- hub_test/hub_test.xpr | 7 + hub_test/ip/clk_wiz_0/clk_wiz_0.xci | 67 +- hub_test/ip/clk_wiz_0/clk_wiz_0.xml | 69 +- hub_test/ip/clk_wiz_1/clk_wiz_1.xci | 707 +++++ hub_test/ip/clk_wiz_1/clk_wiz_1.xml | 4584 +++++++++++++++++++++++++++ hub_test/src/hub_test.vhd | 90 +- hub_test/sw/init.c | 2 +- 8 files changed, 5427 insertions(+), 101 deletions(-) create mode 100644 hub_test/ip/clk_wiz_1/clk_wiz_1.xci create mode 100644 hub_test/ip/clk_wiz_1/clk_wiz_1.xml diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc index 0ae6022..567207e 100644 --- a/hub_test/constrs/hub_test.xdc +++ b/hub_test/constrs/hub_test.xdc @@ -35,7 +35,7 @@ set_property PACKAGE_PIN B34 [get_ports UC_RESET_N] set_property IOSTANDARD LVCMOS18 [get_ports UC_RESET_N] set_property PACKAGE_PIN N6 [get_ports MGTREFCLK0P_232] -create_clock -period 10.000 -name MGTREFCLK0P_232 [get_ports MGTREFCLK0P_232] +create_clock -period 8.333 -name MGTREFCLK0P_232 [get_ports MGTREFCLK0P_232] set_property PACKAGE_PIN R6 [get_ports MGTREFCLK0P_231] create_clock -period 5.000 -name MGTREFCLK0P_231 [get_ports MGTREFCLK0P_231] diff --git a/hub_test/hub_test.xpr b/hub_test/hub_test.xpr index 1f8587f..3f78f10 100644 --- a/hub_test/hub_test.xpr +++ b/hub_test/hub_test.xpr @@ -130,6 +130,13 @@ + + + + + + + diff --git a/hub_test/ip/clk_wiz_0/clk_wiz_0.xci b/hub_test/ip/clk_wiz_0/clk_wiz_0.xci index 25b41b3..6ec1593 100644 --- a/hub_test/ip/clk_wiz_0/clk_wiz_0.xci +++ b/hub_test/ip/clk_wiz_0/clk_wiz_0.xci @@ -99,21 +99,21 @@ clkfb_out clkfb_out_p clkfb_stopped - 100.0 + 83.33 100.0 0000 0000 - 100.00000 + 120.00000 0000 0000 - 200.00000 + 240.00000 BUFG 50.0 false - 100.00000 + 120.00000 0.000 50.000 - 100.000 + 120.000 0.000 1 0000 @@ -122,10 +122,10 @@ BUFG 50.0 false - 200.00000 + 240.00000 0.000 50.000 - 200.000 + 240.000 0.000 1 1 @@ -209,11 +209,11 @@ 0000 1 0.5 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 + 1.2 + 1.2 + 1.2 + 1.2 + 1.2 dout drdy dwe @@ -232,7 +232,7 @@ 0000 0 Input Clock Freq (MHz) Input Jitter (UI) - __primary_________100.000____________0.010 + __primary_________120.000____________0.010 no_secondary_input_clock input_clk_stopped 0 @@ -251,16 +251,16 @@ false false OPTIMIZED - 10.000 + 8.000 0.000 FALSE - 10.000 + 8.333 10.000 - 10.000 + 8.000 0.500 0.000 FALSE - 5 + 4 0.500 0.000 FALSE @@ -297,8 +297,8 @@ 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1__100.00000______0.000______50.0______130.958_____98.575 - clk_out2__200.00000______0.000______50.0______114.829_____98.575 + clk_out1__120.00000______0.000______50.0______123.514_____99.820 + clk_out2__240.00000______0.000______50.0______108.425_____99.820 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output @@ -348,7 +348,7 @@ clk_in1 MMCM AUTO - 100.000 + 120.000 0.010 10.000 No_buffer @@ -414,25 +414,25 @@ clkfb_out clkfb_out_p clkfb_stopped - 100.0 + 83.33 0.010 100.0 0.010 Buffer - 130.958 + 123.514 false - 98.575 + 99.820 50.000 - 100.000 + 120.000 0.000 1 true Buffer - 114.829 + 108.425 false - 98.575 + 99.820 50.000 - 200.000 + 240.000 0.000 1 true @@ -530,16 +530,16 @@ No_Jitter locked OPTIMIZED - 10.000 + 8.000 0.000 false - 10.000 + 8.333 10.000 - 10.000 + 8.000 0.500 0.000 false - 5 + 4 0.500 0.000 false @@ -609,7 +609,7 @@ clk_in1 MMCM mmcm_adv - 100.000 + 120.000 0.010 10.000 No_buffer @@ -703,6 +703,7 @@ + @@ -716,7 +717,9 @@ + + diff --git a/hub_test/ip/clk_wiz_0/clk_wiz_0.xml b/hub_test/ip/clk_wiz_0/clk_wiz_0.xml index 7c84f5c..cafebee 100644 --- a/hub_test/ip/clk_wiz_0/clk_wiz_0.xml +++ b/hub_test/ip/clk_wiz_0/clk_wiz_0.xml @@ -1270,7 +1270,7 @@ outputProductCRC - 9:c19c43be + 9:fc75f429 @@ -2338,7 +2338,7 @@ C_PRIM_IN_FREQ - 100.000 + 120.000 C_PRIM_IN_TIMEPERIOD @@ -2446,7 +2446,7 @@ C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 + __primary_________120.000____________0.010 C_INCLK_SUM_ROW2 @@ -2463,11 +2463,11 @@ C_OUTCLK_SUM_ROW1 - clk_out1__100.00000______0.000______50.0______130.958_____98.575 + clk_out1__120.00000______0.000______50.0______123.514_____99.820 C_OUTCLK_SUM_ROW2 - clk_out2__200.00000______0.000______50.0______114.829_____98.575 + clk_out2__240.00000______0.000______50.0______108.425_____99.820 C_OUTCLK_SUM_ROW3 @@ -2491,11 +2491,11 @@ C_CLKOUT1_REQUESTED_OUT_FREQ - 100.000 + 120.000 C_CLKOUT2_REQUESTED_OUT_FREQ - 200.000 + 240.000 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2575,11 +2575,11 @@ C_CLKOUT1_OUT_FREQ - 100.00000 + 120.00000 C_CLKOUT2_OUT_FREQ - 200.00000 + 240.00000 C_CLKOUT3_OUT_FREQ @@ -2703,11 +2703,11 @@ C_MMCM_CLKFBOUT_MULT_F - 10.000 + 8.000 C_MMCM_CLKIN1_PERIOD - 10.000 + 8.333 C_MMCM_CLKIN2_PERIOD @@ -2743,11 +2743,11 @@ C_MMCM_CLKOUT0_DIVIDE_F - 10.000 + 8.000 C_MMCM_CLKOUT1_DIVIDE - 5 + 4 C_MMCM_CLKOUT2_DIVIDE @@ -3119,7 +3119,7 @@ C_CLKIN1_JITTER_PS - 100.0 + 83.33 C_CLKIN2_JITTER_PS @@ -3277,23 +3277,23 @@ C_DIVIDE3_AUTO - 1.0 + 1.2 C_DIVIDE4_AUTO - 1.0 + 1.2 C_DIVIDE5_AUTO - 1.0 + 1.2 C_DIVIDE6_AUTO - 1.0 + 1.2 C_DIVIDE7_AUTO - 1.0 + 1.2 C_PLLBUFGCEDIV @@ -3377,11 +3377,11 @@ C_CLKOUT0_ACTUAL_FREQ - 100.00000 + 120.00000 C_CLKOUT1_ACTUAL_FREQ - 200.00000 + 240.00000 C_CLKOUT2_ACTUAL_FREQ @@ -3689,7 +3689,7 @@ PRIM_IN_FREQ - 100.000 + 120.000 PRIM_IN_TIMEPERIOD @@ -3753,7 +3753,7 @@ CLKIN1_JITTER_PS - 100.0 + 83.33 CLKIN2_JITTER_PS @@ -3897,7 +3897,7 @@ CLKOUT1_REQUESTED_OUT_FREQ - 100.000 + 120.000 CLKOUT1_REQUESTED_PHASE @@ -3909,7 +3909,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 200.000 + 240.000 CLKOUT2_REQUESTED_PHASE @@ -4185,7 +4185,7 @@ MMCM_CLKFBOUT_MULT_F - 10.000 + 8.000 MMCM_CLKFBOUT_PHASE @@ -4197,7 +4197,7 @@ MMCM_CLKIN1_PERIOD - 10.000 + 8.333 MMCM_CLKIN2_PERIOD @@ -4229,7 +4229,7 @@ MMCM_CLKOUT0_DIVIDE_F - 10.000 + 8.000 MMCM_CLKOUT0_DUTY_CYCLE @@ -4245,7 +4245,7 @@ MMCM_CLKOUT1_DIVIDE - 5 + 4 MMCM_CLKOUT1_DUTY_CYCLE @@ -4544,22 +4544,22 @@ CLKOUT1_JITTER Clkout1 Jitter - 130.958 + 123.514 CLKOUT1_PHASE_ERROR Clkout1 Phase - 98.575 + 99.820 CLKOUT2_JITTER Clkout2 Jitter - 114.829 + 108.425 CLKOUT2_PHASE_ERROR Clkout2 Phase - 98.575 + 99.820 CLKOUT3_JITTER @@ -4660,6 +4660,7 @@ + @@ -4673,7 +4674,9 @@ + + diff --git a/hub_test/ip/clk_wiz_1/clk_wiz_1.xci b/hub_test/ip/clk_wiz_1/clk_wiz_1.xci new file mode 100644 index 0000000..94c93df --- /dev/null +++ b/hub_test/ip/clk_wiz_1/clk_wiz_1.xci @@ -0,0 +1,707 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_1 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + + + + 100000000 + 0 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 120.00000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 120.00000 + 0.000 + 50.000 + 120.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 1.2 + 1.2 + 1.2 + 1.2 + 1.2 + 1.2 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 50.250 + 0.000 + FALSE + 10.000 + 10.000 + 8.375 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 5 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1__120.00000______0.000______50.0______234.636____298.923 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1440.000 + 600.000 + clk_wiz_1 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + Buffer + 234.636 + false + 298.923 + 50.000 + 120.000 + 0.000 + 1 + true + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_1 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 50.250 + 0.000 + false + 10.000 + 10.000 + 8.375 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 5 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + false + false + true + false + false + false + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hub_test/ip/clk_wiz_1/clk_wiz_1.xml b/hub_test/ip/clk_wiz_1/clk_wiz_1.xml new file mode 100644 index 0000000..887d684 --- /dev/null +++ b/hub_test/ip/clk_wiz_1/clk_wiz_1.xml @@ -0,0 +1,4584 @@ + + + xilinx.com + customized_ip + clk_wiz_1 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_aclk + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi_lite + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + ref_clk + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_resetn + S_AXI_RESETN + + + + + + + RST + + + s_axi_aresetn + + + + + + ASSOCIATED_RESET + aresetn + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + intr + Intr + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + CLK_IN1_D + CLK_IN1_D + Differential Clock input + + + + + + + CLK_N + + + clk_in1_n + + + + + CLK_P + + + clk_in1_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLK_IN2_D + CLK_IN2_D + Differential Clock input + + + + + + + CLK_N + + + clk_in2_n + + + + + CLK_P + + + clk_in2_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN2_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + clock_CLK_IN1 + + + + + + + CLK_IN1 + + + clk_in1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + 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C_USER_CLK_FREQ2 + 100.0 + + + C_USER_CLK_FREQ3 + 100.0 + + + C_ENABLE_CLOCK_MONITOR + 0 + + + C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + clk_wiz_1 + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 0 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 100.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + No_buffer + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 1 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 1 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1__120.00000______0.000______50.0______234.636____298.923 + + + C_OUTCLK_SUM_ROW2 + no_CLK_OUT2_output + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 120.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 120.00000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 50.250 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + AUTO + + + C_MMCM_DIVCLK_DIVIDE + 5 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 8.375 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 1.2 + + + C_DIVIDE3_AUTO + 1.2 + + + C_DIVIDE4_AUTO + 1.2 + + + C_DIVIDE5_AUTO + 1.2 + + + C_DIVIDE6_AUTO + 1.2 + + + C_DIVIDE7_AUTO + 1.2 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 120.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 64.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 93.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 600.000 + + + C_VCO_MAX + 1440.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_d0ea4aeb + MMCM + PLL + Auto + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_39d99e50 + Buffer + Buffer_with_CE + BUFG + BUFGCE + BUFGCE_DIV + No_buffer + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_94e02745 + AUTO + EXTERNAL + INTERNAL + BUF_IN + ZHOLD + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_1 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + false + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 120.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + No_buffer + + + CLKOUT1_DRIVES + Buffer + + + CLKOUT2_DRIVES + Buffer + + + CLKOUT3_DRIVES + Buffer + + + CLKOUT4_DRIVES + Buffer + + + CLKOUT5_DRIVES + Buffer + + + CLKOUT6_DRIVES + Buffer + + + CLKOUT7_DRIVES + Buffer + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + true + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 5 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 50.250 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + AUTO + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 8.375 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 234.636 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 298.923 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.1 + + + + + + + + diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd index 5783343..3d006cf 100644 --- a/hub_test/src/hub_test.vhd +++ b/hub_test/src/hub_test.vhd @@ -16,7 +16,7 @@ entity hub_test is CLK_200_P : in std_logic; CLK_200_N : in std_logic; - SI5345_IN0_P : out std_logic; -- 100 MHz + SI5345_IN0_P : out std_logic; -- 120 MHz SI5345_IN0_N : out std_logic; MPOD_RX1_RESET_N : out std_logic; @@ -31,7 +31,7 @@ entity hub_test is PEX_I2C_SEL1 : out std_logic; UC_RESET_N : out std_logic; - MGTREFCLK0P_232 : in std_logic; -- 100 MHz, derived from SI5345_IN0_P + MGTREFCLK0P_232 : in std_logic; -- 120 MHz, derived from SI5345_IN0_P MGTREFCLK0N_232 : in std_logic; MGTREFCLK0P_231 : in std_logic; -- 200 MHz, free-running @@ -75,14 +75,27 @@ architecture behavioral of hub_test is ); end component; + component clk_wiz_1 + port ( + clk_out1 : out std_logic; + reset : in std_logic; + locked : out std_logic; + clk_in1 : in std_logic + ); + end component; + signal clk_200_ibuf : std_logic; signal baseclk_100 : std_logic; - signal baseclk_out : std_logic; signal mb_ext_resets_n : std_logic_vector(7 downto 0); signal mb_sysclk_reset : std_logic; - signal sysclk_100 : std_logic; - signal sysclk_200 : std_logic; + signal outclk_120 : std_logic; + signal outclk_locked : std_logic; + signal outclk_not_locked : std_logic; + signal outclk_out : std_logic; + + signal sysclk_120 : std_logic; + signal sysclk_240 : std_logic; signal sysclk_locked : std_logic; signal mgtrefclk_downlink : std_logic; @@ -177,7 +190,7 @@ architecture behavioral of hub_test is signal trb_data_tkeep : std_logic_vector((INTERFACE_NUM - 1) * 4 - 1 downto 0); signal trb_data_tlast : std_logic_vector(INTERFACE_NUM - 2 downto 0); - constant MS_PERIOD_COUNTS : integer := 20480; -- assuming clock with 5 ns period + constant MS_PERIOD_COUNTS : integer := 24576; -- assuming clock with 4.1666 ns period signal ms_count : integer range 0 to MS_PERIOD_COUNTS - 1 := 0; signal trg_out : std_logic := '0'; signal dlm : std_logic := '0'; @@ -203,7 +216,16 @@ begin I => clk_200_ibuf ); - ODDRE1_baseclk : ODDRE1 + THE_OUTCLK : clk_wiz_1 + port map ( + clk_out1 => outclk_120, + reset => '0', + locked => outclk_locked, + clk_in1 => baseclk_100 + ); + outclk_not_locked <= not outclk_locked; + + ODDRE1_outclk : ODDRE1 generic map ( IS_C_INVERTED => '0', IS_D1_INVERTED => '0', @@ -212,24 +234,24 @@ begin SRVAL => '0' ) port map ( - Q => baseclk_out, - C => baseclk_100, + Q => outclk_out, + C => outclk_120, D1 => '1', D2 => '0', - SR => '0' + SR => outclk_not_locked ); - OBUFDS_baseclk : OBUFDS + OBUFDS_outclk : OBUFDS port map ( O => SI5345_IN0_P, OB => SI5345_IN0_N, - I => baseclk_out + I => outclk_out ); THE_SYSCLK : clk_wiz_0 port map ( - clk_out1 => sysclk_100, - clk_out2 => sysclk_200, + clk_out1 => sysclk_120, + clk_out2 => sysclk_240, reset => mb_sysclk_reset, locked => sysclk_locked, clk_in1 => mgtrefclk_downlink_bufg @@ -309,11 +331,11 @@ begin send_reset_in <= med2int_i(INTERFACE_NUM - 1).stat_op(15); reset_from_net <= med2int_i(INTERFACE_NUM - 1).stat_op(13); - process (sysclk_100) is + process (sysclk_120) is begin - if rising_edge(sysclk_100) then + if rising_edge(sysclk_120) then send_reset_detect <= send_reset_in; - if initial_clear_timer(27 - CLOCK_FAST_SELECT * 11) = '0' then -- after 135us or 8.8ms plus 1 + if initial_clear_timer(27 - CLOCK_FAST_SELECT * 11) = '0' then -- TODO: Check reset length initial_clear_timer <= initial_clear_timer + 1; end if; initial_clear_n <= initial_clear_timer(27 - CLOCK_FAST_SELECT * 11); @@ -330,8 +352,8 @@ begin port map ( CLEAR_IN => reset_from_vio, CLEAR_N_IN => initial_clear_n, - CLK_IN => sysclk_100, - SYSCLK_IN => sysclk_100, + CLK_IN => sysclk_120, + SYSCLK_IN => sysclk_120, PLL_LOCKED_IN => sysclk_locked, RESET_IN => '0', TRB_RESET_IN => trb_reset, @@ -348,7 +370,7 @@ begin REFCLK_FREQ_HZ => 200000000 ) port map ( - SYSCLK => sysclk_100, + SYSCLK => sysclk_120, CLK_100 => baseclk_100, GTREFCLK => mgtrefclk_uplink, GTREFCLK_BUFG => mgtrefclk_uplink_bufg, @@ -391,16 +413,16 @@ begin REFCLK_FREQ_HZ => 100000000 ) port map ( - SYSCLK => sysclk_100, + SYSCLK => sysclk_120, CLK_100 => baseclk_100, GTREFCLK => mgtrefclk_downlink, GTREFCLK_BUFG => mgtrefclk_downlink_bufg, RXOUTCLK => open, TXOUTCLK => open, - RXUSRCLK => sysclk_100, - RXUSRCLK_DOUBLE => sysclk_200, - TXUSRCLK => sysclk_100, - TXUSRCLK_DOUBLE => sysclk_200, + RXUSRCLK => sysclk_120, + RXUSRCLK_DOUBLE => sysclk_240, + TXUSRCLK => sysclk_120, + TXUSRCLK_DOUBLE => sysclk_240, RXUSRCLK_ACTIVE => sysclk_locked, TXUSRCLK_ACTIVE => sysclk_locked, RXPMARESETDONE => open, @@ -426,15 +448,15 @@ begin -- Create a 100 ns test pulse for debugging of microslice timing - process (sysclk_200) is + process (sysclk_240) is begin - if rising_edge(sysclk_200) then + if rising_edge(sysclk_240) then if ms_count = MS_PERIOD_COUNTS - 1 then ms_count <= 0; else ms_count <= ms_count + 1; end if; - if ms_count < 10 then + if ms_count < 24 then trg_out <= '1'; else trg_out <= '0'; @@ -493,7 +515,7 @@ begin COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)) ) port map ( - CLK => sysclk_100, + CLK => sysclk_120, RESET => reset, CLK_EN => '1', MED_DATAREADY_OUT => med_dataready_out, @@ -542,7 +564,7 @@ begin begin trb_parser_i : entity work.trb_parser port map ( - CLK => sysclk_100, + CLK => sysclk_120, RESET => reset, DATA_ACTIVE => hub_data_active(i), DATA_OUT => hub_data_out(32 * i + 31 downto 32 * i), @@ -579,7 +601,7 @@ begin THE_XDNA : entity work.trb_net_xdna port map ( - CLK => sysclk_100, + CLK => sysclk_120, RESET => reset, DATA_OUT => onewire_data, ADDR_OUT => onewire_addr, @@ -603,7 +625,7 @@ begin PORT_MASK_ENABLE => 1 ) port map( - CLK => sysclk_100, + CLK => sysclk_120, RESET => reset, REGIO_RX => ctrlbus_rx_i, REGIO_TX => ctrlbus_tx_i, @@ -630,9 +652,9 @@ begin TERMINATE_UNUSED: - process (sysclk_100) is + process (sysclk_120) is begin - if rising_edge(sysclk_100) then + if rising_edge(sysclk_120) then bustools_tx.data <= (others => '0'); bustc_tx.data <= (others => '0'); bussci1_tx.data <= (others => '0'); diff --git a/hub_test/sw/init.c b/hub_test/sw/init.c index 5d07001..131238a 100644 --- a/hub_test/sw/init.c +++ b/hub_test/sw/init.c @@ -6,7 +6,7 @@ #include "xil_cache.h" #include "xil_printf.h" -#include "Si5345-RevD-CRI_100E-Registers.h" +#include "Si5345-RevD-CRI_120E-Registers.h" #define NUM_PAGES (12) #define SI5345_ADDRESS (0x68) -- 2.43.0