From 0c0d94d7cdaa4e4da1a140097e93b7c2905a4987 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Fri, 26 Apr 2013 11:28:42 +0200 Subject: [PATCH] Litte rewording, mention ROOT --- .../abstract.txt | 5 ++-- .../summary.txt | 27 +++++++++---------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/2013-twepp-neiser-trb3_applications/abstract.txt b/2013-twepp-neiser-trb3_applications/abstract.txt index 3fa5e62..6a6d392 100644 --- a/2013-twepp-neiser-trb3_applications/abstract.txt +++ b/2013-twepp-neiser-trb3_applications/abstract.txt @@ -1,5 +1,5 @@ # Word count by `grep -v '^#' abstract.txt | wc -w` -# Currently 91 (maximum allowed: 100) +# Currently 92 (maximum allowed: 100) The TRB3 features four FPGA-based TDCs with <20ps RMS time precision between two channels and 256+4 channels in total. One central FPGA @@ -9,4 +9,5 @@ platform following the COME&KISS principle: Successful test beamtimes at CERN (CBM), in Juelich and Mainz with an FPGA-based discriminator board (PaDiWa), a charge-to-width FEE board with high dynamic range, read-out of the n-XYTER ASIC and software for data unpacking and TDC -calibration. We conclude with an outlook on future developments. +calibration in ROOT. We conclude with an outlook on future +developments. diff --git a/2013-twepp-neiser-trb3_applications/summary.txt b/2013-twepp-neiser-trb3_applications/summary.txt index 0ea95b9..e604123 100644 --- a/2013-twepp-neiser-trb3_applications/summary.txt +++ b/2013-twepp-neiser-trb3_applications/summary.txt @@ -1,5 +1,5 @@ # Word count by `grep -v '^#' summary.txt | wc -w` -# Currently 500 (maximum allowed: 500) +# Currently 496 (maximum allowed: 500) The 4+1 FPGA board "TRB3" can serve various applications in experimental particle physics and beyond due to its general-purpose @@ -15,16 +15,15 @@ long-term maintainability of the platform. Usually, in each of the four peripheral FPGAs a tapped delay line TDC is implemented with <20ps RMS time precision between two channels providing 64 channels plus one reference channel. The TDCs are used -for leading edge measurements, for example from time of flight -experiments, or by using the TDC channels in pairs, one can -additionally extract the width of the digital pulse. The central FPGA -serves as a flexible central trigger system and manages slow control -and read-out of the peripheral FPGAs over a single gigabit Ethernet -connection. The project provides a comfortable, robust and modular -software environment, ranging from low-level register access to the -FPGA firmwares on the command line to high-level control web2.0 -technologies. This is complemented by comprehensive specifications and -documentation. +for leading edge measurements or by using the TDC channels in pairs, +one can additionally extract the width of the digital pulse. The +central FPGA serves as a flexible central trigger system and manages +slow control and read-out of the peripheral FPGAs over a single +gigabit Ethernet connection. The project provides a comfortable, +robust and modular software environment, ranging from low-level +register access to the FPGA firmwares on the command line to +high-level control via web2.0 technologies. This is complemented by +comprehensive specifications and documentation. To convert the analog signals from the detector to digital pulses suitable for the TDC, the front-end electronics board PaDiWa was @@ -43,14 +42,14 @@ performance of this platform was proven in three test beamtimes with different detectors and FEEs at CERN (CBM), in Juelich and Mainz with up to 2400 channels, of which results are shown. -Furthermore, the TRB3 can be used as an infrastructure to read-out +Furthermore, the TRB3 can be used as an infrastructure to read out specialized integrated solutions using the peripheral FPGAs, for example to provide a timing reference, transport the acquired data to the eventbuilder and slow control configuration of the chip. This was realized for the n-XYTER ASIC. Additionally, the platform enables every user group to profit from common software developments, such as -an unpacker for the TDC datastream including the necessary calibration -of the delay lines. +a ROOT unpacker for the TDC datastream including the necessary +calibration of the delay lines. Finally, we present planned extensions of the platform: The detection of leading and trailing edge in a single TDC channel, which doubles -- 2.43.0