From 0d417ce3276c48513845a05a630f35537edbf0cc Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Thu, 18 Oct 2007 13:12:56 +0000
Subject: [PATCH] updated fifo, Jan

---
 trb_net16_fifo.vhd | 4 +++-
 trb_net_fifo.vhd   | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/trb_net16_fifo.vhd b/trb_net16_fifo.vhd
index 234e653..0a3c988 100644
--- a/trb_net16_fifo.vhd
+++ b/trb_net16_fifo.vhd
@@ -39,7 +39,9 @@ architecture trb_net16_fifo_arch of trb_net16_fifo is
 
   component trb_net_fifo is
     generic (WIDTH : integer := DATA_WIDTH + NUM_WIDTH;   -- FIFO word width
-            DEPTH : integer := DEPTH + 2);
+            DEPTH : integer := DEPTH + 2;
+            FORCE_LUT : integer := 0
+            );
     port (
       CLK    : in std_logic;
       RESET  : in std_logic;
diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd
index 582182c..21174a1 100644
--- a/trb_net_fifo.vhd
+++ b/trb_net_fifo.vhd
@@ -14,7 +14,7 @@ entity trb_net_fifo is
   
   generic (WIDTH : integer := 18;  	-- FIFO word width
            DEPTH : integer := 3;     -- Depth of the FIFO, 2^(n+1)
-           FORCE_LUT : integer range 0 to 1 := 0): --don't allow use of BlockRAM
+           FORCE_LUT : integer range 0 to 1 := 0); --don't allow use of BlockRAM
 
   port (CLK    : in std_logic;  		
         RESET  : in std_logic;  	
-- 
2.43.0