From 0dce6223b90cc4eab6e3b9c431301df3f0463d1a Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 30 Jun 2008 20:47:35 +0000 Subject: [PATCH] *** empty log message *** --- testbench/trb_net16_dummy_apl.vhd | 8 +- trb_net16_api_base.vhd | 8 +- trb_net16_endpoint_0_trg_1_api.vhd | 209 ++--- trb_net16_endpoint_1_trg_2_data_1_regio.vhd | 918 ++++++++++++++++++++ trb_net16_hub_base.vhd | 149 ++-- trb_net16_hub_logic.vhd | 2 +- trb_net16_ibuf.vhd | 5 +- trb_net16_io_multiplexer.vhd | 120 +-- trb_net16_iobuf.vhd | 32 +- trb_net16_term.vhd | 2 +- trb_net16_term_buf.vhd | 66 +- trb_net_pattern_gen.vhd | 2 +- trb_net_std.vhd | 17 + 13 files changed, 1186 insertions(+), 352 deletions(-) create mode 100644 trb_net16_endpoint_1_trg_2_data_1_regio.vhd diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd index 6284520..454225d 100644 --- a/testbench/trb_net16_dummy_apl.vhd +++ b/testbench/trb_net16_dummy_apl.vhd @@ -67,10 +67,12 @@ begin -- address <= x"0008"; -- reghigh <= x"DEAD"; -- reglow <= x"AFFE"; - address <= x"0001"; + address <= READ_ID; --x"0001"; reghigh <= x"0000"; reglow <= x"0000"; - + APL_DTYPE_OUT <= x"8"; + APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; + process(current_state) begin case current_state is @@ -84,9 +86,7 @@ begin end process; APL_READ_OUT <= '1'; --just read, do not check - APL_DTYPE_OUT <= "1000"; APL_ERROR_PATTERN_OUT <= x"12345678"; - APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; --APL_DATA_OUT <= reg_counter; CHECK_1:if TRANSFER_LENGTH >0 generate diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 1c3e1db..b8c6aa2 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -9,13 +9,13 @@ use work.trb_net_std.all; entity trb_net16_api_base is generic ( - API_TYPE : integer range 0 to 1 := c_API_ACTIVE; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 0;--std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_NO; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 52bdaeb..5dc142f 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -18,7 +18,6 @@ entity trb_net16_endpoint_0_trg_1_api is FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL; FIFO_TO_APL_DEPTH : integer range 0 to 6 := 0;--c_FIFO_SMALL; SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL; - MUX_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE; IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE; API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_NON_SECURE_MODE; API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_SECURE_MODE; @@ -111,31 +110,22 @@ component trb_net16_iobuf is RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Internal direction port @@ -245,66 +235,62 @@ end component; component trb_net16_io_multiplexer is - - generic ( - MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? - ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; + CLK : in std_logic; + RESET : in std_logic; CLK_EN : in std_logic; + -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - -- highest bits are mult. - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); + MED_READ_IN: in STD_LOGIC; + -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) + CTRL: in STD_LOGIC_VECTOR (31 downto 0); + STAT: out STD_LOGIC_VECTOR (31 downto 0) ); end component; component trb_net16_term_buf is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_OUT: out std_logic - ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic + ); end component; signal apl_to_buf_INIT_DATAREADY: std_logic; @@ -333,30 +319,25 @@ signal MED_INIT_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal MED_INIT_READ_IN : std_logic; -signal MED_INIT_DATAREADY_IN : std_logic; -signal MED_INIT_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); -signal MED_INIT_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); -signal MED_INIT_READ_OUT : std_logic; +signal MED_IO_DATAREADY_IN : std_logic; +signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_OUT : std_logic; signal MED_REPLY_DATAREADY_OUT : std_logic; signal MED_REPLY_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal MED_REPLY_READ_IN : std_logic; -signal MED_REPLY_DATAREADY_IN : std_logic; -signal MED_REPLY_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); -signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); -signal MED_REPLY_READ_OUT : std_logic; - signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); -signal m_DATAREADY_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); +signal m_DATAREADY_IN : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0); +signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); +signal m_READ_OUT : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0); signal buf_STAT_INIT_BUFFER : std_logic_vector (31 downto 0); signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 downto 0); @@ -377,14 +358,11 @@ begin m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; MED_INIT_READ_IN <= m_READ_IN(i*2); MED_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2); - MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH); - MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2); - MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; + + MED_IO_DATAREADY_IN <= m_DATAREADY_IN(i); + MED_IO_DATA_IN <= m_DATA_IN(c_DATA_WIDTH-1 downto 0); + MED_IO_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0); + m_READ_OUT(i) <= MED_IO_READ_OUT; end generate; genelse: if i /= DAT_CHANNEL generate termbuf: trb_net16_term_buf @@ -396,19 +374,16 @@ begin MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2), MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2), MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) + + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), + MED_READ_OUT => m_READ_OUT(i) + ); end generate; end generate; @@ -574,23 +549,17 @@ IOBUF: trb_net16_iobuf MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, MED_INIT_READ_IN => MED_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => MED_ERROR_IN, + MED_DATAREADY_IN => MED_IO_DATAREADY_IN, + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT, + MED_ERROR_IN => MED_ERROR_IN, MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT, MED_REPLY_READ_IN => MED_REPLY_READ_IN, - - MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => MED_ERROR_IN, - + -- Internal direction port INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, @@ -622,9 +591,7 @@ IOBUF: trb_net16_iobuf STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER; MPLEX: trb_net16_io_multiplexer - generic map ( - MUX_SECURE_MODE => MUX_SECURE_MODE - ) + port map ( CLK => CLK, RESET => RESET, diff --git a/trb_net16_endpoint_1_trg_2_data_1_regio.vhd b/trb_net16_endpoint_1_trg_2_data_1_regio.vhd new file mode 100644 index 0000000..18a5c46 --- /dev/null +++ b/trb_net16_endpoint_1_trg_2_data_1_regio.vhd @@ -0,0 +1,918 @@ +-- an active api together with an iobuf + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + +--Entity decalaration for clock generator +entity trb_net16_endpoint_1_trg_2_api_1_regio is + generic ( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE); + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers + SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers + --standard values for output registers + SCTR_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + SCTR_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + --no data / address out? + SCTR_USE_DATA_PORT : std_logic := '0'; + SCTR_USE_1WIRE_INTERFACE : integer := c_YES; + SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); + SCTR_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + SCTR_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + SCTR_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + MED_STAT_OP : in std_logic_vector (15 downto 0); + MED_CTRL_OP : out std_logic_vector (15 downto 0); + + -- LVL1 trigger APL + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + LVL1_GOT_TRIGGER_OUT : out std_logic; + LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_RELEASE_IN : in std_logic; + + -- IPU-Data Channel APL + IPUD_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + IPUD_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + IPUD_APL_DATAREADY_IN: in std_logic; + IPUD_APL_READ_OUT: out std_logic; + IPUD_APL_SHORT_TRANSFER_IN: in std_logic; + IPUD_APL_DTYPE_IN: in std_logic_vector (3 downto 0); + IPUD_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); + IPUD_APL_SEND_IN: in std_logic; + IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); + IPUD_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + IPUD_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + IPUD_APL_TYP_OUT: out std_logic_vector (2 downto 0); + IPUD_APL_DATAREADY_OUT: out std_logic; + IPUD_APL_READ_IN: in std_logic; + IPUD_APL_RUN_OUT: out std_logic; + IPUD_APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- IPU-Data Channel APL + LVL2_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + LVL2_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + LVL2_APL_DATAREADY_IN: in std_logic; + LVL2_APL_READ_OUT: out std_logic; + LVL2_APL_SHORT_TRANSFER_IN: in std_logic; + LVL2_APL_DTYPE_IN: in std_logic_vector (3 downto 0); + LVL2_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); + LVL2_APL_SEND_IN: in std_logic; + LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); + LVL2_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + LVL2_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + LVL2_APL_TYP_OUT: out std_logic_vector (2 downto 0); + LVL2_APL_DATAREADY_OUT: out std_logic; + LVL2_APL_READ_IN: in std_logic; + LVL2_APL_RUN_OUT: out std_logic; + LVL2_APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Slow Control Data Port + SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); + SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0); + SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0); + SCTR_READ_ENABLE_OUT : out std_logic; + SCTR_WRITE_ENABLE_OUT : out std_logic; + SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0); + SCTR_DATA_IN : in std_logic_vector(32-1 downto 0); + SCTR_DATAREADY_IN : in std_logic; + SCTR_NO_MORE_DATA_IN : in std_logic; + --IDRAM is used if no 1-wire interface, onewire used otherwise + SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + SCTR_IDRAM_WR_IN : in std_logic; + SCTR_ONEWIRE_INOUT : inout std_logic; + + -- Status + STAT_GEN_1: out std_logic_vector (31 downto 0); -- General Status + STAT_GEN_2: out std_logic_vector (31 downto 0) -- General Status + ); +end entity; + +architecture trb_net16_endpoint_1_trg_2_api_1_regio_arch of trb_net16_endpoint_1_trg_2_api_1_regio is + + component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_regIO is + generic ( + REGISTER_WIDTH : integer range 32 to 32 := 32; + ADDRESS_WIDTH : integer range 8 to 16 := 16; + NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers + --standard values for output registers + INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := + (others => '0'); + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := + (others => '1'); + --no data / address out? + NO_DAT_PORT : std_logic := '0'; + + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + --Port to write Unique ID + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + --Common Register in / out + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + --Custom Register in / out + REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + --following ports only used when no internal register is accessed + DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + DAT_NO_MORE_DATA_IN : in std_logic; + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + + + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_ACTIVE; + FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted + APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_MASTER_DATAREADY_OUT: out std_logic; + INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN: in std_logic; + + INT_MASTER_DATAREADY_IN: in std_logic; + INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT: out std_logic; + + + INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the SLAVE path) + INT_SLAVE_DATAREADY_OUT: out std_logic; + INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN: in std_logic; + + INT_SLAVE_DATAREADY_IN: in std_logic; + INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT: out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); + end component; + + + + component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); + MED_READ_IN: in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL: in STD_LOGIC_VECTOR (31 downto 0); + STAT: out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + + component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic + ); + end component; + component trb_net16_term is + generic ( + USE_APL_PORT : integer range 0 to 1 := 0; + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + APL_GOT_TRM: out std_logic; + APL_RELEASE_TRM: in std_logic; + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr + -- Status and control port + ); + end component; +signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0); +signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0); + +signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0); +signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0); + +signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0); +signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0); + +signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0); +signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); + +-- for the connection to the multiplexer +signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); +signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); + +signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); +signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_IN : std_logic_vector(7 downto 0); + +signal buf_APL_DATA_IN : std_logic_vector(3*c_DATA_WIDTH-1 downto 0); +signal buf_APL_PACKET_NUM_IN : std_logic_vector(3*c_NUM_WIDTH-1 downto 0); +signal buf_APL_DATAREADY_IN : std_logic_vector(2 downto 0); +signal buf_APL_READ_OUT : std_logic_vector(2 downto 0); +signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(2 downto 0); +signal buf_APL_DTYPE_IN : std_logic_vector(3*4-1 downto 0); +signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(3*32-1 downto 0); +signal buf_APL_SEND_IN : std_logic_vector(2 downto 0); +signal buf_APL_TARGET_ADDRESS_IN : std_logic_vector(3*16-1 downto 0); +signal buf_APL_DATA_OUT : std_logic_vector(3*c_DATA_WIDTH-1 downto 0); +signal buf_APL_PACKET_NUM_OUT : std_logic_vector(3*c_NUM_WIDTH-1 downto 0); +signal buf_APL_DATAREADY_OUT : std_logic_vector(2 downto 0); +signal buf_APL_READ_IN : std_logic_vector(2 downto 0); +signal buf_APL_TYP_OUT : std_logic_vector(3*3-1 downto 0); +signal buf_APL_RUN_OUT : std_logic_vector(2 downto 0); +signal buf_APL_SEQNR_OUT : std_logic_vector(3*8-1 downto 0); + +signal MY_ADDRESS : std_logic_vector(15 downto 0); + +signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0); +signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0); +signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); +signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0); +signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); +signal MPLEX_CTRL : std_logic_vector(31 downto 0); +signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0); + +signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); + +signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); +signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); +signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); +signal buf_IDRAM_WR_IN : std_logic; + +begin + + MED_CTRL_OP(15) <= MED_STAT_OP(15); + MED_CTRL_OP(14 downto 0) <= (others => '0'); + + --Connections for data channel + genbuffers : for i in 0 to 3 generate + geniobuf: if USE_CHANNEL(i) = c_YES generate + IOBUF: trb_net16_iobuf + generic map ( + IBUF_DEPTH => IBUF_DEPTH(i), + IBUF_SECURE_MODE => IBUF_SECURE_MODE(i), + SBUF_VERSION => 0, + USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i), + USE_VENDOR_CORES => c_YES, + USE_CHECKSUM => cfg_USE_CHECKSUM(i), + INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i), + REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i) + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => MED_IO_READ_IN(i*2), + + MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT(i), + MED_ERROR_IN => MED_ERROR_IN, + + MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), + + -- Status and control port + STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32), + STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32), + CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32), + STAT_CTRL_IBUF_BUFFER => buf_STAT_CTRL_INIT_BUFFER(32*(i+1)-1 downto i*32) + ); + genactapi : if API_TYPE(i) = c_API_ACTIVE and i /= 0 generate + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => API_TYPE(i), + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0 + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + APL_DATAREADY_IN => buf_APL_DATAREADY_IN(i), + APL_READ_OUT => buf_APL_READ_OUT(i), + APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(i), + APL_DTYPE_IN => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4), + APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), + APL_SEND_IN => buf_APL_SEND_IN(i), + APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16), + -- Receiver port + APL_DATA_OUT => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + APL_TYP_OUT => buf_APL_TYP_OUT((i+1)*3-1 downto i*3), + APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(i), + APL_READ_IN => buf_APL_READ_IN(i), + -- APL Control port + APL_RUN_OUT => buf_APL_RUN_OUT(i), + APL_MY_ADDRESS_IN => MY_ADDRESS, + APL_SEQNR_OUT => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i), + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) + ); + end generate; + genpasapi : if API_TYPE(i) = c_API_PASSIVE and i /= 0 generate + constant j : integer := i-1; + begin + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => API_TYPE(i), + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0 + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j), + APL_READ_OUT => buf_APL_READ_OUT(j), + APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j), + APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4), + APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32), + APL_SEND_IN => buf_APL_SEND_IN(j), + APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((j+1)*16-1 downto j*16), + -- Receiver port + APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3), + APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j), + APL_READ_IN => buf_APL_READ_IN(j), + -- APL Control port + APL_RUN_OUT => buf_APL_RUN_OUT(j), + APL_MY_ADDRESS_IN => MY_ADDRESS, + APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_SLAVE_HEADER_IN => '0', + INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) + ); + end generate; + gentrgapi : if i = 0 generate + trglvl1 : trb_net16_term + generic map( + USE_APL_PORT => c_NO, + SECURE_MODE => std_TERM_SECURE_MODE + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + + INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_IN => apl_to_buf_REPLY_READ(i), + + INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_OUT => buf_to_apl_INIT_READ(i), + + -- "mini" APL, just to see the triggers coming in + APL_DTYPE_OUT => LVL1_DTYPE_OUT, + APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT, + APL_SEQNR_OUT => LVL1_SEQNR_OUT, + APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT, + APL_RELEASE_TRM => LVL1_RELEASE_IN, + APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN + ); + end generate; + end generate; + gentermbuf: if USE_CHANNEL(i) = c_NO generate + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT(i), + + MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => MED_IO_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1) + ); + end generate; + end generate; + + + buf_APL_DATA_IN(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH) <= IPUD_APL_DATA_IN; + buf_APL_DATA_IN(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH) <= LVL2_APL_DATA_IN; + buf_APL_PACKET_NUM_IN(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH) <= IPUD_APL_PACKET_NUM_IN; + buf_APL_PACKET_NUM_IN(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH) <= LVL2_APL_PACKET_NUM_IN; + buf_APL_DATAREADY_IN(0) <= IPUD_APL_DATAREADY_IN; + buf_APL_DATAREADY_IN(1) <= LVL2_APL_DATAREADY_IN; + IPUD_APL_READ_OUT <= buf_APL_READ_OUT(0); + LVL2_APL_READ_OUT <= buf_APL_READ_OUT(1); + buf_APL_SHORT_TRANSFER_IN(0) <= IPUD_APL_SHORT_TRANSFER_IN; + buf_APL_SHORT_TRANSFER_IN(1) <= LVL2_APL_SHORT_TRANSFER_IN; + buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN; + buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN; + buf_APL_ERROR_PATTERN_IN(1*32-1 downto 0*32) <= IPUD_APL_ERROR_PATTERN_IN; + buf_APL_ERROR_PATTERN_IN(2*32-1 downto 1*32) <= LVL2_APL_ERROR_PATTERN_IN; + buf_APL_SEND_IN(0) <= IPUD_APL_SEND_IN; + buf_APL_SEND_IN(1) <= LVL2_APL_SEND_IN; + buf_APL_TARGET_ADDRESS_IN(1*16-1 downto 0*16) <= IPUD_APL_TARGET_ADDRESS_IN; + buf_APL_TARGET_ADDRESS_IN(2*16-1 downto 1*16) <= LVL2_APL_TARGET_ADDRESS_IN; + + IPUD_APL_DATA_OUT <= buf_APL_DATA_OUT(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH); + LVL2_APL_DATA_OUT <= buf_APL_DATA_OUT(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH); + IPUD_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH); + LVL2_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH); + IPUD_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(0); + LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(1); + buf_APL_READ_IN(0) <= IPUD_APL_READ_IN; + buf_APL_READ_IN(1) <= LVL2_APL_READ_IN; + + buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN; + buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN; + IPUD_APL_RUN_OUT <= buf_APL_RUN_OUT(0); + LVL2_APL_RUN_OUT <= buf_APL_RUN_OUT(1); + IPUD_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8); + LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(2*8-1 downto 1*8); + + regIO : trb_net16_regIO + generic map( + REGISTER_WIDTH => 32, + ADDRESS_WIDTH => 16, + NUM_STAT_REGS => SCTR_NUM_STAT_REGS, + NUM_CTRL_REGS => SCTR_NUM_CTRL_REGS, + --standard values for output registers + INIT_CTRL_REGS => SCTR_INIT_CTRL_REGS, + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS => SCTR_USED_CTRL_REGS, + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK, + --no data / address out? + NO_DAT_PORT => SCTR_USE_DATA_PORT, + INIT_ADDRESS => SCTR_INIT_ADDRESS, + INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID, + COMPILE_TIME => SCTR_COMPILE_TIME, + COMPILE_VERSION => SCTR_COMPILE_VERSION, + HARDWARE_VERSION => SCTR_HARDWARE_VERSION + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- Port to API + API_DATA_OUT => buf_APL_DATA_IN(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH), + API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH), + API_DATAREADY_OUT => buf_APL_DATAREADY_IN(2), + API_READ_IN => buf_APL_READ_OUT(2), + API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(2), + API_DTYPE_OUT => buf_APL_DTYPE_IN(3*4-1 downto 2*4), + API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN(3*32-1 downto 2*32), + API_SEND_OUT => buf_APL_SEND_IN(2), + API_TARGET_ADDRESS_OUT => buf_APL_TARGET_ADDRESS_IN(3*16-1 downto 2*16), + API_DATA_IN => buf_APL_DATA_OUT(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH), + API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH), + API_TYP_IN => buf_APL_TYP_OUT(3*3-1 downto 2*3), + API_DATAREADY_IN => buf_APL_DATAREADY_OUT(2), + API_READ_OUT => buf_APL_READ_IN(2), + API_RUN_IN => buf_APL_RUN_OUT(2), + API_SEQNR_IN => buf_APL_SEQNR_OUT(3*8-1 downto 2*8), + --Port to write Unique ID + IDRAM_DATA_IN => buf_IDRAM_DATA_IN, + IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT, + IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, + IDRAM_WR_IN => buf_IDRAM_WR_IN, + MY_ADDRESS_OUT => MY_ADDRESS, + --Common Register in / out + COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, + COMMON_CTRL_REG_OUT => SCTR_COMMON_CTRL_REG_OUT, + --Custom Register in / out + REGISTERS_IN => SCTR_REGISTERS_IN, + REGISTERS_OUT => SCTR_REGISTERS_OUT, + --following ports only used when no internal register is accessed + DAT_ADDR_OUT => SCTR_ADDR_OUT, + DAT_READ_ENABLE_OUT => SCTR_READ_ENABLE_OUT, + DAT_WRITE_ENABLE_OUT => SCTR_WRITE_ENABLE_OUT, + DAT_DATA_OUT => SCTR_DATA_OUT, + DAT_DATA_IN => SCTR_DATA_IN, + DAT_DATAREADY_IN => SCTR_DATAREADY_IN, + DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN, + STAT => SCTR_REGIO_STAT + ); + + gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate + buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN; + buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN; + buf_IDRAM_WR_IN <= SCTR_IDRAM_WR_IN; + SCTR_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT; + SCTR_ONEWIRE_INOUT <= '0'; + buf_COMMON_STAT_REG_IN <= SCTR_COMMON_STAT_REG_IN; + end generate; + gen_1wire : if SCTR_USE_1WIRE_INTERFACE = 1 generate + buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0); + buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32); + + onewire_interface : trb_net_onewire + generic map( + USE_TEMPERATURE_READOUT => 1, + CLK_PERIOD => 10 + ) + port map( + CLK => CLK, + RESET => RESET, + --connection to 1-wire interface + ONEWIRE => SCTR_ONEWIRE_INOUT, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => buf_IDRAM_DATA_IN, + ADDR_OUT => buf_IDRAM_ADDR_IN, + WRITE_OUT=> buf_IDRAM_WR_IN, + TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20), + STAT => open + ); + end generate; + + + MPLEX: trb_net16_io_multiplexer + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => MED_IO_DATAREADY_IN, + INT_DATA_OUT => MED_IO_DATA_IN, + INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN, + INT_READ_IN => MED_IO_READ_OUT, + INT_DATAREADY_IN => MED_IO_DATAREADY_OUT, + INT_DATA_IN => MED_IO_DATA_OUT, + INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT, + INT_READ_OUT => MED_IO_READ_IN, + CTRL => MPLEX_CTRL + ); + +end architecture; + diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 79908fd..6e0a971 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -12,8 +12,8 @@ entity trb_net16_hub_base is --general settings MUX_SECURE_MODE : integer range 0 to 1 := c_NO; --hub control - HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL; - HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; + HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 3;--c_SLOW_CTRL_CHANNEL; + HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4; HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); @@ -94,10 +94,10 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); - signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); - signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); - signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); - signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0); + signal m_DATA_IN : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0); signal m_ERROR_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*3-1 downto 0); signal hub_to_buf_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0); @@ -217,37 +217,38 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is ); end component; - component trb_net16_io_multiplexer is - generic ( - MUX_SECURE_MODE : integer range 0 to 1 := c_NO - ); port( -- Misc CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; + -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); + MED_READ_IN: in STD_LOGIC; + -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH *(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH *(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) + CTRL: in STD_LOGIC_VECTOR (31 downto 0); + STAT: out STD_LOGIC_VECTOR (31 downto 0) ); end component; @@ -273,20 +274,18 @@ end component; MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; -- Media is reading - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; -- Media is reading - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; -- buffer reads a word from media + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + -- Internal direction port INT_INIT_DATAREADY_OUT: out std_logic; INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word @@ -495,20 +494,15 @@ end component; MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_OUT: out std_logic + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic ); end component; @@ -568,9 +562,6 @@ begin constant t : integer := 0; begin MPLEX: trb_net16_io_multiplexer - generic map ( - MUX_SECURE_MODE => MUX_SECURE_MODE - ) port map ( CLK => CLK, RESET => RESET, @@ -583,10 +574,10 @@ begin MED_DATA_OUT => MED_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_IN => MED_READ_IN(i), - INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), - INT_DATA_OUT => m_DATA_IN((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH), - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto i*c_NUM_WIDTH*2**c_MUX_WIDTH), - INT_READ_IN => m_READ_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), + INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)), + INT_DATA_OUT => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_IN => m_READ_OUT((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)), INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), INT_DATA_IN => m_DATA_OUT((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH), INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto i*c_NUM_WIDTH*2**c_MUX_WIDTH), @@ -618,24 +609,30 @@ begin MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), MED_INIT_READ_IN => m_READ_IN(i*2), - - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), +-- +-- MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), +-- MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), +-- MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), +-- MED_INIT_READ_OUT => m_READ_OUT(i*2), +-- MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), MED_REPLY_READ_IN => m_READ_IN(i*2+1), - - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1), - MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - +-- +-- MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), +-- MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), +-- MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), +-- MED_REPLY_READ_OUT => m_READ_OUT(i*2+1), +-- MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + MED_READ_OUT => m_READ_OUT(i), + MED_ERROR_IN => m_ERROR_IN((j+1)*3-1 downto j*3), + -- Internal direction port INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), @@ -678,19 +675,15 @@ begin MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_OUT => m_READ_OUT(i*2), MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) - ); + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + MED_READ_OUT => m_READ_OUT(i) + ); end generate; end generate; end generate; @@ -1228,8 +1221,8 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --8x CTRL, 8x STAT - buf_HUB_STAT_GEN(3 downto 0) <= MED_PACKET_NUM_IN; - buf_HUB_STAT_GEN(5 downto 4) <= MED_DATAREADY_IN; + buf_HUB_STAT_GEN(3 downto 0) <= MED_PACKET_NUM_IN(3 downto 0); + buf_HUB_STAT_GEN(5 downto 4) <= MED_DATAREADY_IN(1 downto 0); buf_HUB_STAT_GEN(7 downto 6) <= HUB_MED_CONNECTED(1 downto 0); buf_HUB_STAT_GEN(15 downto 8) <= buf_STAT_POINTS_locked(7 downto 0); buf_HUB_STAT_GEN(19 downto 16) <= (others => '0'); diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 729423c..dcb49a3 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -189,7 +189,7 @@ STAT(5) <= comb_REPLY_muxed_DATA(14); STAT(6) <= REPLY_DATA_IN(14); STAT(7) <= REPLY_DATA_IN(30); -STAT(8) <= REPLY_DATA_IN(46); +STAT(8) <= '0';--REPLY_DATA_IN(46); STAT(9) <= locked; STAT(15 downto 10) <= (others => '0'); diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index e6c7d7c..e7b6afe 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -452,7 +452,10 @@ begin when others => STAT_BUFFER(13 downto 12) <= "11"; end case; end process; - STAT_BUFFER(31 downto 14) <= (others => '0'); + + STAT_BUFFER(14) <= fifo_write; + STAT_BUFFER(17 downto 15) <= current_packet_type(2 downto 0); + STAT_BUFFER(31 downto 18) <= (others => '0'); INT_ERROR_OUT <= MED_ERROR_IN; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 0afaa82..4dff348 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -9,10 +9,6 @@ use work.trb_net_std.all; entity trb_net16_io_multiplexer is - generic ( - MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? - ); - port( -- Misc CLK : in std_logic; @@ -31,10 +27,10 @@ entity trb_net16_io_multiplexer is MED_READ_IN: in STD_LOGIC; -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); @@ -51,15 +47,7 @@ end trb_net16_io_multiplexer; architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is - component trb_net_pattern_gen is - generic ( - WIDTH : integer := 1 - ); - port( - INPUT_IN : in STD_LOGIC_VECTOR (c_MUX_WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0) - ); - end component; + component trb_net16_sbuf is generic ( @@ -102,8 +90,8 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is ); end component; - signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); - signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); + signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH-1)-1 downto 0); + signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC; signal final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); @@ -114,75 +102,46 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal current_mux_packet_number : std_logic_vector (1 downto 0); signal last_mux_enable : std_logic; signal arbiter_CLK_EN : std_logic; - signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - signal demux_comb_dataready_in : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR ((c_DATA_WIDTH)-1 downto 0); + signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (1 downto 0); +-- signal demux_comb_dataready_in : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); begin ------------------------------------------------------------------------------- -- DEMUX ------------------------------------------------------------------------------ - gensbuf: if MUX_SECURE_MODE = 1 generate - G1: for i in 0 to 2**c_MUX_WIDTH-1 generate - demux_comb_dataready_in(i) <= next_demux_dr(i) and MED_DATAREADY_IN; - DEMUX_SBUF: trb_net16_sbuf - generic map ( - VERSION => std_SBUF_VERSION - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => demux_comb_dataready_in(i), - COMB_next_READ_OUT => demux_next_READ(i), - COMB_READ_IN => current_demux_READ(i), - COMB_DATA_IN => MED_DATA_IN, - COMB_PACKET_NUM_IN => MED_PACKET_NUM_IN, - SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i), - SYN_DATA_OUT => INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)), - SYN_PACKET_NUM_OUT => INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i), - SYN_READ_IN => INT_READ_IN(i) - ); - end generate; - end generate; - - genff: if MUX_SECURE_MODE = 0 generate + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= (others => '0'); + buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= (others => '0'); + else + buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= MED_DATA_IN; + buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= MED_PACKET_NUM_IN; + end if; + end if; + end process; + G2: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= (others => '0'); - buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= (others => '0'); - INT_DATAREADY_OUT(0) <= '0'; + INT_DATAREADY_OUT(i) <= '0'; else - buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= MED_DATA_IN; - buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= MED_PACKET_NUM_IN; - INT_DATAREADY_OUT(0) <= next_demux_dr(0) and MED_DATAREADY_IN; + INT_DATAREADY_OUT(i) <= next_demux_dr(i) and MED_DATAREADY_IN; end if; end if; end process; - G2: for i in 1 to 2**c_MUX_WIDTH-1 generate - buf_INT_DATA_OUT (c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i) <= buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0); - buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH*(i+1)-1 downto c_NUM_WIDTH*i) <= buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0); - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - INT_DATAREADY_OUT(i) <= '0'; - else - INT_DATAREADY_OUT(i) <= next_demux_dr(i) and MED_DATAREADY_IN; - end if; - end if; - end process; - end generate; + end generate; + INT_DATA_OUT <= buf_INT_DATA_OUT; INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; - end generate; + --current_demux_READ <= INT_READ_IN; - gen2: if MUX_SECURE_MODE = 0 generate - demux_next_READ <= (others => '1'); - end generate; + demux_next_READ <= (others => '1'); MED_READ_OUT <= current_MED_READ_OUT; comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN, @@ -192,7 +151,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is next_demux_dr <= demux_dr_tmp; --(others => '0'); current_demux_READ <= (others => '0'); -- generate the READ_OUT - next_MED_READ_OUT <= and_all(demux_next_READ or INT_READ_IN); + next_MED_READ_OUT <= '1'; --and_all(demux_next_READ or INT_READ_IN); -- -- (follow instruction on sbuf) current_demux_READ <= (others => '0'); @@ -212,14 +171,15 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- define next DRx -- the output of the pattern generator is only valid for packet number 00! - DEFDR: trb_net_pattern_gen - generic map ( - WIDTH => c_MUX_WIDTH - ) - port map ( - INPUT_IN => MED_DATA_IN(3+c_MUX_WIDTH-1 downto 3), - RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case - ); +-- DEFDR: trb_net_pattern_gen +-- generic map ( +-- WIDTH => c_MUX_WIDTH-1 +-- ) +-- port map ( +-- INPUT_IN => MED_DATA_IN(4+c_MUX_WIDTH-2 downto 4), +-- RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case +-- ); + next_demux_dr_tmp <= conv_std_logic_vector(2**conv_integer(MED_DATA_IN(4+c_MUX_WIDTH-2 downto 4)),2**(c_MUX_WIDTH-1)); keep_valid_demux : process(CLK) begin diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 113d58c..375c25b 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -30,22 +30,19 @@ entity trb_net16_iobuf is MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); - MED_REPLY_DATAREADY_OUT: out std_logic; MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_OUT: out std_logic; - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + + -- Internal direction port @@ -198,9 +195,9 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is begin GEN_IBUF: if IBUF_DEPTH>0 generate - ibuf_dataready_in <= MED_INIT_DATAREADY_IN or MED_REPLY_DATAREADY_IN; - MED_INIT_READ_OUT <= ibuf_read_out; - MED_REPLY_READ_OUT <= ibuf_read_out; + ibuf_dataready_in <= MED_DATAREADY_IN;-- or MED_REPLY_DATAREADY_IN; + MED_READ_OUT <= ibuf_read_out; +-- MED_REPLY_READ_OUT <= ibuf_read_out; IBUF : trb_net16_ibuf generic map ( @@ -216,10 +213,10 @@ begin RESET => RESET, CLK_EN => CLK_EN, MED_DATAREADY_IN => ibuf_dataready_in, - MED_DATA_IN => MED_INIT_DATA_IN, - MED_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, MED_READ_OUT => ibuf_read_out, - MED_ERROR_IN => MED_INIT_ERROR_IN, + MED_ERROR_IN => MED_ERROR_IN, INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, INT_INIT_DATA_OUT => INT_INIT_DATA_OUT, INT_INIT_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, @@ -357,6 +354,7 @@ begin end generate; end generate; +STAT_IBUF_BUFFER <= IBUF_stat_buffer; -- build the registers according to the wiki page -- STAT_BUFFER(15 downto 0) diff --git a/trb_net16_term.vhd b/trb_net16_term.vhd index a530da5..1fd9b90 100644 --- a/trb_net16_term.vhd +++ b/trb_net16_term.vhd @@ -15,7 +15,7 @@ use work.trb_net_std.all; entity trb_net16_term is generic ( - USE_APL_PORT : integer range 0 to 1 := 0; + USE_APL_PORT : integer range 0 to 1 := c_YES; --even when 0, ERROR_PACKET_IN is used for automatic replys SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE --if secure_mode is not used, apl must provide error pattern and dtype until diff --git a/trb_net16_term_buf.vhd b/trb_net16_term_buf.vhd index dc04115..6a63747 100644 --- a/trb_net16_term_buf.vhd +++ b/trb_net16_term_buf.vhd @@ -21,27 +21,22 @@ entity trb_net16_term_buf is MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_OUT: out std_logic + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic ); end entity; architecture trb_net16_term_buf_arch of trb_net16_term_buf is signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0); - signal INIT_saved_packet_type : std_logic_vector(2 downto 0); + signal saved_packet_type : std_logic_vector(3 downto 0); signal INIT_transfer_counter : std_logic_vector(1 downto 0); signal buf_MED_INIT_DATAREADY_OUT, next_MED_INIT_DATAREADY_OUT : std_logic; signal buf_MED_INIT_DATA_OUT, next_MED_INIT_DATA_OUT : std_logic_vector(15 downto 0); @@ -58,32 +53,26 @@ architecture trb_net16_term_buf_arch of trb_net16_term_buf is signal send_REPLY_trm : std_logic; signal next_send_REPLY_trm : std_logic; signal sent_REPLY_trm : std_logic; - + signal init_channel : std_logic; signal sending_REPLY_ACK, next_sending_REPLY_ACK : std_logic; begin - MED_INIT_READ_OUT <= '1'; - MED_REPLY_READ_OUT <= '1'; + MED_READ_OUT <= '1'; - process(MED_INIT_DATAREADY_IN, MED_INIT_PACKET_NUM_IN, MED_INIT_DATA_IN, - MED_REPLY_DATAREADY_IN, MED_REPLY_PACKET_NUM_IN, MED_REPLY_DATA_IN, - send_INIT_ack, send_REPLY_trm, + process(MED_DATAREADY_IN, MED_PACKET_NUM_IN, MED_DATA_IN, + send_INIT_ack, send_REPLY_trm, REPLY_transfer_counter, REPLY_saved_packet_type, MED_INIT_READ_IN, - INIT_SEQNR, INIT_transfer_counter, INIT_saved_packet_type, MED_REPLY_READ_IN, + INIT_SEQNR, INIT_transfer_counter, saved_packet_type, MED_REPLY_READ_IN, buf_MED_INIT_DATA_OUT, buf_MED_REPLY_DATA_OUT, buf_MED_INIT_DATAREADY_OUT, buf_MED_REPLY_DATAREADY_OUT) begin sent_INIT_ack <= '0'; --- sent_REPLY_ack <= '0'; sent_REPLY_trm <= '0'; next_send_INIT_ack <= send_INIT_ack; --- next_send_REPLY_ack <= send_REPLY_ack; next_send_REPLY_trm <= send_REPLY_trm; --- next_sending_REPLY_ACK <= sending_REPLY_ACK; next_MED_INIT_DATA_OUT <= buf_MED_INIT_DATA_OUT; next_MED_INIT_DATAREADY_OUT <= '0'; next_MED_REPLY_DATA_OUT <= buf_MED_REPLY_DATA_OUT; next_MED_REPLY_DATAREADY_OUT <= '0'; - next_INIT_SEQNR <= INIT_SEQNR; --output INIT data @@ -94,10 +83,9 @@ begin next_MED_INIT_DATA_OUT(2 downto 0) <= TYPE_ACK; elsif INIT_transfer_counter = "01" then next_MED_INIT_DATA_OUT(3 downto 0) <= "0111"; - elsif INIT_transfer_counter = "10" then - if MED_INIT_READ_IN = '1' then - next_send_INIT_ack <= '0'; - end if; + end if; + if INIT_transfer_counter = "10" then + next_send_INIT_ack <= '0'; end if; end if; end if; @@ -109,28 +97,27 @@ begin next_MED_REPLY_DATA_OUT(2 downto 0) <= TYPE_TRM; elsif REPLY_transfer_counter = "10" then next_MED_REPLY_DATA_OUT(11 downto 4) <= INIT_SEQNR; - next_MED_REPLY_DATA_OUT(3 downto 0) <= "0000"; next_send_REPLY_trm <= '0'; end if; end if; end if; -- input data - if MED_INIT_DATAREADY_IN = '1' then - if MED_INIT_PACKET_NUM_IN = "11" then - if INIT_saved_packet_type = TYPE_EOB then + if MED_DATAREADY_IN = '1' then + if MED_PACKET_NUM_IN = "11" then + if saved_packet_type = '0' & TYPE_EOB then next_send_INIT_ack <= '1'; next_MED_INIT_DATAREADY_OUT <= '1'; next_MED_INIT_DATA_OUT(2 downto 0) <= TYPE_ACK; end if; - if INIT_saved_packet_type = TYPE_TRM then + if saved_packet_type = '0' & TYPE_TRM then next_send_INIT_ack <= '1'; next_MED_INIT_DATAREADY_OUT <= '1'; next_MED_INIT_DATA_OUT(2 downto 0) <= TYPE_ACK; next_send_REPLY_trm <= '1'; next_MED_REPLY_DATA_OUT(2 downto 0) <= TYPE_TRM; next_MED_REPLY_DATAREADY_OUT <= '1'; - next_INIT_SEQNR <= MED_INIT_DATA_IN(11 downto 4); + next_INIT_SEQNR <= MED_DATA_IN(11 downto 4); end if; end if; end if; @@ -218,20 +205,11 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - INIT_saved_packet_type <= "111"; - elsif MED_INIT_PACKET_NUM_IN = "00" then - INIT_saved_packet_type <= MED_INIT_DATA_IN(2 downto 0); - end if; - end if; - end process; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - REPLY_saved_packet_type <= "111"; - elsif MED_REPLY_PACKET_NUM_IN = "00" then - REPLY_saved_packet_type <= MED_REPLY_DATA_IN(2 downto 0); + saved_packet_type <= "1111"; + elsif MED_PACKET_NUM_IN = "00" then + saved_packet_type <= MED_DATA_IN(3 downto 0); end if; end if; end process; + end architecture; diff --git a/trb_net_pattern_gen.vhd b/trb_net_pattern_gen.vhd index 6f017db..9e24f4e 100644 --- a/trb_net_pattern_gen.vhd +++ b/trb_net_pattern_gen.vhd @@ -13,7 +13,7 @@ use work.trb_net_std.all; entity trb_net_pattern_gen is generic ( - WIDTH : integer := 3 + WIDTH : integer := 2 ); port( INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); diff --git a/trb_net_std.vhd b/trb_net_std.vhd index c52117b..0b93ab6 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -61,6 +61,7 @@ package trb_net_std is constant std_TERM_SECURE_MODE : integer := c_NO; constant std_MUX_SECURE_MODE : integer := c_NO; constant std_FORCE_REPLY : integer := c_YES; + constant cfg_USE_CHECKSUM : channel_config_t := (c_NO ,c_YES,c_YES,c_YES); constant cfg_USE_ACKNOWLEDGE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); constant cfg_FORCE_REPLY : channel_config_t := (c_YES,c_YES,c_YES,c_YES); constant cfg_USE_REPLY_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); @@ -94,8 +95,11 @@ package trb_net_std is constant READ_ID : std_logic_vector(15 downto 0) := x"5B1D"; --common registers + --maximum: 4, because of regio implementation constant std_COMSTATREG : integer := 2; constant std_COMCTRLREG : integer := 1; + --needed address width for common registers + constant std_COMneededwidth : integer := 1; --RegIO operation dtype constant c_network_control_type : std_logic_vector(3 downto 0) := x"F"; @@ -121,6 +125,9 @@ package trb_net_std is function is_time_reached (timer : integer; time : integer; period : integer) return std_logic; + + function MAX(x : integer; y : integer) + return integer; end package trb_net_std; @@ -203,6 +210,16 @@ package body trb_net_std is end if; if i = 1 then return '1'; else return '0'; end if; end is_time_reached; + + function MAX(x : integer; y : integer) + return integer is + begin + if x > y then + return x; + else + return y; + end if; + end MAX; end package body trb_net_std; -- 2.43.0