From 0e60273175ee34354666df1045c77029505b1f3e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 14 Jul 2015 17:44:40 +0200 Subject: [PATCH] add rate setting feature to SPI interface --- special/spi_ltc2600.vhd | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd index 73a6d95..27cf185 100644 --- a/special/spi_ltc2600.vhd +++ b/special/spi_ltc2600.vhd @@ -48,7 +48,7 @@ architecture spi_ltc2600_arch of spi_ltc2600 is signal word_count : integer range 0 to BITS-1; signal bit_count : integer range 0 to BITS-1; - signal time_count : integer range 0 to WAITCYCLES; + signal time_count : integer range 0 to 1023; signal readback : std_logic_vector(31 downto 0); signal blocked : std_logic; signal sudolock : std_logic; @@ -57,6 +57,8 @@ architecture spi_ltc2600_arch of spi_ltc2600 is signal fsm_state : fsm_t; signal word_length : integer range 0 to BITS := BITS; + signal wait_cycles : integer range 0 to 1023 := WAITCYCLES; + begin PROC_MEM : process @@ -80,6 +82,8 @@ begin invert_reg <= BUS_DATA_IN(0); elsif BUS_ADDR_IN(3 downto 0) = x"9" then -- 0x19 word_length <= to_integer(unsigned(BUS_DATA_IN(5 downto 0))); + elsif BUS_ADDR_IN(3 downto 0) = x"a" then -- 0x1a + wait_cycles <= to_integer(unsigned(BUS_DATA_IN(9 downto 0))); elsif BUS_ADDR_IN(3 downto 0) = x"1" then --0x11 ctrl_reg <= BUS_DATA_IN; blocked <= BUS_DATA_IN(16); @@ -118,6 +122,9 @@ begin elsif BUS_ADDR_IN(3 downto 0) = x"9" then BUS_DATA_OUT <= (others => '0'); BUS_DATA_OUT(5 downto 0) <= std_logic_vector(to_unsigned(word_length,6)); + elsif BUS_ADDR_IN(3 downto 0) = x"a" then + BUS_DATA_OUT <= (others => '0'); + BUS_DATA_OUT(9 downto 0) <= std_logic_vector(to_unsigned(wait_cycles,10)); end if; BUS_ACK_OUT <= '1'; end if; @@ -139,7 +146,7 @@ begin ram_addr <= 0; word_count <= to_integer(unsigned(ctrl_reg(4 downto 0))); bit_count <= word_length-1; - time_count <= WAITCYCLES; + time_count <= wait_cycles; fsm_state <= WAIT_STATE; spi_cs <= not chipselect_reg; spi_sck <= '1'; @@ -156,7 +163,7 @@ begin end if; when SET => - time_count <= WAITCYCLES; + time_count <= wait_cycles; spi_sck <= not spi_sck; if spi_sck = '1' then spi_sd <= ram_data(bit_count); @@ -203,18 +210,18 @@ begin spi_cs <= not chipselect_reg; bit_count <= word_length-1; fsm_state <= WAIT_STATE; - time_count <= WAITCYCLES; + time_count <= wait_cycles; end if; when TOGGLE_CS_2 => time_count <= time_count - 1; if time_count = 0 then spi_sck <= not spi_sck; fsm_state <= WAIT_STATE; - time_count <= WAITCYCLES; + time_count <= wait_cycles; end if; when FINISH => if time_count = 0 and spi_sck = '0' then - time_count <= WAITCYCLES; + time_count <= wait_cycles; spi_sck <= not spi_sck; readback <= readback(30 downto 0) & SPI_SDI_IN; elsif time_count = 0 and spi_sck = '1' then @@ -231,7 +238,7 @@ begin -- Outputs - Invert : process(invert_reg) + Invert : process(invert_reg, spi_cs,spi_sck,spi_sd) begin if invert_reg = '1' then SPI_CS_OUT <= not spi_cs; -- 2.43.0