From 0e8868b14b32bdc5d9a25307a4bbb6247c9df2a5 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 6 Nov 2007 12:36:52 +0000 Subject: [PATCH] removed renamed files, Jan --- trb_net16_active_api.vhd | 221 ----- trb_net16_apimbuf.vhd | 646 -------------- trb_net16_base_api.vhd | 813 ------------------ trb_net16_base_hub.vhd | 450 ---------- trb_net16_base_hub_logic.vhd | 107 --- trb_net16_passive_api.vhd | 221 ----- ...et16_trigger_receiver_apimbuf_endpoint.vhd | 797 ----------------- trb_net16_trigger_receiver_endpoint.vhd | 468 ---------- 8 files changed, 3723 deletions(-) delete mode 100644 trb_net16_active_api.vhd delete mode 100644 trb_net16_apimbuf.vhd delete mode 100644 trb_net16_base_api.vhd delete mode 100644 trb_net16_base_hub.vhd delete mode 100644 trb_net16_base_hub_logic.vhd delete mode 100644 trb_net16_passive_api.vhd delete mode 100644 trb_net16_trigger_receiver_apimbuf_endpoint.vhd delete mode 100644 trb_net16_trigger_receiver_endpoint.vhd diff --git a/trb_net16_active_api.vhd b/trb_net16_active_api.vhd deleted file mode 100644 index 744ad19..0000000 --- a/trb_net16_active_api.vhd +++ /dev/null @@ -1,221 +0,0 @@ --- connection between the TRBNET and any application --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_active_api is - - generic ( - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path - -- if set to 0, no buffer is used - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_INIT_READ_IN : in std_logic; - - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT : out std_logic; - - - INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN : in std_logic; - - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_active_api_arch of trb_net16_active_api is - - component trb_net16_base_api is - generic ( - API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - - - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - -begin - - BASE_API: trb_net16_base_api - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH - ) - port map ( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT, - INT_MASTER_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, - INT_MASTER_READ_IN => INT_INIT_READ_IN, - - INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_MASTER_DATA_IN => INT_INIT_DATA_IN, - INT_MASTER_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, - INT_MASTER_READ_OUT => INT_INIT_READ_OUT, - - INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - - INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT, - INT_SLAVE_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, - INT_SLAVE_READ_IN => INT_REPLY_READ_IN, - - INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN, - INT_SLAVE_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, - INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT, - -- Status and control port - STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, - STAT_FIFO_TO_APL => STAT_FIFO_TO_APL - -- not needed now, but later - ); - -end architecture; diff --git a/trb_net16_apimbuf.vhd b/trb_net16_apimbuf.vhd deleted file mode 100644 index 195035e..0000000 --- a/trb_net16_apimbuf.vhd +++ /dev/null @@ -1,646 +0,0 @@ --- an active api together with an iobuf - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net16_apimbuf is - - generic ( - API_TYPE : integer range 0 to 1 := 1; - INIT_DEPTH : integer range 0 to 6 := 0; - REPLY_DEPTH : integer range 0 to 6 := 1; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 1; - FIFO_TO_APL_DEPTH : integer range 0 to 6 := 1; - SBUF_VERSION : integer range 0 to 1 := 0; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0; - DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0; - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_READ_IN: in std_logic; -- Media is reading - - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out std_logic_vector(31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - MPLEX_CTRL: in std_logic_vector (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_apimbuf_arch of trb_net16_apimbuf is - -component trb_net16_iobuf is - - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3); -- or the replyibuf - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); -end component; - -component trb_net16_base_api is - generic ( - API_TYPE : integer := 1; - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - SBUF_VERSION : integer range 0 to 1 := 0 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_MASTER_DATAREADY_OUT: out std_logic; - INT_MASTER_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN: in std_logic; - - INT_MASTER_DATAREADY_IN: in std_logic; - INT_MASTER_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT: out std_logic; - - - INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the SLAVE path) - INT_SLAVE_DATAREADY_OUT: out std_logic; - INT_SLAVE_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN: in std_logic; - - INT_SLAVE_DATAREADY_IN: in std_logic; - INT_SLAVE_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT: out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end component; - - - -component trb_net16_io_multiplexer is - - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - -- highest bits are mult. - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; - - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_READ_IN: in std_logic; - - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); -end component; - - component trb_net16_term_buf is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic - ); - end component; - -signal apl_to_buf_INIT_DATAREADY: std_logic; -signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0); -signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0); -signal apl_to_buf_INIT_READ : std_logic; - -signal buf_to_apl_INIT_DATAREADY: std_logic; -signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0); -signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0); -signal buf_to_apl_INIT_READ : std_logic; - -signal apl_to_buf_REPLY_DATAREADY: std_logic; -signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0); -signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); -signal apl_to_buf_REPLY_READ : std_logic; - -signal buf_to_apl_REPLY_DATAREADY: std_logic; -signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0); -signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); -signal buf_to_apl_REPLY_READ : std_logic; - --- for the connection to the multiplexer -signal MED_INIT_DATAREADY_OUT : std_logic; -signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0); -signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0); -signal MED_INIT_READ_IN : std_logic; - -signal MED_INIT_DATAREADY_IN : std_logic; -signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0); -signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0); -signal MED_INIT_READ_OUT : std_logic; - -signal MED_REPLY_DATAREADY_OUT : std_logic; -signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0); -signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0); -signal MED_REPLY_READ_IN : std_logic; - -signal MED_REPLY_DATAREADY_IN : std_logic; -signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0); -signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); -signal MED_REPLY_READ_OUT : std_logic; - -signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -signal buf_STAT_INIT_BUFFER : std_logic_vector (31 downto 0); -signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 downto 0); - -begin - - --Connections for data channel - genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate - gendat: if i = DAT_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; - MED_INIT_READ_IN <= m_READ_IN(i*2); - MED_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; - end generate; - genelse: if i /= DAT_CHANNEL generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) - ); - end generate; - end generate; - - - - gen_actapi: if API_TYPE = 1 generate - DAT_ACTIVE_API: trb_net16_base_api - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0, - SBUF_VERSION => SBUF_VERSION - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_INIT_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_INIT_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ, - -- Status and control port - STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl - ); - end generate; - - gen_pasapi: if API_TYPE = 0 generate - DAT_PASSIVE_API: trb_net16_base_api - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0, - SBUF_VERSION => SBUF_VERSION - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_REPLY_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_INIT_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ, - -- Status and control port - STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl - ); - end generate; -api_stat_fifo_to_apl <= buf_api_stat_fifo_to_apl; -api_stat_fifo_to_int <= buf_api_stat_fifo_to_int; - -STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); -STAT_api_control_signals(3) <= APL_WRITE_IN; -STAT_api_control_signals(4) <= APL_SEND_IN; -STAT_api_control_signals(7 downto 5) <= (others => '0'); -STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0); -STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY; -STAT_api_control_signals(12) <= apl_to_buf_INIT_READ; -STAT_api_control_signals(28 downto 13) <= (others => '0'); - -STAT_api_control_signals(31) <= buf_to_apl_INIT_READ; ---STAT_api_control_signals(30) <= buf_to_apl_INIT_PACKET_NUM(0); ---STAT_api_control_signals(29) <= buf_to_apl_INIT_DATAREADY; -STAT_api_control_signals(30) <= buf_api_stat_fifo_to_apl(3); -STAT_api_control_signals(29) <= buf_api_stat_fifo_to_apl(14); - - -IOBUF: trb_net16_iobuf - - generic map (INIT_DEPTH => INIT_DEPTH, - REPLY_DEPTH => REPLY_DEPTH) - - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_INIT_READ_IN, - - MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - - MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_REPLY_READ_IN, - - MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_INIT_READ, - - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_INIT_READ, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, - - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, - - -- Status and control port - STAT_GEN => STAT_GEN, - STAT_LOCKED => STAT_LOCKED, - STAT_INIT_BUFFER => buf_STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, - CTRL_GEN => CTRL_GEN, - CTRL_LOCKED => CTRL_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER - ); - -STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER; - - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT => m_DATA_IN, - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, - INT_READ_IN => m_READ_OUT, - INT_DATAREADY_IN => m_DATAREADY_OUT, - INT_DATA_IN => m_DATA_OUT, - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, - INT_READ_OUT => m_READ_IN, - CTRL => MPLEX_CTRL - ); - -end architecture; - diff --git a/trb_net16_base_api.vhd b/trb_net16_base_api.vhd deleted file mode 100644 index 5c65226..0000000 --- a/trb_net16_base_api.vhd +++ /dev/null @@ -1,813 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_base_api is - - generic ( - API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 1; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering master path - -- if set to 0, no buffer is used - SBUF_VERSION : integer range 0 to 1 := 0 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - - - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); -end entity; - - - -architecture trb_net16_base_api_arch of trb_net16_base_api is - - component trb_net16_dummy_fifo is - generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - end component; - - component trb_net16_fifo is - generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2; - DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) 64Bit packets - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - end component; - - component trb_net16_sbuf is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - - component trb_net16_term is - generic ( - FIFO_TERM_BUFFER_DEPTH : integer := FIFO_TERM_BUFFER_DEPTH; - -- fifo for auto-answering of the master path, if set to 0 no buffer is used at all - SECURE_MODE : integer range 0 to 1 := 0 - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) - -- Status and control port - ); - end component; - - -- signals for the APL to INT fifo: - signal fifo_to_int_data_in : std_logic_vector(15 downto 0); - signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); - signal fifo_to_int_write : std_logic; - signal fifo_to_int_data_out : std_logic_vector(15 downto 0); - signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0); - signal fifo_to_int_read : std_logic; - signal fifo_to_int_full : std_logic; - signal fifo_to_int_empty : std_logic; - - -- signals for the INT to APL: - signal fifo_to_apl_data_in : std_logic_vector(15 downto 0); - signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0); - signal fifo_to_apl_write : std_logic; - signal fifo_to_apl_data_out : std_logic_vector(15 downto 0); - signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); - signal fifo_to_apl_read : std_logic; - signal fifo_to_apl_full : std_logic; - signal fifo_to_apl_empty : std_logic; - signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); - - - -- signals for the test buffer - signal fifo_term_buffer_data_in : std_logic_vector(15 downto 0); - signal fifo_term_buffer_packet_num_in : std_logic_vector(1 downto 0); - signal fifo_term_buffer_write : std_logic; - signal fifo_term_buffer_data_out : std_logic_vector(15 downto 0); - signal fifo_term_buffer_packet_num_out : std_logic_vector(1 downto 0); - signal fifo_term_buffer_read : std_logic; - signal fifo_term_buffer_full : std_logic; - signal fifo_term_buffer_empty : std_logic; - - signal state_bits : std_logic_vector(2 downto 0); - type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); - type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); - signal current_state, next_state : API_STATE; - signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; - signal slave_running, next_slave_running : std_logic; - - signal next_INT_MASTER_DATA_OUT: std_logic_vector(15 downto 0); - signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(1 downto 0); - signal next_INT_MASTER_DATAREADY_OUT: std_logic; - signal sbuf_free, sbuf_next_READ: std_logic; - signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic; - signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; - signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(15 downto 0); - signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(1 downto 0); - signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); - - type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); - signal out_select, last_out_select: OUTPUT_SELECT; - signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); - signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); - signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); - signal next_registered_trailer_F1, next_registered_trailer_F2, next_registered_trailer_F3 : std_logic_vector(15 downto 0); - signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0); - signal current_combined_header, current_registered_trailer, current_combined_trailer, current_data : std_logic_vector(15 downto 0); - - signal update_registered_trailer: std_logic; - signal master_counter : std_logic_vector(1 downto 0); - signal out_enable : std_logic_vector(1 downto 0); -begin ---------------------------------------- --- termination for active api ---------------------------------------- - genterm: if API_TYPE = 1 generate - TrbNetTerm: trb_net16_term - generic map( - SECURE_MODE => 0 - ) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => INT_SLAVE_DATAREADY_OUT, - INT_DATA_OUT => INT_SLAVE_DATA_OUT, - INT_PACKET_NUM_OUT=> INT_SLAVE_PACKET_NUM_OUT, - INT_READ_IN => INT_SLAVE_READ_IN, - INT_DATAREADY_IN => INT_MASTER_DATAREADY_IN, - INT_DATA_IN => INT_MASTER_DATA_IN, - INT_PACKET_NUM_IN => INT_MASTER_PACKET_NUM_IN, - INT_READ_OUT => INT_MASTER_READ_OUT, - APL_RELEASE_TRM => '1', - APL_ERROR_PATTERN_IN => (others => '0') - ); - end generate; - gennotterm: if API_TYPE = 0 generate - INT_MASTER_READ_OUT <= '1'; - INT_SLAVE_DATAREADY_OUT <= '0'; - end generate; - ---------------------------------------- --- fifo to internal ---------------------------------------- - - CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate - FIFO_TO_INT: trb_net16_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, - DEPTH => FIFO_TO_INT_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_int_data_in, - PACKET_NUM_IN => fifo_to_int_packet_num_in, - WRITE_ENABLE_IN => fifo_to_int_write, - DATA_OUT => fifo_to_int_data_out, - PACKET_NUM_OUT => fifo_to_int_packet_num_out, - READ_ENABLE_IN => fifo_to_int_read, - FULL_OUT => fifo_to_int_full, - EMPTY_OUT => fifo_to_int_empty - ); - end generate; - - CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate - FIFO_TO_INT: trb_net16_dummy_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_int_data_in, - PACKET_NUM_IN => fifo_to_int_packet_num_in, - WRITE_ENABLE_IN => fifo_to_int_write, - DATA_OUT => fifo_to_int_data_out, - PACKET_NUM_OUT => fifo_to_int_packet_num_out, - READ_ENABLE_IN => fifo_to_int_read, - FULL_OUT => fifo_to_int_full, - EMPTY_OUT => fifo_to_int_empty - ); - end generate CHECK_BUFFER4; - - STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); - STAT_FIFO_TO_INT(3) <= fifo_to_int_write; - STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0); - STAT_FIFO_TO_INT(11) <= fifo_to_int_read; - STAT_FIFO_TO_INT(14) <= fifo_to_int_full; - STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; - STAT_FIFO_TO_INT(7 downto 4) <= (others => '0'); - STAT_FIFO_TO_INT(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_INT(28 downto 16) <= (others => '0'); - STAT_FIFO_TO_INT(31 downto 29) <= state_bits; ---------------------------------------- --- fifo to apl ---------------------------------------- - - CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate - FIFO_TO_APL: trb_net16_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, - DEPTH => FIFO_TO_APL_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_apl_data_in, - PACKET_NUM_IN => fifo_to_apl_packet_num_in, - WRITE_ENABLE_IN => fifo_to_apl_write, - DATA_OUT => fifo_to_apl_data_out, - PACKET_NUM_OUT => fifo_to_apl_packet_num_out, - READ_ENABLE_IN => fifo_to_apl_read, - FULL_OUT => fifo_to_apl_full, - EMPTY_OUT => fifo_to_apl_empty - ); - end generate CHECK_BUFFER5; - - CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate - FIFO_TO_APL: trb_net16_dummy_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_apl_data_in, - PACKET_NUM_IN => fifo_to_apl_packet_num_in, - WRITE_ENABLE_IN => fifo_to_apl_write, - DATA_OUT => fifo_to_apl_data_out, - PACKET_NUM_OUT => fifo_to_apl_packet_num_out, - READ_ENABLE_IN => fifo_to_apl_read, - FULL_OUT => fifo_to_apl_full, - EMPTY_OUT => fifo_to_apl_empty - ); - end generate CHECK_BUFFER6; - - STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); - STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; - STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); - STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; - STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; - STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; - STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); - --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); - STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; - STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; - STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; - ---------------------------------------- --- a sbuf on the active channel ---------------------------------------- - - ACTIVE_SBUF: trb_net16_sbuf - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, - VERSION => SBUF_VERSION) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT, - COMB_next_READ_OUT => sbuf_next_READ, - COMB_READ_IN => '1', - COMB_DATA_IN => next_INT_MASTER_DATA_OUT, - COMB_PACKET_NUM_IN => next_INT_MASTER_PACKET_NUM_OUT, - SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT, - SYN_DATA_OUT => INT_MASTER_DATA_OUT, - SYN_PACKET_NUM_OUT => INT_MASTER_PACKET_NUM_OUT, - SYN_READ_IN => INT_MASTER_READ_IN - ); - - sbuf_free <= sbuf_next_READ; - - - next_APL_DATA_OUT <= fifo_to_apl_data_out; - next_APL_PACKET_NUM_OUT <= fifo_to_apl_packet_num_out; - next_APL_TYP_OUT <= current_fifo_to_apl_packet_type; - - - --this holds the current packet type from fifo_to_apl - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL; - elsif fifo_to_apl_packet_num_out = "00" then - saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0); - end if; - end if; - end process; - --create comb. real packet type - current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_packet_num_out = "00") - else saved_fifo_to_apl_packet_type; - ---------------------------------------- --- select data for int direction ---------------------------------------- - - - process(current_combined_header, current_registered_trailer, current_combined_trailer, current_data, out_select) - begin - case out_select is - when HDR => next_INT_MASTER_DATA_OUT <= current_combined_header; - when TRM => next_INT_MASTER_DATA_OUT <= current_registered_trailer; - when TRM_COMB => next_INT_MASTER_DATA_OUT <= current_combined_trailer; - when others => next_INT_MASTER_DATA_OUT <= current_data; - end case; - end process; - - - - process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1, - combined_trailer_F1, combined_header_F2, registered_trailer_F2, combined_trailer_F2, - combined_header_F3, registered_trailer_F3, combined_trailer_F3) - begin - case master_counter is - when "01" => - current_combined_header <= combined_header_F1; - current_registered_trailer <= registered_trailer_F1; - current_combined_trailer <= combined_trailer_F1; - current_data <= fifo_to_int_data_out; - when "10" => - current_combined_header <= combined_header_F2; - current_registered_trailer <= registered_trailer_F2; - current_combined_trailer <= combined_trailer_F2; - current_data <= fifo_to_int_data_out; - when "11" => - current_combined_header <= combined_header_F3; - current_registered_trailer <= registered_trailer_F3; - current_combined_trailer <= combined_trailer_F3; - current_data <= fifo_to_int_data_out; - when others => - current_combined_header <= "0000000000000" & TYPE_HDR; - current_registered_trailer <= "0000000000000" & TYPE_TRM; - current_combined_trailer <= "0000000000000" & TYPE_TRM; - current_data <= "0000000000000" & TYPE_DAT; - end case; - end process; - - next_INT_MASTER_PACKET_NUM_OUT <= master_counter; - - MASTER_TRANSFER_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - master_counter <= (others => '0'); - elsif next_INT_MASTER_DATAREADY_OUT = '1' then - master_counter <= master_counter + 1; - end if; - end if; - end process; - - ---------------------------------------- ---the state machine ---------------------------------------- - - STATE_COMB: process(current_state, APL_SEND_IN, slave_running, sequence_counter, - APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty, - sbuf_free, master_counter, fifo_to_apl_full, - reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT, - INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN, - fifo_to_apl_packet_num_out, reg_APL_TYP_OUT, - reg_APL_PACKET_NUM_OUT, last_out_select) - begin - next_state <= MY_ERROR; - next_INT_MASTER_DATAREADY_OUT <= '0'; - out_select <= DAT; - update_registered_trailer <= '0'; - fifo_to_int_read <= '0'; - next_INT_SLAVE_READ_OUT <= '0'; - fifo_to_apl_write <= '0'; - next_APL_DATAREADY_OUT <= '0'; - fifo_to_apl_read <= '0'; - next_slave_running <= slave_running; - next_sequence_counter <= sequence_counter; - ------------------------------------------------------------------------------- - -- IDLE - ------------------------------------------------------------------------------- - if current_state = IDLE then - if APL_SEND_IN = '1' then - if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' - next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN - update_registered_trailer <= '1'; -- moved from SEND_SHORT - else -- normal transfer, prepare the header - next_state <= SEND_HEADER; - out_select <= HDR; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; -- next word will be a header - else - next_state <= IDLE; - end if; -- APL_SEND_IN - ------------------------------------------------------------------------------- - -- SEND_SHORT - ------------------------------------------------------------------------------- - elsif current_state = SEND_SHORT then - next_state <= SEND_SHORT; - out_select <= TRM; - if APL_SEND_IN = '0' then -- terminate the transfer - next_state <= SEND_TRAILER; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - ------------------------------------------------------------------------------- - -- SEND_HEADER - ------------------------------------------------------------------------------- - elsif current_state = SEND_HEADER then - out_select <= HDR; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - if master_counter = "00" then - next_state <= RUNNING; - next_INT_MASTER_DATAREADY_OUT <= '0'; - else - next_state <= SEND_HEADER; - end if; - ------------------------------------------------------------------------------- - -- RUNNING - ------------------------------------------------------------------------------- - elsif current_state = RUNNING then - if sbuf_free = '1' then - fifo_to_int_read <= '1'; - end if; - if APL_SEND_IN = '0' then -- terminate the transfer - update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' then -- immediate stop - next_INT_MASTER_DATAREADY_OUT <= '1'; - if master_counter = "11" then - next_state <= SEND_TRAILER; - out_select <= TRM_COMB; - end if; - else - next_state <= SHUTDOWN; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - end if; - else -- APL_SEND_IN: still running - next_state <= RUNNING; - if fifo_to_int_empty = '0' and sbuf_free = '1' then - -- data words have to be prepared - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; -- fifo_to_int_empty = '0' - end if; - ------------------------------------------------------------------------------- - -- SHUTDOWN: Empty the pipe - ------------------------------------------------------------------------------- - elsif current_state = SHUTDOWN then - next_state <= SHUTDOWN; - if sbuf_free = '1' then --- next_INT_MASTER_DATAREADY_OUT <= '1'; --- -- we are done --- --implicit: fill with padding words --- if master_counter = "00" and fifo_to_int_empty = '1' then --- next_state <= SEND_TRAILER; --- out_select <= TRM; - if fifo_to_int_empty = '0' then - -- data words have to be prepared - fifo_to_int_read <= '1'; - next_INT_MASTER_DATAREADY_OUT <= '1'; - else - -- we are done - --implicit: fill with padding words - if master_counter = "00" then - next_state <= SEND_TRAILER; - out_select <= TRM; - end if; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - end if; - ------------------------------------------------------------------------------- - -- SEND_TRAILER - ------------------------------------------------------------------------------- - elsif current_state = SEND_TRAILER then - out_select <= TRM; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - if master_counter = "00" then - next_state <= WAITING; - next_INT_MASTER_DATAREADY_OUT <= '0'; - if API_TYPE = 0 then --here is the end of the passive transfer - next_sequence_counter <= sequence_counter +1; - next_slave_running <= '0'; - end if; - else - next_state <= SEND_TRAILER; - end if; - ------------------------------------------------------------------------------- - -- WAITING => for the answer or a request - ------------------------------------------------------------------------------- - elsif current_state = WAITING then - next_state <= WAITING; - -- here we have to supply the receiver port - -- part 1: connection to network - if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then - next_INT_SLAVE_READ_OUT <= '1'; - end if; - if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then - fifo_to_apl_write <= '1'; -- use fifo as the pipe - end if; - - -- part 2: connection to apl --- if fifo_to_apl_empty = '0' then - if fifo_to_apl_empty = '0' --and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') - and fifo_to_apl_packet_num_out /= "00" then --is this really correct???? - next_APL_DATAREADY_OUT <= '1'; - end if; -- read/no read - - if (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') or fifo_to_apl_packet_num_out = "00" then - -- valid read - fifo_to_apl_read <= not fifo_to_apl_empty; - if API_TYPE = 0 then - if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then - next_slave_running <= '1'; - end if; - end if; - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') - then --fifo_to_apl_read = '1' - next_state <= IDLE; - if API_TYPE = 1 then - next_sequence_counter <= sequence_counter +1; - end if; - end if; - end if; - -- MISSING: SEQNR check - -- OPEN QUESTION: Address matching? makes sense for a reply transfer? - end if; - if master_counter = "00" or fifo_to_int_empty = '1' then - fifo_to_int_read <= '0'; - end if; - end process; - - CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - sequence_counter <= (others => '0'); - reg_INT_SLAVE_READ_OUT <= '0'; - last_out_select <= DAT; - if API_TYPE = 1 then - current_state <= IDLE; - else - current_state <= WAITING; - end if; - slave_running <= '0'; - elsif CLK_EN = '1' then - sequence_counter <= next_sequence_counter; - last_out_select <= out_select; - reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; - current_state <= next_state; - slave_running <= next_slave_running; - end if; - end if; - end process; - ---------------------------------------- --- ---------------------------------------- - - --get target address from active APL - gentarget1: if API_TYPE = 1 generate - combined_header_F2 <= APL_TARGET_ADDRESS_IN; - end generate; - --save target address for passive api - gentarget0: if API_TYPE = 0 generate - reg_hdr_f1: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - combined_header_F2 <= (others => '1'); - elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" then - combined_header_F2 <= fifo_to_apl_data_out; - end if; - end if; - end process; - end generate; - -- combine the next header - combined_header_F1 <= APL_MY_ADDRESS_IN; - combined_header_F3(15 downto 14) <= (others => '0'); -- LAY - combined_header_F3(13 downto 12) <= (others => '0'); -- VERS - combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR - combined_header_F3(3 downto 0) <= APL_DTYPE_IN; - combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); - combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 0); - combined_trailer_F3(15 downto 14) <= (others => '0'); -- res. - combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS - combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR - combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN; - - -- connect Transmitter port - fifo_to_int_data_in <= APL_DATA_IN; - fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN; - fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full) - when (current_state = IDLE or current_state = SEND_HEADER or current_state = RUNNING) - else '0'; - - APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing - - INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_DATAREADY_OUT <= '0'; - reg_APL_DATA_OUT <= (others => '0'); - reg_APL_PACKET_NUM_OUT <= (others => '0'); - reg_APL_TYP_OUT <= (others => '0'); - elsif CLK_EN = '1' then - reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; - reg_APL_DATA_OUT <= next_APL_DATA_OUT; - reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; - reg_APL_TYP_OUT <= next_APL_TYP_OUT; - end if; - end if; - end process; - - - -- connect receiver - fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; - fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN; - - APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; - APL_DATA_OUT <= reg_APL_DATA_OUT; - APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT; - APL_TYP_OUT <= reg_APL_TYP_OUT; - - genAPL_RUN_OUT_0: if API_TYPE = 0 generate - APL_RUN_OUT <= slave_running; - end generate; - genAPL_RUN_OUT_1: if API_TYPE = 1 generate - APL_RUN_OUT <= '0' when current_state = IDLE else '1'; - end generate; - - APL_SEQNR_OUT <= sequence_counter; - - REG3 : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - registered_trailer_F1 <= (others => '0'); - registered_trailer_F2 <= (others => '0'); - registered_trailer_F3 <= (others => '0'); - elsif update_registered_trailer = '1' then - registered_trailer_F1 <= combined_trailer_F1; - registered_trailer_F2 <= combined_trailer_F2; - registered_trailer_F3 <= combined_trailer_F3; - end if; - end if; - end process; - - process(current_state) - begin - case current_state is - when IDLE => state_bits <= "000"; - when SEND_HEADER => state_bits <= "001"; - when RUNNING => state_bits <= "010"; - when SHUTDOWN => state_bits <= "011"; - when SEND_SHORT => state_bits <= "100"; - when SEND_TRAILER => state_bits <= "101"; - when WAITING => state_bits <= "110"; - when others => state_bits <= "111"; - end case; - end process; - -end architecture; \ No newline at end of file diff --git a/trb_net16_base_hub.vhd b/trb_net16_base_hub.vhd deleted file mode 100644 index 4f79576..0000000 --- a/trb_net16_base_hub.vhd +++ /dev/null @@ -1,450 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_base_hub is - generic{ - --media interfaces - MII_NUMBER : integer range 2 to 16 := 2; - MII_INIT_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; - MII_REPLY_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; - -- settings for apis - API_NUMBER : integer range 0 to 16 := 1; - API_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"3"; - --channel, each api is connected to - API_TYPE : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_INIT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_REPLY_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_FIFO_TO_INT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - API_FIFO_TO_APL_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; - --trigger reading interfaces - TRG_NUMBER : integer range 0 to 16 := 2; - TRG_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"10"; - --general settings - MUX_SECURE_MODE : integer range 0 to 1 := 0; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_CTRL_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3; - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - } - port { - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - --Media interfacces - --each port is one bit bigger than actually necessary to avoid error messages - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media - MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3 downto 0); - --API: interfaces - APL_DATA_IN : in std_logic_vector (APL_NUMBER*DATA_WIDTH downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0); - APL_WRITE_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_FIFO_FULL_OUT : out std_logic_vector (APL_NUMBER downto 0); - APL_SHORT_TRANSFER_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_DTYPE_IN : in std_logic_vector (APL_NUMBER*4 downto 0); - APL_ERROR_PATTERN_IN : in std_logic_vector (APL_NUMBER*32 downto 0); - APL_SEND_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_TARGET_ADDRESS_IN : in std_logic_vector (APL_NUMBER*16 downto 0); - APL_DATA_OUT : out std_logic_vector (APL_NUMBER*16 downto 0); - APL_PACKET_NUM_OUT: out std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0); - APL_TYP_OUT : out std_logic_vector (APL_NUMBER*3 downto 0); - APL_DATAREADY_OUT : out std_logic_vector (APL_NUMBER downto 0); - APL_READ_IN : in std_logic_vector (APL_NUMBER downto 0); - APL_RUN_OUT : out std_logic_vector (APL_NUMBER downto 0); - APL_MY_ADDRESS_IN : in std_logic_vector (APL_NUMBRT*16 downto 0); - APL_SEQNR_OUT : out std_logic_vector (APL_NUMBER*8 downto 0); - --TRG interfaces - TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0); - TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0); - TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0); - TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0); - TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0); - TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0); - --Status ports (for debugging) - HUB_CHANNEL_STAT : out std_logic_vector (2**(MUX_WIDTH-1)*16 downto 0); - HUB_GEN_STAT : out std_logic_vector (31 downto 0); - MPLEX_CTRL : out std_logic_vector (MII_NUMBER*32-1 downto 0); - - } -end entity; - -architecture trb_net16_base_hub_arch of trb_net16_base_hub is - - signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - signal m_DATA_OUT : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_READ_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - signal m_DATA_IN : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0); - signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0); - - signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal hub_to_buf_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal hub_to_buf_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal buf_to_hub_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal buf_to_hub_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal hub_to_buf_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal hub_to_buf_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - signal buf_to_hub_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0); - signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0); - signal buf_to_hub_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); - - component trb_net16_base_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to 16 := 2; - INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - --general settings - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER downto 0); - REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER downto 0); - STAT_CHANNEL : out std_logic_vector (15 downto 0); - STAT_GEN : out std_logic_vector (31 downto 0); - CTRL_CHANNEL : in std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0) - ); -end component; - - - component trb_net16_io_multiplexer is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_iobuf is - generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - -- Internal direction port - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - INT_REPLY_HEADER_IN: in std_logic; - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - - component trb_net16_base_api is - generic ( - API_TYPE : integer := API_TYPE; - FIFO_TO_INT_DEPTH : integer := 1; - FIFO_TO_APL_DEPTH : integer := 1; - FIFO_TERM_BUFFER_DEPTH : integer := 0); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - -- Internal direction port - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - - -begin - ---generate multiplexers - gen_muxes: for i in 0 to MII_NUMBER-1 generate - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN(i*2+1 downto i*2), - MED_DATA_IN => MED_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_READ_OUT => MED_READ_OUT(i*2+1 downto i*2), - MED_DATAREADY_OUT => MED_DATAREADY_OUT(i*2+1 downto i*2), - MED_DATA_OUT => MED_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_READ_IN => MED_READ_IN(i*2+1 downto i*2), - INT_DATAREADY_OUT => m_DATAREADY_IN(i*2+1 downto i*2), - INT_DATA_OUT => m_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - INT_READ_IN => m_READ_OUT(i*2+1 downto i*2), - INT_DATAREADY_IN => m_DATAREADY_OUT(i*2+1 downto i*2), - INT_DATA_IN => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - INT_READ_OUT => m_READ_IN(i*2+1 downto i*2), - CTRL => MPLEX_CTRL((i+1)*32-1) downto i*32) - ); - end generate; - ---generate IOBufs for MII - gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate - IOBUF: trb_net16_iobuf - generic map ( - INIT_DEPTH => to_integer(MII_INIT_DEPTH((i+1)*4-1 downto i)), - REPLY_DEPTH => to_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i)) - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_ÌN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2), - MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - - MED_REPLY_DATAREADY_IN => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_IN => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2), - MED_REPLY_READ_OUT => m_READ_IN(i*2+1), - MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), - - INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), - - INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i), - INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), - - INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), - INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), - - -- Status and control port - STAT_GEN => IOBUF_STAT_GEN((i+1)*32 downto i*32), - STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32 downto i*32), - STAT_INIT_BUFFER => IOBUF_buf_STAT_INIT_BUFFER((i+1)*32 downto i*32), - STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32 downto i*32), - CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32 downto i*32), - CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32 downto i*32), - STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32 downto i*32), - STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32 downto i*32) - ); - end generate; - - gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate - HUBLOGIC : trb_net16_base_hub_logic - generic map{ - --media interfaces - POINT_NUMBER => MII_NUMBER, - INIT_DEPTH => MII_INIT_DEPTH((i+1)*4 downto i*4), - REPLY_DEPTH => MII_REPLY_DEPTH((i+1)*4 downto i*4), - --general settings - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INIT_DATAREADY_IN => buf_to_hub_INIT_DATAREADY(i), - INIT_DATA_IN => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INIT_PACKET_NUM_IN => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INIT_READ_OUT => buf_to_hub_INIT_READ(i), - INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INIT_DATA_OUT => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INIT_PACKET_NUM_OUT => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INIT_READ_IN => hub_to_buf_INIT_READ(i), - REPLY_HEADER_OUT => hub_to_buf_REPLY_HEADER_OUT(i), - REPLY_DATAREADY_IN => buf_to_hub_REPLY_DATAREADY(i), - REPLY_DATA_IN => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - REPLY_PACKET_NUM_IN => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - REPLY_READ_OUT => buf_to_hub_REPLY_READ(i), - REPLY_DATAREADY_OUT => hub_to_buf_REPLY_DATAREADY(i), - REPLY_DATA_OUT => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - REPLY_READ_IN => hub_to_buf_REPLY_READ(i), - STAT_INTERFACE => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32), - STAT_GEN => HUB_STAT_GEN((i+1)*32-1 downto i*32), - CTRL_INTERFACE => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32), - CTRL_GEN => HUB_CTRL_GEN((i+1)*32-1 downto i*32) - ) - end generate; - -end architecture; diff --git a/trb_net16_base_hub_logic.vhd b/trb_net16_base_hub_logic.vhd deleted file mode 100644 index 1120fdb..0000000 --- a/trb_net16_base_hub_logic.vhd +++ /dev/null @@ -1,107 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_base_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to 16 := 2; - INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - --general settings - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - --Internal interfaccs to IOBufs - INIT_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - INIT_READ_OUT : out std_logic_vector (PONUMBER downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - INIT_READ_IN : in std_logic_vector (PONUMBER downto 0); - REPLY_HEADER_OUT : out std_logic_vector (PONUMBER downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - REPLY_READ_OUT : out std_logic_vector (PONUMBER downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0); - REPLY_READ_IN : in std_logic_vector (PONUMBER downto 0); - --Status ports (for debugging) - STAT_CHANNEL : out std_logic_vector (15 downto 0); - STAT_GEN : out std_logic_vector (31 downto 0); - CTRL_CHANNEL : in std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0) - ); -end entity; - -architecture trb_net16_base_hub_logic_arch of trb_net16_base_hub_logic is -begin ---Datapool for Init-Channel - INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0); - INIT_POOL_READ <= - and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_pool_has_read(POINT_NUMBER-1 downto 0)); - - gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate - process(INIT_DATA_IN) - variable VAR_INIT_POOL_DATA : std_logic; - begin - VAR_INIT_POOL_DATA := 0; - gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop - VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i); - end loop; - INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA; - end process; - end generate; - ---Data for obuf output - gen_init_dataready_out: for i in 0 to POINT_NUMBER-1 generate - INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_pool_has_read(i); - end generate; - - gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate - INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA; - end generate; - - gen_init_read_in - - --DATAREADY for each OBUF is dataready from all ibufs and not already have been reading this word - -- gen_init_datapool_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate - -- gen_init_datapool_m: for MEDIA in 0 to MII_NUMBER-1 generate - -- hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) <= - -- or_all(buf_to_hub_DATAREADY((CHANNEL+1)*MII_NUMBER-1 downto CHANNEL*MII_NUMBER) - -- and not buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA); - -- hub_to_buf_INIT_DATA((CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH+1)-1 downto CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH)) <= - -- or_all( - -- end generate; - -- end generate; - - -- gen_init_has_read_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate - -- gen_init_has_read_m: for MEDIA in 0 to MII_NUMBER-1 generate - -- process(CLK) - -- begin - -- if rising_edge(CLK) then - -- if RESET = '1' or buf_to_hub_INIT_CHANNEL_READ(CHANNEL) = '1' then - -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '0'; - -- else - -- if hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) = '1' - -- and hub_to_buf_INIT_READ(CHANNEL*MII_NUMBER+MEDIA) = '1' then - -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '1'; - -- end if; - -- end if; - -- end if; - -- end process; - -- end generate; - -- end generate; -end architecture; \ No newline at end of file diff --git a/trb_net16_passive_api.vhd b/trb_net16_passive_api.vhd deleted file mode 100644 index 31543a8..0000000 --- a/trb_net16_passive_api.vhd +++ /dev/null @@ -1,221 +0,0 @@ --- connection between the TRBNET and any application --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_passive_api is - - generic ( - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path - -- if set to 0, no buffer is used - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_INIT_READ_IN : in std_logic; - - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT : out std_logic; - - - INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN : in std_logic; - - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_passive_api_arch of trb_net16_passive_api is - - component trb_net16_base_api is - generic ( - API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - - - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - -begin - - BASE_API: trb_net16_base_api - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH - ) - port map ( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT, - INT_MASTER_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, - INT_MASTER_READ_IN => INT_REPLY_READ_IN, - - INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_MASTER_DATA_IN => INT_REPLY_DATA_IN, - INT_MASTER_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, - INT_MASTER_READ_OUT => INT_REPLY_READ_OUT, - - INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - - INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT, - INT_SLAVE_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, - INT_SLAVE_READ_IN => INT_INIT_READ_IN, - - INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_SLAVE_DATA_IN => INT_INIT_DATA_IN, - INT_SLAVE_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, - INT_SLAVE_READ_OUT => INT_INIT_READ_OUT, - -- Status and control port - STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, - STAT_FIFO_TO_APL => STAT_FIFO_TO_APL - -- not needed now, but later - ); - -end architecture; diff --git a/trb_net16_trigger_receiver_apimbuf_endpoint.vhd b/trb_net16_trigger_receiver_apimbuf_endpoint.vhd deleted file mode 100644 index f5dda9c..0000000 --- a/trb_net16_trigger_receiver_apimbuf_endpoint.vhd +++ /dev/null @@ -1,797 +0,0 @@ --- this is an trigger receiver combined with a passive api - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net16_trigger_receiver_apimbuf_endpoint is - - generic ( - --api type for data channel - API_TYPE : integer range 0 to 1 := 0; - --Fifo for data channel - DAT_INIT_DEPTH : integer range 0 to 7 := 2; - DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here - DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1; - DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1; - --SBUF_DATA_VERSION : integer range 0 to 1 := 0; - --Fifo for TRG channel - TRG_INIT_DEPTH : integer range 0 to 7 := 0; - TRG_REPLY_DEPTH : integer range 0 to 7 := 0; - TRG_SECURE_MODE : integer range 0 to 1 := 0; - --SBUF_TRG_VERSION : integer range 0 to 1 := 0; - --Multiplexer - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0; - TRG_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0; - DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 2; - --General - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_READ_IN: in std_logic; -- Media is reading - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- APL Transceiver port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0); - - -- TRG Receiver port - TRG_GOT_TRIGGER_OUT : out std_logic; - TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - TRG_DTYPE_OUT : out std_logic_vector(3 downto 0); - TRG_SEQNR_OUT : out std_logic_vector(7 downto 0); - TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - TRG_RELEASE_IN : in std_logic; - - -- Status and control port => for debugging - STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_DAT_GEN: in std_logic_vector (31 downto 0); - CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0); - STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_TRG_GEN: in std_logic_vector (31 downto 0); - CTRL_TRG_LOCKED: in std_logic_vector (31 downto 0); - STAT_TRG_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_MPLEX: out std_logic_vector(31 downto 0); - MPLEX_CTRL: in std_logic_vector (31 downto 0); - DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_trigger_receiver_apimbuf_endpoint_arch of trb_net16_trigger_receiver_apimbuf_endpoint is - - component trb_net16_iobuf is - - generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_base_api is - generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 1; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net16_term is - generic ( - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - SECURE_MODE : integer range 0 to 1 := 0 - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr - -- Status and control port - ); - end component; - - component trb_net16_io_multiplexer is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_term_buf is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic - ); - end component; -signal apl_to_buf_DAT_INIT_DATAREADY: std_logic; -signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT_INIT_READ : std_logic; - -signal buf_to_apl_DAT_INIT_DATAREADY: std_logic; -signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT_INIT_READ : std_logic; - -signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic; -signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT_REPLY_READ : std_logic; - -signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic; -signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT_REPLY_READ : std_logic; - -signal apl_to_buf_TRG_INIT_DATAREADY: std_logic; -signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG_INIT_READ : std_logic; - -signal buf_to_apl_TRG_INIT_DATAREADY: std_logic; -signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG_INIT_READ : std_logic; - -signal apl_to_buf_TRG_REPLY_DATAREADY: std_logic; -signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG_REPLY_READ : std_logic; - -signal buf_to_apl_TRG_REPLY_DATAREADY: std_logic; -signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG_REPLY_READ : std_logic; - --- for the connection to the multiplexer -signal MED_DAT_INIT_DATAREADY_OUT : std_logic; -signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_INIT_READ_IN : std_logic; - -signal MED_DAT_INIT_DATAREADY_IN : std_logic; -signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_INIT_READ_OUT : std_logic; - -signal MED_DAT_REPLY_DATAREADY_OUT : std_logic; -signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_REPLY_READ_IN : std_logic; - -signal MED_DAT_REPLY_DATAREADY_IN : std_logic; -signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_REPLY_READ_OUT : std_logic; - -signal MED_TRG_INIT_DATAREADY_OUT : std_logic; -signal MED_TRG_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_TRG_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_TRG_INIT_READ_IN : std_logic; - -signal MED_TRG_INIT_DATAREADY_IN : std_logic; -signal MED_TRG_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_TRG_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_TRG_INIT_READ_OUT : std_logic; - -signal MED_TRG_REPLY_DATAREADY_OUT : std_logic; -signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_TRG_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_TRG_REPLY_READ_IN : std_logic; - -signal MED_TRG_REPLY_DATAREADY_IN : std_logic; -signal MED_TRG_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_TRG_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_TRG_REPLY_READ_OUT : std_logic; - -signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -begin - - --Connections for data and trigger channel - genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate - gendat: if i = DAT_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT; - MED_DAT_INIT_READ_IN <= m_READ_IN(i*2); - MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT; - end generate; - gentrg: if i = TRG_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_TRG_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_TRG_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG_REPLY_PACKET_NUM_OUT; - MED_TRG_INIT_READ_IN <= m_READ_IN(i*2); - MED_TRG_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_TRG_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_TRG_REPLY_READ_OUT; - end generate; - genelse: if i /= DAT_CHANNEL and i /= TRG_CHANNEL generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) - ); - end generate; - end generate; - - gen_actapi: if API_TYPE = 1 generate - DAT_ACTIVE_API: trb_net16_base_api - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl - ); - end generate; - - gen_pasapi: if API_TYPE = 0 generate - DAT_PASSIVE_API: trb_net16_base_api - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl - ); - end generate; - -STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); -STAT_DAT_api_control_signals(3) <= APL_WRITE_IN; -STAT_DAT_api_control_signals(4) <= APL_SEND_IN; -STAT_DAT_api_control_signals(7 downto 5) <= (others => '0'); -STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0); -STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY; -STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ; -STAT_DAT_api_control_signals(31 downto 13) <= (others => '0'); - - - -DAT_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => DAT_INIT_DEPTH, - REPLY_DEPTH => DAT_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_DAT_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_DAT_GEN, - STAT_LOCKED => STAT_DAT_LOCKED, - STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER, - CTRL_GEN => CTRL_DAT_GEN, - CTRL_LOCKED => CTRL_DAT_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER - ); - - TRG_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => TRG_INIT_DEPTH, - REPLY_DEPTH => TRG_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_TRG_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_TRG_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_TRG_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_TRG_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_TRG_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_TRG_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_TRG_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_TRG_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_TRG_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_TRG_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_TRG_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_TRG_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_TRG_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_TRG_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_TRG_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_TRG_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_TRG_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_TRG_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_TRG_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_TRG_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_TRG_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_TRG_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_TRG_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_TRG_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_TRG_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_TRG_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_TRG_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_TRG_GEN, - STAT_LOCKED => STAT_TRG_LOCKED, - STAT_INIT_BUFFER => STAT_TRG_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_TRG_REPLY_BUFFER, - CTRL_GEN => CTRL_TRG_GEN, - CTRL_LOCKED => CTRL_TRG_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_TRG_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_TRG_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, - INT_READ_IN =>m_READ_OUT, - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, - INT_READ_OUT =>m_READ_IN, - CTRL => MPLEX_CTRL - ); - - TRG_INIT : trb_net16_term - generic map ( - FIFO_TERM_BUFFER_DEPTH => 0, - SECURE_MODE => TRG_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => apl_to_buf_TRG_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_TRG_REPLY_DATA, - INT_PACKET_NUM_OUT => apl_to_buf_TRG_REPLY_PACKET_NUM, - INT_READ_IN => apl_to_buf_TRG_REPLY_READ, - INT_DATAREADY_IN => buf_to_apl_TRG_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_TRG_INIT_DATA, - INT_PACKET_NUM_IN => buf_to_apl_TRG_INIT_PACKET_NUM, - INT_READ_OUT => buf_to_apl_TRG_INIT_READ, - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => TRG_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => TRG_SEQNR_OUT, - APL_GOT_TRM => TRG_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => TRG_RELEASE_IN, - APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN - -- Status and control port - ); - - - -apl_to_buf_TRG_INIT_DATAREADY <= '0'; -apl_to_buf_TRG_INIT_DATA <= (others => '0'); -apl_to_buf_TRG_INIT_PACKET_NUM <= (others => '0'); -buf_to_apl_TRG_REPLY_READ <= '1'; -end architecture; diff --git a/trb_net16_trigger_receiver_endpoint.vhd b/trb_net16_trigger_receiver_endpoint.vhd deleted file mode 100644 index f8854d9..0000000 --- a/trb_net16_trigger_receiver_endpoint.vhd +++ /dev/null @@ -1,468 +0,0 @@ --- a trigger receiver - as simple as possible - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net16_trigger_receiver_endpoint is - - generic ( - TRG_INIT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - TRG_REPLY_DEPTH : integer := 0; -- or the replyibuf - MUX_WIDTH : integer := 3; - MUX_SECURE_MODE : integer := 0; - TRG_CHANNEL : integer := 0; - DATA_WIDTH : integer := 16; --not to be changed - NUM_WIDTH : integer := 2; --not to be changed - TRG_SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next - -- trigger comes in. if 1 these can be valid on falling edge of hold_trm only - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; -- Media is reading - - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - TRG_GOT_TRIGGER_OUT : out std_logic; - TRG_DTYPE_OUT : out std_logic_vector(3 downto 0); - TRG_SEQNR_OUT : out std_logic_vector(7 downto 0); - TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - TRG_RELEASE_IN : in std_logic; - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out std_logic_vector(31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - MPLEX_CTRL: in std_logic_vector (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_trigger_receiver_endpoint_arch of trb_net16_trigger_receiver_endpoint is - - component trb_net16_iobuf is - generic (INIT_DEPTH : integer := TRG_INIT_DEPTH; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := TRG_REPLY_DEPTH); -- or the replyibuf - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - -- Internal direction port - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - component trb_net16_io_multiplexer is - generic ( - DATA_WIDTH : integer := DATA_WIDTH; - NUM_WIDTH : integer := NUM_WIDTH; - MUX_WIDTH : integer range 1 to 5 := MUX_WIDTH; - MUX_SECURE_MODE : integer range 0 to 1 := MUX_SECURE_MODE --use sbufs or not? - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - -- highest bits are mult. - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); - end component; - component trb_net16_term is - generic ( - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr - -- Status and control port - ); - end component; - component trb_net16_term_buf is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic - ); - end component; - - signal apl_to_buf_INIT_DATAREADY: std_logic; - signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0); - signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0); - signal apl_to_buf_INIT_READ : std_logic; - - signal buf_to_apl_INIT_DATAREADY: std_logic; - signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0); - signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0); - signal buf_to_apl_INIT_READ : std_logic; - - signal apl_to_buf_REPLY_DATAREADY: std_logic; - signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0); - signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); - signal apl_to_buf_REPLY_READ : std_logic; - - signal buf_to_apl_REPLY_DATAREADY: std_logic; - signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0); - signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); - signal buf_to_apl_REPLY_READ : std_logic; - - -- for the connection to the multiplexer - signal MED_INIT_DATAREADY_OUT : std_logic; - signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0); - signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0); - signal MED_INIT_READ_IN : std_logic; - - signal MED_INIT_DATAREADY_IN : std_logic; - signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0); - signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0); - signal MED_INIT_READ_OUT : std_logic; - - signal MED_REPLY_DATAREADY_OUT : std_logic; - signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0); - signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0); - signal MED_REPLY_READ_IN : std_logic; - - signal MED_REPLY_DATAREADY_IN : std_logic; - signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0); - signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); - signal MED_REPLY_READ_OUT : std_logic; - -signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*(2**MUX_WIDTH)-1 downto 0); -signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*(2**MUX_WIDTH)-1 downto 0); -signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -begin -------------------------------------------------- ---Connection between multiplexer and iobuf -------------------------------------------------- - --Connections for data and trigger channel - genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate - gentrg: if i = TRG_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; - MED_INIT_READ_IN <= m_READ_IN(i*2); - MED_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; - end generate; - genelse: if i /= TRG_CHANNEL generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) - ); - end generate; - end generate; - -IOBUF: trb_net16_iobuf - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_GEN, - STAT_LOCKED => STAT_LOCKED, - STAT_INIT_BUFFER => STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, - CTRL_GEN => CTRL_GEN, - CTRL_LOCKED => CTRL_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET , - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, - INT_READ_IN =>m_READ_OUT, - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, - INT_READ_OUT =>m_READ_IN, - CTRL => MPLEX_CTRL - ); - - - TRM_INIT : trb_net16_term - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_REPLY_DATA, - INT_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, - INT_READ_IN => apl_to_buf_REPLY_READ, - INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_INIT_DATA, - INT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, - INT_READ_OUT => buf_to_apl_INIT_READ, - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => TRG_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => TRG_SEQNR_OUT, - APL_GOT_TRM => TRG_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => TRG_RELEASE_IN, - APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN - -- Status and control port - ); - - --- TRM_REPLY : trb_net16_term --- port map( --- -- Misc --- CLK => CLK, --- RESET => RESET, --- CLK_EN => CLK_EN, --- INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, --- INT_DATA_OUT => apl_to_buf_INIT_DATA, --- INT_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, --- INT_READ_IN => apl_to_buf_INIT_READ, --- INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, --- INT_DATA_IN => buf_to_apl_REPLY_DATA, --- INT_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, --- INT_READ_OUT => buf_to_apl_REPLY_READ, --- -- "mini" APL, just to see the triggers coming in --- APL_DTYPE_OUT => open, --- APL_ERROR_PATTERN_OUT => open, --- APL_SEQNR_OUT => open, --- APL_GOT_TRM => open, --- APL_RELEASE_TRM => '1', --- APL_ERROR_PATTERN_IN => (others => '0') --- -- Status and control port --- ); -apl_to_buf_INIT_DATAREADY <= '0'; -apl_to_buf_INIT_DATA <= (others => '0'); -apl_to_buf_INIT_PACKET_NUM <= (others => '0'); -buf_to_apl_REPLY_READ <= '1'; - - -end architecture; \ No newline at end of file -- 2.43.0