From 0f1c4c0c44cf90dad208fa9c120543a6ce198603 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 20 Jan 2022 14:35:15 +0100 Subject: [PATCH] DLM fixed --- backplanemaster/trb3sc_master.vhd | 96 +++++++++++++++--------------- cts/trb3sc_cts.vhd | 79 +++++++++++++++++------- hub/trb3sc_hub.vhd | 88 +++++++++++++-------------- tdctemplate/trb3sc_tdctemplate.vhd | 38 ++++++------ 4 files changed, 168 insertions(+), 133 deletions(-) diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index c30262e..f0d4ec8 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -93,10 +93,13 @@ architecture trb3sc_arch of trb3sc_master is attribute syn_keep : boolean; attribute syn_preserve : boolean; - signal clk_sys, clk_full, clk_full_osc : std_logic; - signal GSR_N : std_logic; - signal reset_i : std_logic; - signal do_reboot_i, reboot_from_gbe : std_logic; + signal clk_sys : std_logic; + signal clk_full : std_logic; + signal clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal do_reboot_i : std_logic; + signal reboot_from_gbe : std_logic; signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); @@ -111,19 +114,19 @@ architecture trb3sc_arch of trb3sc_master is bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - - signal sed_error_i : std_logic; + signal sed_error_i : std_logic; signal bus_master_active : std_logic; signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); - signal uart_tx, uart_rx : std_logic; + signal uart_tx : std_logic; + signal uart_rx : std_logic; - signal timer : TIMERS; - signal lcd_data : std_logic_vector(511 downto 0); + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); signal cts_number : std_logic_vector(15 downto 0); signal cts_code : std_logic_vector(7 downto 0); @@ -145,28 +148,27 @@ architecture trb3sc_arch of trb3sc_master is signal gsc_init_read, gsc_reply_read : std_logic; signal gsc_init_dataready, gsc_reply_dataready : std_logic; signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); - signal gsc_busy : std_logic; - signal my_address : std_logic_vector(15 downto 0); - signal mc_unique_id : std_logic_vector(63 downto 0); - signal reset_via_gbe : std_logic; + signal gsc_busy : std_logic; + signal my_address : std_logic_vector(15 downto 0); + signal mc_unique_id : std_logic_vector(63 downto 0); + signal reset_via_gbe : std_logic; - signal med_dataready_out : std_logic_vector (11-1 downto 0); - signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); - signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); - signal med_read_in : std_logic_vector (11-1 downto 0); - signal med_dataready_in : std_logic_vector (11-1 downto 0); - signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); - signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); - signal med_read_out : std_logic_vector (11-1 downto 0); - signal med_stat_op : std_logic_vector (11*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); - signal rdack, wrack : std_logic; --- signal reset_from_net_i : std_logic; + signal med_dataready_out : std_logic_vector (11-1 downto 0); + signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (11-1 downto 0); + signal med_dataready_in : std_logic_vector (11-1 downto 0); + signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (11-1 downto 0); + signal med_stat_op : std_logic_vector (11*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); + signal rdack, wrack : std_logic; signal external_reset_delayed : std_logic_vector(4 downto 0); - - signal trig_gen_out_i : std_logic_vector(3 downto 0); - signal monitor_inputs_i : std_logic_vector(18+4+32-1 downto 0); - signal trigger_inputs_i : std_logic_vector(18+4+32-1 downto 0); + + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal monitor_inputs_i : std_logic_vector(18+4+32-1 downto 0); + signal trigger_inputs_i : std_logic_vector(18+4+32-1 downto 0); signal backplane_rx_present, backplane_tx_present : std_logic_vector(8 downto 0); @@ -230,9 +232,9 @@ THE_CLOCK_RESET : entity work.clock_reset_handler tx_pll_lol_qd_c_i <= '0'; --------------------------------------------------------------------------- --- TrbNet Uplink +-- PCBSB: TrbNet Uplink --------------------------------------------------------------------------- -THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB +THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE), IS_WAP_ZERO => 1 @@ -260,9 +262,9 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB RX_DLM_WORD_OUT(23 downto 0) => open, RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", - RX_RST_OUT => send_rst_i, --open, - RX_RST_WORD_OUT => send_rst_word_i, --open, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, TX_RST_IN => '0', TX_RST_WORD_IN => x"00", -- sync operation @@ -304,9 +306,8 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB ); --------------------------------------------------------------------------- --- PCSC not used +-- PCSC: not used --------------------------------------------------------------------------- - tx_pll_lol_qd_c_i <= '0'; bussci3_tx.data <= (others => '0'); @@ -315,9 +316,8 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); --------------------------------------------------------------------------- --- PCSD not used +-- PCSD: not used --------------------------------------------------------------------------- - tx_pll_lol_qd_d_i <= '0'; bussci4_tx.data <= (others => '0'); @@ -345,9 +345,9 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --PCSB ); --------------------------------------------------------------------------- --- TrbNet Downlink +-- PCSA: TrbNet Downlink --------------------------------------------------------------------------- -THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS --PCSA +THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER), IS_WAP_ZERO => 1 @@ -370,11 +370,11 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS --PCSA RX_DLM_OUT => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + TX_DLM_WORD_IN => send_dlm_word_i, RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => send_rst_i, --'0', - TX_RST_WORD_IN => send_rst_word_i, --x"00", + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -422,7 +422,7 @@ GEN_READY_SIGNALS : for i in 0 to 4 generate end generate GEN_READY_SIGNALS; --------------------------------------------------------------------------- --- GbE +-- PCSD: GbE --------------------------------------------------------------------------- gen_noGBE : if INCLUDE_GBE = c_NO generate busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write; @@ -800,8 +800,8 @@ end generate; LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); -- LED_WHITE <= led; + LED_WHITE(1) <= not send_dlm_word_i(7); LED_WHITE(0) <= not send_rst_word_i(0); - LED_WHITE(1) <= not send_rst_word_i(1); LED_SFP_GREEN(1) <= not med2int(4).stat_op(9); --SFP Link Status LED_SFP_RED(1) <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)); --SFP RX/TX gen_led_nogbe : if INCLUDE_GBE = c_NO generate diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index e3293b6..96f0125 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -238,19 +238,22 @@ architecture trb3sc_arch of trb3sc_cts is signal debug_i : std_logic_vector(31 downto 0); signal master_clk_i : std_logic; - signal dlm_counter : unsigned(15 downto 0); + signal dlm_counter : unsigned(31 downto 0); signal dlm_send_x : std_logic; signal dlm_send_q : std_logic; signal dlm_send_qq : std_logic; signal test_reg : std_logic_vector(31 downto 0); signal pulse_detect : std_logic_vector(7 downto 0); - signal pulse_raising_egde_x : std_logic; - signal pulse_raising_edge : std_logic; signal send_rst_i : std_logic; signal send_rst_word_i : std_logic_vector(7 downto 0); signal send_dlm_word_i : std_logic_vector(7 downto 0); - + signal dlm_tag_ctr : unsigned(7 downto 0); + signal rst_ctrs_mc : std_logic; + signal rst_ctrs_sc : std_logic; + signal tx_rst_i : std_logic; + signal tx_rst_x : std_logic; + -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; -- attribute syn_keep of tx_dlm_i : signal is true; @@ -317,7 +320,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ); --------------------------------------------------------------------------- --- PCSA +-- PCSA: not used --------------------------------------------------------------------------- bussci1_tx.data <= (others => '0'); bussci1_tx.ack <= '0'; @@ -325,7 +328,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler bussci1_tx.unknown <= bussci1_rx.read or bussci1_rx.write when rising_edge(clk_sys); --------------------------------------------------------------------------- --- PCSB Downlink without backplane is SFP +-- PCSB: Downlink without backplane is SFP --------------------------------------------------------------------------- gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS @@ -354,15 +357,15 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate RX_DLM_OUT(3) => rx_dlm_i, RX_DLM_WORD_OUT => open, TX_DLM_IN => tx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"aa", + TX_DLM_WORD_IN => send_dlm_word_i, RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => pulse_raising_edge, --'0', - TX_RST_WORD_IN => send_rst_word_i, --x"00", + TX_RST_IN => tx_rst_i, + TX_RST_WORD_IN => send_rst_word_i, -- sync operation - WORD_SYNC_IN => '1', -- CTS MASTER + WORD_SYNC_IN => '1', WORD_SYNC_OUT => word_sync_i, - MASTER_CLK_IN => master_clk_i, -- CTS MASTER + MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, QUAD_RST_IN => '0', -- check GLOBAL_RESET_OUT => open, @@ -424,22 +427,23 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate enable_dlm_i <= test_reg(31); send_rst_i <= test_reg(30); destroy_link_i <= test_reg(24); - send_dlm_word_i <= test_reg(15 downto 8); + send_dlm_word_i <= std_logic_vector(dlm_tag_ctr); --test_reg(15 downto 8); send_rst_word_i <= test_reg(7 downto 0); tx_dlm_i <= dlm_send_qq; -- LED feedback - LED_WHITE(1) <= not send_rst_word_i(1); +-- LED_WHITE(1) <= not send_rst_word_i(1); + LED_WHITE(1) <= not std_logic(dlm_tag_ctr(7)); LED_WHITE(0) <= not send_rst_word_i(0); - -- DLM generator + -- DLM timing generator THE_DLM_SEND_PROC: process( master_clk_i ) begin if( rising_edge(master_clk_i) ) then dlm_send_q <= dlm_send_x; dlm_send_qq <= dlm_send_q; - if( (med2int(0).stat_op(3 downto 0) /= x"0") or (dlm_send_x = '1') ) then + if( (rst_ctrs_mc = '1') or (dlm_send_x = '1') ) then dlm_counter <= (others => '0'); elsif( word_sync_i = '1' ) then dlm_counter <= dlm_counter + 1; @@ -447,26 +451,57 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate end if; end process THE_DLM_SEND_PROC; - dlm_send_x <= '1' when (dlm_counter(13) = '1') and (word_sync_i = '1') and (enable_dlm_i = '1') else '0'; - + -- send pulse for DLM komma + -- needs to be shifted by two clock cycles to hit correct byte position + dlm_send_x <= '1' when (dlm_counter(17) = '1') and (word_sync_i = '1') and (enable_dlm_i = '1') else '0'; + + -- DLM "tag" for blinking LEDs :) + THE_DLM_TAG_CTR_PROC: process( master_clk_i ) + begin + if( rising_edge(master_clk_i) ) then + if( rst_ctrs_mc = '1' ) then + dlm_tag_ctr <= (others => '0'); + elsif( dlm_send_x = '1' ) then + dlm_tag_ctr <= dlm_tag_ctr + 1; + end if; + end if; + end process THE_DLM_TAG_CTR_PROC; + + -- reset counters if link is offline + rst_ctrs_sc <= '1' when ( med2int(0).stat_op(3 downto 0) /= x"0" ) else '0'; + + -- sync from CLK_SYS to MASTER_CLK + SYNC_SIGNALS: signal_sync + generic map( + WIDTH => 1, + DEPTH => 3 + ) + port map( + RESET => '0', + CLK0 => clk_sys, + CLK1 => master_clk_i, + D_IN(0) => rst_ctrs_sc, + D_OUT(0) => rst_ctrs_mc + ); + -- HDR_IO(10 downto 1) <= (others => '0'); -- TEST_LINE(15 downto 0) <= (others => '0'); - -- RST generator + -- RST send pulse generator THE_RST_SEND_PROC: process( master_clk_i ) begin if( rising_edge(master_clk_i) ) then pulse_detect(7 downto 0) <= pulse_detect(6 downto 0) & send_rst_i; - pulse_raising_edge <= pulse_raising_egde_x; + tx_rst_i <= tx_rst_x; end if; end process THE_RST_SEND_PROC; - pulse_raising_egde_x <= not pulse_detect(7) and pulse_detect(6); + tx_rst_x <= not pulse_detect(7) and pulse_detect(6); end generate; --------------------------------------------------------------------------- --- PCSC 4 downlinks +-- PCSC: not used --------------------------------------------------------------------------- bussci3_tx.data <= (others => '0'); bussci3_tx.ack <= '0'; @@ -474,7 +509,7 @@ end generate; bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); --------------------------------------------------------------------------- --- GbE (PCSD) +-- PCSD: GbE --------------------------------------------------------------------------- GBE : entity work.gbe_wrapper generic map( diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index 8ecfd01..d747323 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -211,7 +211,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler --------------------------------------------------------------------------- --- PCSA Uplink when backplane is used +-- PCSA: Uplink when backplane is used --------------------------------------------------------------------------- gen_PCSA : if USE_BACKPLANE = c_YES generate THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_RS @@ -244,11 +244,11 @@ gen_PCSA : if USE_BACKPLANE = c_YES generate RX_DLM_WORD_OUT(23 downto 16) => open, RX_DLM_WORD_OUT(31 downto 24) => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", - RX_RST_OUT => send_rst_i, --open, - RX_RST_WORD_OUT => send_rst_word_i, --open, - TX_RST_IN => send_rst_i, --'0', - TX_RST_WORD_IN => send_rst_word_i, --"00", + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, + TX_RST_IN => '0', + TX_RST_WORD_IN => x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => word_sync_i, @@ -289,7 +289,7 @@ gen_PCSA : if USE_BACKPLANE = c_YES generate end generate; --------------------------------------------------------------------------- --- PCSB Uplink without backplane and 3/4 downlinks +-- PCSB: TrbNet downlinks (backplane) --------------------------------------------------------------------------- gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS @@ -318,11 +318,11 @@ gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate RX_DLM_OUT(3) => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + TX_DLM_WORD_IN => send_dlm_word_i, RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => send_rst_i, --'0', - TX_RST_WORD_IN => send_rst_word_i, --x"00", + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -362,6 +362,9 @@ gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate ); end generate; +--------------------------------------------------------------------------- +-- PCSB: TrbNet one uplink and three downlinks (no backplane) +--------------------------------------------------------------------------- gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS generic map( @@ -393,11 +396,11 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate RX_DLM_WORD_OUT(23 downto 16) => open, RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", - RX_RST_OUT => send_rst_i, --open, - RX_RST_WORD_OUT => send_rst_word_i, --open, - TX_RST_IN => send_rst_i, --'0', - TX_RST_WORD_IN => send_rst_word_i, --x"00", + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => word_sync_i, @@ -459,7 +462,7 @@ end generate; -- sync_tx_quad_i <= '1'; --------------------------------------------------------------------------- --- PCSC 4 downlinks +-- PCSC: 4 downlinks --------------------------------------------------------------------------- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS generic map( @@ -484,11 +487,11 @@ end generate; RX_DLM_OUT => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + TX_DLM_WORD_IN => send_dlm_word_i, RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => send_rst_i, --'0', - TX_RST_WORD_IN => send_rst_word_i, --x"00", + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -528,7 +531,7 @@ end generate; ); --------------------------------------------------------------------------- --- PCSD GBE or 2 downlinks +-- PCSD: 2 downlinks (no GbE) --------------------------------------------------------------------------- gen_PCSD : if INCLUDE_GBE = c_NO generate THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS @@ -554,11 +557,11 @@ gen_PCSD : if INCLUDE_GBE = c_NO generate RX_DLM_OUT => open, RX_DLM_WORD_OUT => open, TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, --x"00", + TX_DLM_WORD_IN => send_dlm_word_i, RX_RST_OUT => open, RX_RST_WORD_OUT => open, - TX_RST_IN => send_rst_i, --'0', - TX_RST_WORD_IN => send_rst_word_i, --x"00", + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => open, @@ -608,6 +611,9 @@ gen_noGBE : if INCLUDE_GBE = c_NO generate busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write; end generate; +--------------------------------------------------------------------------- +-- PCSD: GbE +--------------------------------------------------------------------------- gen_GBE : if INCLUDE_GBE = c_YES generate GBE : entity work.gbe_wrapper generic map( @@ -638,15 +644,15 @@ gen_GBE : if INCLUDE_GBE = c_YES generate CLK_125_IN => CLK_SUPPL_PCLK, RESET => reset_i, GSR_N => GSR_N, - + -- TRIGGER_IN => '0', - + -- SD_PRSNT_N_IN(0) => SFP_MOD0(0), SD_PRSNT_N_IN(3 downto 1) => "111", SD_LOS_IN(0) => SFP_LOS(0), SD_LOS_IN(3 downto 1) => "111", SD_TXDIS_OUT(0) => SFP_TX_DIS(0), - + -- CTS_NUMBER_IN => cts_number, CTS_CODE_IN => cts_code, CTS_INFORMATION_IN => cts_information, @@ -658,17 +664,17 @@ gen_GBE : if INCLUDE_GBE = c_YES generate CTS_READ_IN => cts_read, CTS_LENGTH_OUT => cts_length, CTS_ERROR_PATTERN_OUT => cts_status_bits, - + -- FEE_DATA_IN => fee_data, FEE_DATAREADY_IN => fee_dataready, FEE_READ_OUT => fee_read, FEE_STATUS_BITS_IN => fee_status_bits, FEE_BUSY_IN => fee_busy, - + -- MC_UNIQUE_ID_IN => mc_unique_id, MY_TRBNET_ADDRESS_IN => my_address, ISSUE_REBOOT_OUT => reboot_from_gbe, - + -- GSC_CLK_IN => clk_sys, GSC_INIT_DATAREADY_OUT => gsc_init_dataready, GSC_INIT_DATA_OUT => gsc_init_data, @@ -679,14 +685,14 @@ gen_GBE : if INCLUDE_GBE = c_YES generate GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, GSC_REPLY_READ_OUT => gsc_reply_read, GSC_BUSY_IN => gsc_busy, - + -- BUS_IP_RX => busgbeip_rx, BUS_IP_TX => busgbeip_tx, BUS_REG_RX => busgbereg_rx, BUS_REG_TX => busgbereg_tx, - + -- MAKE_RESET_OUT => reset_via_gbe, - + -- DEBUG_OUT => open ); end generate; @@ -744,11 +750,10 @@ gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate MY_ADDRESS_OUT => my_address, UNIQUE_ID_OUT => mc_unique_id, EXTERNAL_SEND_RESET => external_reset_i, - + -- BUS_RX => ctrlbus_rx, BUS_TX => ctrlbus_tx, TIMER => timer, - --Gbe Sctrl Input GSC_INIT_DATAREADY_IN => gsc_init_dataready, GSC_INIT_DATA_IN => gsc_init_data, @@ -759,20 +764,18 @@ gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, GSC_REPLY_READ_IN => gsc_reply_read, GSC_BUSY_OUT => gsc_busy, - - --status and control ports + --status and control ports HUB_STAT_CHANNEL => open, HUB_STAT_GEN => open, MPLEX_CTRL => (others => '0'), MPLEX_STAT => open, STAT_REGS => open, STAT_CTRL_REGS => open, - --Fixed status and control ports STAT_DEBUG => open, CTRL_DEBUG => (others => '0') ); - external_reset_i <= reset_via_gbe; -- or med2int(INTERFACE_NUM-1).stat_op(15); + external_reset_i <= reset_via_gbe; end generate; @@ -982,15 +985,8 @@ end generate; LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11) or not med2int(9).stat_op(9)) when INCLUDE_GBE = c_NO else not (med2int(7).stat_op(10) or med2int(7).stat_op(11) or not med2int(7).stat_op(9)); + LED_WHITE(1) <= not send_dlm_word_i(7); LED_WHITE(0) <= not send_rst_word_i(0); - LED_WHITE(1) <= not send_rst_word_i(1); - --- LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = c_NO and USE_BACKPLANE = c_YES else --- not med2int(8).stat_op(9) when INCLUDE_GBE = c_YES and USE_BACKPLANE = c_YES else --- '1'; --- LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = c_NO and USE_BACKPLANE = c_YES else --- not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = c_YES and USE_BACKPLANE = c_YES else --- '1'; end architecture; diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 97a90bd..7e63290 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -155,12 +155,13 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal rx_dlm_i : std_logic; signal word_sync_i : std_logic; signal master_clk_i : std_logic; - + signal tx_reset_state : std_logic_vector(3 downto 0); signal global_reset_i : std_logic; - signal send_rst_i : std_logic; - signal send_rst_word_i : std_logic_vector(7 downto 0); + signal send_rst_i : std_logic; + signal send_rst_word_i : std_logic_vector(7 downto 0); + signal send_dlm_word_i : std_logic_vector(7 downto 0); begin @@ -234,22 +235,26 @@ end generate; RX_DLM_OUT(1) => open, RX_DLM_OUT(2) => open, RX_DLM_OUT(3) => rx_dlm_i, - RX_DLM_WORD_OUT => open, - TX_DLM_IN => rx_dlm_i, -- DLM komma ping - TX_DLM_WORD_IN => x"aa", - RX_RST_OUT => send_rst_i, --open, - RX_RST_WORD_OUT => send_rst_word_i, --open, +-- RX_DLM_WORD_OUT => open, + RX_DLM_WORD_OUT(7 downto 0) => open, + RX_DLM_WORD_OUT(15 downto 8) => open, + RX_DLM_WORD_OUT(23 downto 16) => open, + RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, TX_RST_IN => '0', TX_RST_WORD_IN => x"00", -- sync operation - WORD_SYNC_IN => word_sync_i, -- downlink synced to uplink + WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => word_sync_i, - MASTER_CLK_IN => master_clk_i, -- downlink uses uplink clock + MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => master_clk_i, QUAD_RST_IN => '0', GLOBAL_RESET_OUT => global_reset_i, - SLAVE_ACTIVE_OUT => open, -- BUG - SLAVE_ACTIVE_IN => '0', -- BUG + SLAVE_ACTIVE_OUT => open, + SLAVE_ACTIVE_IN => '0', TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, @@ -499,9 +504,6 @@ gen_ada : if PINOUT = 3 or PINOUT = 4 generate end generate; - - - --------------------------------------------------------------------------- -- FEE test signals and temperature sensors --------------------------------------------------------------------------- @@ -544,8 +546,10 @@ end generate; LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1); LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); - LED_WHITE(0) <= not send_rst_word_i(0); --time_counter(26) and time_counter(19); - LED_WHITE(1) <= not send_rst_word_i(1); --time_vector(20); + + LED_WHITE(1) <= not send_dlm_word_i(7); + LED_WHITE(0) <= not send_rst_word_i(0); + LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX -- 2.43.0