From 0f36432643b4391ecb22b642b1fb1bb2fcc0538f Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Tue, 6 May 2014 15:52:57 +0200 Subject: [PATCH] Working connections once again. There was an error in the lpf files designating the wrong quad. BUMMER! --- .gitignore | 12 +- code/ip/serdes_4_sync_hub_downstream.ipx | 14 +- code/ip/serdes_4_sync_hub_downstream.lpc | 18 +- code/ip/serdes_4_sync_hub_downstream.txt | 8 +- code/ip/serdes_sync_client_upstream.txt | 2 +- code/ip/serdes_sync_source_downstream.ipx | 14 +- code/ip/serdes_sync_source_downstream.lpc | 6 +- code/ip/serdes_sync_source_downstream.txt | 4 +- code/ip/serdes_sync_source_downstream.vhd | 3 +- code/ip/serdes_sync_upstream.ipx | 14 +- code/ip/serdes_sync_upstream.lpc | 36 +-- code/ip/serdes_sync_upstream.vhd | 27 +- code/med_ecp3_sfp_sync_down.vhd | 2 +- code/med_ecp3_sfp_sync_up.vhd | 68 ++--- code/trb3_periph_sodaclient.vhd | 57 +++-- code/trb3_periph_sodahub.vhd | 39 +-- soda_client.ldf | 22 +- soda_client.lpf | 4 +- soda_client_probe.rvl | 184 ++++---------- soda_hub_probe.rvl | 292 ++++++++++++++++++---- soda_source.ldf | 18 +- soda_source/soda_source_syn.prj | 164 ------------ soda_source_probe.rvl | 36 ++- source/serdes_sync_downstream.ipx | 11 - source/serdes_sync_downstream.lpc | 258 ------------------- source/serdes_sync_downstream.txt | 58 ----- source/tb/TB_soda_source.vhd | 162 ------------ trb3_soda_client.xcf | 8 +- trb3_soda_dual_client.xcf | 8 +- trb3_soda_hub.xcf | 8 +- trb3_soda_source.xcf | 8 +- 31 files changed, 516 insertions(+), 1049 deletions(-) delete mode 100644 soda_source/soda_source_syn.prj delete mode 100644 source/serdes_sync_downstream.ipx delete mode 100644 source/serdes_sync_downstream.lpc delete mode 100644 source/serdes_sync_downstream.txt delete mode 100644 source/tb/TB_soda_source.vhd diff --git a/.gitignore b/.gitignore index 4893bbb..962d0c5 100644 --- a/.gitignore +++ b/.gitignore @@ -14,14 +14,4 @@ version.vhd *.kate-swp *.html *.xml -source/serdes_4_sync_downstream.ipx -source/serdes_4_sync_downstream.lpc -source/serdes_sync_client_upstream.ipx -source/serdes_sync_upstream.ipx -source/serdes_sync_upstream.lpc -source/serdes_sync_upstream.txt -source/soda_client_synconstraints.fdc -source/soda_hub_synconstraints.fdc -source/soda_source_clock_constraints.sdc -source/soda_source_syn_translated.fdc -source/soda_source_synconstraints.fdc + diff --git a/code/ip/serdes_4_sync_hub_downstream.ipx b/code/ip/serdes_4_sync_hub_downstream.ipx index 097fa1d..249341e 100644 --- a/code/ip/serdes_4_sync_hub_downstream.ipx +++ b/code/ip/serdes_4_sync_hub_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_4_sync_hub_downstream.lpc b/code/ip/serdes_4_sync_hub_downstream.lpc index 5e37d49..b087641 100644 --- a/code/ip/serdes_4_sync_hub_downstream.lpc +++ b/code/ip/serdes_4_sync_hub_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_4_sync_hub_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=04/16/2014 -Time=12:16:52 +Date=05/06/2014 +Time=15:48:34 [Parameters] Verilog=0 @@ -190,10 +190,10 @@ _cc_match_mode0=1 _cc_match_mode1=1 _cc_match_mode2=1 _cc_match_mode3=1 -_k00=01 -_k01=01 -_k02=01 -_k03=01 +_k00=00 +_k01=00 +_k02=00 +_k03=00 _k10=00 _k11=00 _k12=00 @@ -207,9 +207,9 @@ _k31=01 _k32=01 _k33=01 _byten00=00011100 -_byten01=0000000000011100 -_byten02=0000000000011100 -_byten03=0000000000011100 +_byten01=00011100 +_byten02=00011100 +_byten03=00011100 _byten10=00000000 _byten11=00000000 _byten12=00000000 diff --git a/code/ip/serdes_4_sync_hub_downstream.txt b/code/ip/serdes_4_sync_hub_downstream.txt index c22d59e..e4dbb5d 100644 --- a/code/ip/serdes_4_sync_hub_downstream.txt +++ b/code/ip/serdes_4_sync_hub_downstream.txt @@ -131,10 +131,10 @@ CH0_CTC "DISABLED" CH1_CTC "DISABLED" CH2_CTC "DISABLED" CH3_CTC "DISABLED" -CH0_CC_MATCH4 "0100011100" -CH1_CC_MATCH4 "010000000000011100" -CH2_CC_MATCH4 "010000000000011100" -CH3_CC_MATCH4 "010000000000011100" +CH0_CC_MATCH4 "0000011100" +CH1_CC_MATCH4 "0000011100" +CH2_CC_MATCH4 "0000011100" +CH3_CC_MATCH4 "0000011100" CH0_CC_MATCH_MODE "1" CH1_CC_MATCH_MODE "1" CH2_CC_MATCH_MODE "1" diff --git a/code/ip/serdes_sync_client_upstream.txt b/code/ip/serdes_sync_client_upstream.txt index b6d5e8e..54e4aa3 100644 --- a/code/ip/serdes_sync_client_upstream.txt +++ b/code/ip/serdes_sync_client_upstream.txt @@ -30,7 +30,7 @@ CH0_RTERM_TX "50" CH0_RX_EQ "DISABLED" CH0_RTERM_RX "50" CH0_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "3" +CH0_LOS_THRESHOLD_LO "2" PLL_TERM "50" PLL_DCC "AC" PLL_LOL_SET "0" diff --git a/code/ip/serdes_sync_source_downstream.ipx b/code/ip/serdes_sync_source_downstream.ipx index 6af1af9..1d162da 100644 --- a/code/ip/serdes_sync_source_downstream.ipx +++ b/code/ip/serdes_sync_source_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_source_downstream.lpc b/code/ip/serdes_sync_source_downstream.lpc index 7fd9af7..666dd56 100644 --- a/code/ip/serdes_sync_source_downstream.lpc +++ b/code/ip/serdes_sync_source_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_source_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=04/15/2014 -Time=15:10:18 +Date=04/29/2014 +Time=08:57:46 [Parameters] Verilog=0 @@ -91,7 +91,7 @@ _rx_data_width0=8 _rx_data_width1=8 _rx_data_width2=8 _rx_data_width3=8 -_rx_fifo0=DISABLED +_rx_fifo0=ENABLED _rx_fifo1=ENABLED _rx_fifo2=ENABLED _rx_fifo3=ENABLED diff --git a/code/ip/serdes_sync_source_downstream.txt b/code/ip/serdes_sync_source_downstream.txt index ec77632..fdbe384 100644 --- a/code/ip/serdes_sync_source_downstream.txt +++ b/code/ip/serdes_sync_source_downstream.txt @@ -20,7 +20,7 @@ CH0_TX_DATA_RATE "FULL" CH0_TX_DATA_WIDTH "8" CH0_RX_DATA_WIDTH "8" CH0_TX_FIFO "DISABLED" -CH0_RX_FIFO "DISABLED" +CH0_RX_FIFO "ENABLED" CH0_TDRV "0" #CH0_TX_FICLK_RATE 200 #CH0_RXREFCLK_RATE "200" @@ -30,7 +30,7 @@ CH0_RTERM_TX "50" CH0_RX_EQ "DISABLED" CH0_RTERM_RX "50" CH0_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "2" +CH0_LOS_THRESHOLD_LO "3" PLL_TERM "50" PLL_DCC "AC" PLL_LOL_SET "0" diff --git a/code/ip/serdes_sync_source_downstream.vhd b/code/ip/serdes_sync_source_downstream.vhd index 5a7c8a5..0c3024f 100644 --- a/code/ip/serdes_sync_source_downstream.vhd +++ b/code/ip/serdes_sync_source_downstream.vhd @@ -1538,6 +1538,7 @@ entity serdes_sync_source_downstream is hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; txiclk_ch0 : in std_logic; rx_full_clk_ch0 : out std_logic; rx_half_clk_ch0 : out std_logic; @@ -2201,7 +2202,7 @@ port map ( PCIE_PHYSTATUS_0 => open, SCISELCH0 => sci_sel_ch0, SCIENCH0 => fpsc_vhi, - FF_RXI_CLK_0 => fpsc_vlo, + FF_RXI_CLK_0 => rxiclk_ch0, FF_TXI_CLK_0 => txiclk_ch0, FF_EBRD_CLK_0 => fpsc_vlo, FF_RX_F_CLK_0 => rx_full_clk_ch0, diff --git a/code/ip/serdes_sync_upstream.ipx b/code/ip/serdes_sync_upstream.ipx index 1485eb0..be6e918 100644 --- a/code/ip/serdes_sync_upstream.ipx +++ b/code/ip/serdes_sync_upstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_upstream.lpc b/code/ip/serdes_sync_upstream.lpc index 15a05bb..7cbc9d4 100644 --- a/code/ip/serdes_sync_upstream.lpc +++ b/code/ip/serdes_sync_upstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_upstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/25/2014 -Time=13:39:52 +Date=05/06/2014 +Time=11:35:18 [Parameters] Verilog=0 @@ -39,10 +39,10 @@ _ldr0=DISABLED _ldr1=DISABLED _ldr2=DISABLED _ldr3=DISABLED -_datarange=2.0 +_datarange=2 _pll_txsrc=INTERNAL _refclk_mult=10X -_refclk_rate=200.0 +_refclk_rate=200 _tx_protocol0=DISABLED _tx_protocol1=DISABLED _tx_protocol2=DISABLED @@ -55,14 +55,14 @@ _tx_data_width0=8 _tx_data_width1=8 _tx_data_width2=8 _tx_data_width3=8 -_tx_fifo0=ENABLED +_tx_fifo0=DISABLED _tx_fifo1=ENABLED _tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=200.0 -_tx_ficlk_rate1=200.0 -_tx_ficlk_rate2=200.0 -_tx_ficlk_rate3=200.0 +_tx_fifo3=DISABLED +_tx_ficlk_rate0=200 +_tx_ficlk_rate1=200 +_tx_ficlk_rate2=200 +_tx_ficlk_rate3=200 _pll_rxsrc0=INTERNAL _pll_rxsrc1=EXTERNAL _pll_rxsrc2=EXTERNAL @@ -71,7 +71,7 @@ Multiplier0= Multiplier1= Multiplier2= Multiplier3= -_rx_datarange0=2.0 +_rx_datarange0=2 _rx_datarange1=2.5 _rx_datarange2=2.5 _rx_datarange3=2 @@ -83,7 +83,7 @@ _rx_data_rate0=FULL _rx_data_rate1=FULL _rx_data_rate2=FULL _rx_data_rate3=FULL -_rxrefclk_rate0=200.0 +_rxrefclk_rate0=200 _rxrefclk_rate1=250.0 _rxrefclk_rate2=250.0 _rxrefclk_rate3=200 @@ -95,7 +95,7 @@ _rx_fifo0=DISABLED _rx_fifo1=ENABLED _rx_fifo2=ENABLED _rx_fifo3=DISABLED -_rx_ficlk_rate0=200.0 +_rx_ficlk_rate0=200 _rx_ficlk_rate1=250.0 _rx_ficlk_rate2=250.0 _rx_ficlk_rate3=200 @@ -119,7 +119,7 @@ _rterm_rx0=50 _rterm_rx1=50 _rterm_rx2=50 _rterm_rx3=50 -_rx_dcc0=AC +_rx_dcc0=DC _rx_dcc1=AC _rx_dcc2=AC _rx_dcc3=DC @@ -192,7 +192,7 @@ _cc_match_mode2=1 _cc_match_mode3=1 _k00=01 _k01=00 -_k02=01 +_k02=00 _k03=01 _k10=00 _k11=00 @@ -208,7 +208,7 @@ _k32=01 _k33=01 _byten00=00011100 _byten01=00000000 -_byten02=00011100 +_byten02=00000000 _byten03=00011100 _byten10=00000000 _byten11=00000000 @@ -243,8 +243,8 @@ _rx_los_port1=Internal _rx_los_port2=Internal _rx_los_port3=Internal _sci_ports=ENABLED -_sci_int_port=ENABLED -_refck2core=DISABLED +_sci_int_port=DISABLED +_refck2core=ENABLED Regen=module PAR1=0 PARTrace1=0 diff --git a/code/ip/serdes_sync_upstream.vhd b/code/ip/serdes_sync_upstream.vhd index e1a71a5..0f86b70 100644 --- a/code/ip/serdes_sync_upstream.vhd +++ b/code/ip/serdes_sync_upstream.vhd @@ -1574,11 +1574,11 @@ entity serdes_sync_upstream is sci_sel_quad : in std_logic; sci_rd : in std_logic; sci_wrn : in std_logic; - sci_int : out std_logic; fpga_txrefclk : in std_logic; tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; rst_qd_c : in std_logic; + refclk2fpga : out std_logic; serdes_rst_qd_c : in std_logic); end serdes_sync_upstream; @@ -2105,7 +2105,7 @@ end component; attribute CH3_CDR_SRC: string; attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; @@ -2113,7 +2113,7 @@ end component; attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; @@ -2121,21 +2121,23 @@ end component; attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_REFCK2CORE: string; + attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; @@ -2166,6 +2168,7 @@ begin vlo_inst : VLO port map(Z => fpsc_vlo); vhi_inst : VHI port map(Z => fpsc_vhi); + refclk2fpga <= refclk2fpga_sig; rx_los_low_ch3_s <= rx_los_low_ch3_sig; rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; @@ -2636,7 +2639,7 @@ port map ( SCIRD => sci_rd, SCIWSTN => sci_wrn, CYAWSTN => fpsc_vlo, - SCIINT => sci_int, + SCIINT => open, FFC_CK_CORE_TX => fpga_txrefclk, FFC_MACRO_RST => serdes_rst_qd_c, FFC_QUAD_RST => rst_qd_c, diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index b415a3b..3b0abae 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -214,7 +214,7 @@ THE_SERDES : entity work.serdes_sync_source_downstream hdinn_ch0 => SD_RXD_N_IN, hdoutp_ch0 => SD_TXD_P_OUT, hdoutn_ch0 => SD_TXD_N_OUT, --- rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL! + rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL! txiclk_ch0 => clk_200_i, rx_full_clk_ch0 => clk_rx_full, rx_half_clk_ch0 => clk_rx_half, diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index fb2e98c..a9a0745 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -217,45 +217,45 @@ end generate; ------------------------------------------------- -- Serdes ------------------------------------------------- -THE_SERDES : entity work.serdes_sync_client_upstream +THE_SERDES : entity work.serdes_sync_upstream port map( - hdinp_ch0 => SD_RXD_P_IN, - hdinn_ch0 => SD_RXD_N_IN, - hdoutp_ch0 => SD_TXD_P_OUT, - hdoutn_ch0 => SD_TXD_N_OUT, --- rxiclk_ch0 => clk_200_i, -- no more RX-fifo - txiclk_ch0 => clk_200_i, - rx_full_clk_ch0 => clk_rx_full, - rx_half_clk_ch0 => clk_rx_half, - tx_full_clk_ch0 => clk_tx_full, - tx_half_clk_ch0 => clk_tx_half, - fpga_rxrefclk_ch0 => clk_200_internal, - txdata_ch0 => tx_data, - tx_k_ch0 => tx_k, - tx_force_disp_ch0 => '0', - tx_disp_sel_ch0 => '0', - rxdata_ch0 => rx_data, - rx_k_ch0 => rx_k, - rx_disp_err_ch0 => open, - rx_cv_err_ch0 => rx_error, - rx_serdes_rst_ch0_c => rx_serdes_rst, - sb_felb_ch0_c => '0', - sb_felb_rst_ch0_c => '0', - tx_pcs_rst_ch0_c => tx_pcs_rst, - tx_pwrup_ch0_c => '1', - rx_pcs_rst_ch0_c => rx_pcs_rst, - rx_pwrup_ch0_c => '1', - rx_los_low_ch0_s => rx_los_low, - lsm_status_ch0_s => lsm_status, - rx_cdr_lol_ch0_s => rx_cdr_lol, - tx_div2_mode_ch0_c => '0', - rx_div2_mode_ch0_c => '0', + hdinp_ch3 => SD_RXD_P_IN, + hdinn_ch3 => SD_RXD_N_IN, + hdoutp_ch3 => SD_TXD_P_OUT, + hdoutn_ch3 => SD_TXD_N_OUT, +-- rxiclk_ch3 => clk_200_i, -- no more RX-fifo + txiclk_ch3 => clk_200_i, + rx_full_clk_ch3 => clk_rx_full, + rx_half_clk_ch3 => clk_rx_half, + tx_full_clk_ch3 => clk_tx_full, + tx_half_clk_ch3 => clk_tx_half, + fpga_rxrefclk_ch3 => clk_200_internal, + txdata_ch3 => tx_data, + tx_k_ch3 => tx_k, + tx_force_disp_ch3 => '0', + tx_disp_sel_ch3 => '0', + rxdata_ch3 => rx_data, + rx_k_ch3 => rx_k, + rx_disp_err_ch3 => open, + rx_cv_err_ch3 => rx_error, + rx_serdes_rst_ch3_c => rx_serdes_rst, + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pcs_rst_ch3_c => tx_pcs_rst, + tx_pwrup_ch3_c => '1', + rx_pcs_rst_ch3_c => rx_pcs_rst, + rx_pwrup_ch3_c => '1', + rx_los_low_ch3_s => rx_los_low, + lsm_status_ch3_s => lsm_status, + rx_cdr_lol_ch3_s => rx_cdr_lol, + tx_div2_mode_ch3_c => '0', + rx_div2_mode_ch3_c => '0', SCI_WRDATA => sci_data_in_i, SCI_RDDATA => sci_data_out_i, SCI_ADDR => sci_addr_i(5 downto 0), SCI_SEL_QUAD => sci_qd_i, - SCI_SEL_ch0 => sci_ch_i(0), + SCI_SEL_ch3 => sci_ch_i(0), SCI_RD => sci_read_i, SCI_WRN => sci_write_i, @@ -273,7 +273,7 @@ THE_SERDES : entity work.serdes_sync_client_upstream THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n, - RX_REFCLK => clk_200_i, --nternal, -- allways running PL! + RX_REFCLK => clk_200_internal, -- allways running PL! TX_PLL_LOL_QD_S => tx_pll_lol, RX_SERDES_RST_CH_C => rx_serdes_rst, RX_CDR_LOL_CH_S => rx_cdr_lol, diff --git a/code/trb3_periph_sodaclient.vhd b/code/trb3_periph_sodaclient.vhd index 6d5203e..a8bba63 100644 --- a/code/trb3_periph_sodaclient.vhd +++ b/code/trb3_periph_sodaclient.vhd @@ -193,15 +193,15 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is --SODA - signal soda_rx_clock_half : std_logic; - signal soda_rx_clock_full : std_logic; - signal tx_dlm_i : std_logic; - signal rx_dlm_i : std_logic; - signal tx_dlm_word : std_logic_vector(7 downto 0); - signal rx_dlm_word : std_logic_vector(7 downto 0); - signal make_reset : std_logic; - signal tx_dlm_preview_S : std_logic; --PL! - signal link_phase_S : std_logic; --PL! +signal soda_rx_clock_half : std_logic; +signal soda_rx_clock_full : std_logic; +signal tx_dlm_i : std_logic; +signal rx_dlm_i : std_logic; +signal tx_dlm_word : std_logic_vector(7 downto 0); +signal rx_dlm_word : std_logic_vector(7 downto 0); +signal make_reset : std_logic; +signal tx_dlm_preview_S : std_logic; --PL! +signal link_phase_S : std_logic; --PL! -- SODA slow controll signal soda_ack : std_logic; @@ -223,10 +223,6 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is attribute syn_keep of soda_rx_clock_full : signal is true; attribute syn_preserve of soda_rx_clock_half : signal is true; attribute syn_keep of soda_rx_clock_half : signal is true; --- attribute syn_preserve of soda_tx_clock_full : signal is true; --- attribute syn_keep of soda_tx_clock_full : signal is true; --- attribute syn_preserve of soda_tx_clock_half : signal is true; --- attribute syn_keep of soda_tx_clock_half : signal is true; attribute syn_preserve of clk_sys_internal : signal is true; attribute syn_keep of clk_sys_internal : signal is true; attribute syn_preserve of clk_raw_internal : signal is true; @@ -243,7 +239,6 @@ begin --------------------------------------------------------------------------- - TEST_LINE <= (others => '0'); -- otherwise it is floating LED_RX <= (others => '0'); -- otherwise it is floating LED_TX <= (others => '0'); -- otherwise it is floating LED_LINKOK <= (others => '0'); -- otherwise it is floating @@ -525,7 +520,7 @@ THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch THE_SYNC_LINK : med_ecp3_sfp_sync_up generic map( - SERDES_NUM => 0, --number of serdes in quad + SERDES_NUM => 1, --number of serdes in quad IS_SYNC_SLAVE => c_YES ) port map( @@ -552,15 +547,15 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL! LINK_PHASE_OUT => link_phase_S, --PL! --SFP Connection - SD_RXD_P_IN => SERDES_ADDON_RX(0), - SD_RXD_N_IN => SERDES_ADDON_RX(1), - SD_TXD_P_OUT => SERDES_ADDON_TX(0), - SD_TXD_N_OUT => SERDES_ADDON_TX(1), + SD_RXD_P_IN => SERDES_ADDON_RX(4), --(0), + SD_RXD_N_IN => SERDES_ADDON_RX(5), --(1), + SD_TXD_P_OUT => SERDES_ADDON_TX(4), --(0), + SD_TXD_N_OUT => SERDES_ADDON_TX(5), --(1), SD_REFCLK_P_IN => '0', SD_REFCLK_N_IN => '0', - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1), + SD_PRSNT_N_IN => SFP_MOD0(3), --(1), + SD_LOS_IN => SFP_LOS(3), --(1), + SD_TXDIS_OUT => sfp_txdis_S(3), --(1), --SFP_TXDIS(1), SCI_DATA_IN => sci1_data_in, SCI_DATA_OUT => sci1_data_out, @@ -612,8 +607,8 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= SFP_LOS(1); --med_stat_op(8); - LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); + LED_ORANGE <= SFP_LOS(3); --med_stat_op(8); + LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10); LED_GREEN <= med_stat_op(12); --tx_pll_lol LED_RED <= med_stat_op(11); --rx_cdr_lol -- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal); @@ -646,6 +641,18 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up soda_counter_i <= soda_counter_i+1; end if; end process; + + TEST_LINE(0) <= time_counter(1); + TEST_LINE(1) <= '0'; + TEST_LINE(2) <= '0'; + TEST_LINE(3) <= soda_counter_i(2); + TEST_LINE(4) <= '0'; + TEST_LINE(5) <= '0'; + TEST_LINE(6) <= soda_rx_clock_half; + TEST_LINE(7) <= '0'; + TEST_LINE(8) <= '0'; + + TEST_LINE(15 downto 9) <= (others => '0'); -- otherwise it is floating - + end trb3_periph_sodaclient_arch; \ No newline at end of file diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index 2ccab92..103cfb4 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -185,7 +185,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal rxup_dlm_word : std_logic_vector(7 downto 0); signal txup_dlm_preview_S : std_logic; --PL! signal uplink_phase_S : std_logic; --PL! - signal uplink_disable_S : std_logic; + signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); --SODA downlink signal txdn_dlm_i : t_HUB_BIT; @@ -238,7 +238,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is -- fix signal names for constraining attribute syn_preserve of soda_rxup_clock_full : signal is true; attribute syn_keep of soda_rxup_clock_full : signal is true; - + attribute syn_preserve of clk_sys_internal : signal is true; attribute syn_keep of clk_sys_internal : signal is true; attribute syn_preserve of clk_raw_internal : signal is true; @@ -467,15 +467,15 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL! LINK_PHASE_OUT => uplink_phase_S, --PL! --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting - SD_RXD_P_IN => SERDES_ADDON_RX(8), - SD_RXD_N_IN => SERDES_ADDON_RX(9), - SD_TXD_P_OUT => SERDES_ADDON_TX(8), - SD_TXD_N_OUT => SERDES_ADDON_TX(9), + SD_RXD_P_IN => SERDES_ADDON_RX(4), + SD_RXD_N_IN => SERDES_ADDON_RX(5), + SD_TXD_P_OUT => SERDES_ADDON_TX(4), + SD_TXD_N_OUT => SERDES_ADDON_TX(5), SD_REFCLK_P_IN => '0', SD_REFCLK_N_IN => '0', SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0 SD_LOS_IN => SFP_LOS(3), - SD_TXDIS_OUT => uplink_disable_S, --SFP_TXDIS(3), this signal is now used to release downlinks + SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks SCI_DATA_IN => sci1_data_in, SCI_DATA_OUT => sci1_data_out, @@ -491,7 +491,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up CTRL_DEBUG => (others => '0') ); - SFP_TXDIS(3) <= uplink_disable_S; +-- SFP_TXDIS(3) <= sfp_txdis_S; + SFP_TXDIS <= sfp_txdis_S; --------------------------------------------------------------------------- -- The Soda Central @@ -545,7 +546,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up RESET => reset_i, CLEAR => clear_i, --------------------------------------------------------------------------------------------------------------------------------------------------------- - LINK_DISABLE_IN => uplink_disable_S,-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. --------------------------------------------------------------------------------------------------------------------------------------------------------- -- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16), MED_DATA_IN(0) => med_data_out(1*16+15 downto 1*16), @@ -655,10 +656,10 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up SD_LOS_IN(1) => SFP_LOS(6), SD_LOS_IN(2) => SFP_LOS(2), SD_LOS_IN(3) => SFP_LOS(4), - SD_TXDIS_OUT(0) => SFP_TXDIS(1), - SD_TXDIS_OUT(1) => SFP_TXDIS(6), - SD_TXDIS_OUT(2) => SFP_TXDIS(2), - SD_TXDIS_OUT(3) => SFP_TXDIS(4), + SD_TXDIS_OUT(0) => sfp_txdis_S(1), + SD_TXDIS_OUT(1) => sfp_txdis_S(6), + SD_TXDIS_OUT(2) => sfp_txdis_S(2), + SD_TXDIS_OUT(3) => sfp_txdis_S(4), SCI_DATA_IN => sci2_data_in, SCI_DATA_OUT => sci2_data_out, @@ -753,10 +754,14 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= '1'; --med_stat_op(8); - LED_YELLOW <= '0'; --med_stat_op(10); - LED_GREEN <= '0'; --med_stat_op(9); - LED_RED <= '1'; --med_stat_op(6); + LED_ORANGE <= SFP_LOS(1); --med_stat_op(8); + LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); + LED_GREEN <= med_stat_op(12); --tx_pll_lol + LED_RED <= med_stat_op(11); --rx_cdr_lol +-- LED_ORANGE <= '1'; --med_stat_op(8); +-- LED_YELLOW <= '0'; --med_stat_op(10); +-- LED_GREEN <= '0'; --med_stat_op(9); +-- LED_RED <= '1'; --med_stat_op(6); --------------------------------------------------------------------------- -- DEBUG diff --git a/soda_client.ldf b/soda_client.ldf index da04f89..93dc2c1 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -26,28 +26,28 @@ - + - + - + - + - + - + - + - + @@ -314,13 +314,13 @@ - + - + - + diff --git a/soda_client.lpf b/soda_client.lpf index e65d083..b047079 100644 --- a/soda_client.lpf +++ b/soda_client.lpf @@ -1,4 +1,4 @@ -rvl_alias "soda_rx_clock_full" "soda_rx_clock_full"; +rvl_alias "clk_soda_i" "clk_soda_i"; RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; @@ -196,7 +196,7 @@ SYSCONFIG MCCLK_FREQ=20 ; #LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; #LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; #LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; #REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE; # Uplink is now fiber ! #REGION "SPI_REGION" "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE; #REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE; diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl index 4b2f652..fb81dcb 100644 --- a/soda_client_probe.rvl +++ b/soda_client_probe.rvl @@ -1,9 +1,9 @@ - + - + - + @@ -11,62 +11,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -90,11 +34,6 @@ - - - - - @@ -105,6 +44,24 @@ + + + + + + + + + + + + + + + + + + @@ -139,92 +96,37 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + - - - - diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index 6ca046c..7d81ab7 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,7 +1,7 @@ - + - + @@ -11,14 +11,23 @@ - - - - - + + + + + + + + + + + + + + + + - - @@ -42,7 +51,6 @@ - @@ -50,10 +58,6 @@ - - - - @@ -87,51 +91,231 @@ - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + + + + - - - - - - - - - - - - - - - - - - - - - - - + + + + + diff --git a/soda_source.ldf b/soda_source.ldf index c94c37a..9114673 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -38,6 +38,15 @@ + + + + + + + + + @@ -302,15 +311,6 @@ - - - - - - - - - diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj deleted file mode 100644 index cc7ca04..0000000 --- a/soda_source/soda_source_syn.prj +++ /dev/null @@ -1,164 +0,0 @@ -#-- Synopsys, Inc. -#-- Version I-2013.09L -#-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj -#-- Written on Tue Apr 15 15:02:27 2014 - - -#project files -add_file -fpga_constraint "/local/lemmens/lattice/soda/code/soda_source_synconstraints.fdc" -add_file -vhdl -lib work "/usr/local/diamond/3.1_x64/cae_library/synthesis/vhdl/ecp3.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/version.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_components.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_source.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_d8crc8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_packet_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_superburst_gen.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/med_ecp3_sfp_sync_down.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_SOB_faker.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_calibration_timer.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_reply_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_tx_control.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_data.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_ipu.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_trigger_and_data.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/trb_net_reset_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/fpga_reboot.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_ltc2600.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/pulse_sync.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/state_sync.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_dp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_dp_rw.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/pulse_stretch.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf5.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf6.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_dummy_fifo.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_dummy_fifo.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf_nodata.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_endpoint_hades_full_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_control.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/tx_reset_fsm.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_base.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_func.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/trb3_periph_sodasource.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_packet_builder.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/posedge_to_pulse.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/serdes_sync_source_downstream.vhd" - - - -#implementation: "soda_source" -impl -add soda_source -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 - -#device options -set_option -technology LATTICE-ECP3 -set_option -part LFE3_150EA -set_option -package FN672C -set_option -speed_grade -8 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "trb3_periph_sodasource" - -# mapper_options -set_option -frequency 200 -set_option -write_verilog 0 -set_option -write_vhdl 0 -set_option -srs_instrumentation 1 - -# Lattice XP -set_option -maxfan 1000 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 1 -set_option -forcegsr auto -set_option -fix_gated_and_generated_clocks 1 -set_option -RWCheckOnRam 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 -set_option -multi_file_compilation_unit 1 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./soda_source.edi" -impl -active "soda_source" diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index e089486..1cf260f 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,13 +1,13 @@ - + - + - + - + @@ -76,6 +76,9 @@ + + + @@ -99,6 +102,7 @@ + @@ -170,6 +174,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx deleted file mode 100644 index 5ace6b2..0000000 --- a/source/serdes_sync_downstream.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc deleted file mode 100644 index 450fb27..0000000 --- a/source/serdes_sync_downstream.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_sync_downstream -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/07/2014 -Time=16:16:00 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=RXTX -_mode1=DISABLED -_mode2=DISABLED -_mode3=DISABLED -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=2 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=200 -_tx_protocol0=G8B10B -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=DISABLED -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=DISABLED -_tx_fifo1=DISABLED -_tx_fifo2=DISABLED -_tx_fifo3=DISABLED -_tx_ficlk_rate0=200 -_tx_ficlk_rate1=200 -_tx_ficlk_rate2=200 -_tx_ficlk_rate3=200 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=INTERNAL -_pll_rxsrc2=INTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=2.5 -_rx_protocol0=G8B10B -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=DISABLED -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=200 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=250.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=DISABLED -_rx_fifo1=DISABLED -_rx_fifo2=DISABLED -_rx_fifo3=DISABLED -_rx_ficlk_rate0=200 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=250.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=DC -_rx_dcc1=DC -_rx_dcc2=DC -_rx_dcc3=DC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=01 -_k01=00 -_k02=00 -_k03=00 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=01 -_byten00=00011100 -_byten01=00000000 -_byten02=00000000 -_byten03=00000000 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=ENABLED -_sci_int_port=DISABLED -_refck2core=ENABLED -Regen=module -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_sync_downstream.pp=pp -serdes_sync_downstream.tft=tft -serdes_sync_downstream.txt=pcs_module -serdes_sync_downstream.sym=sym diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt deleted file mode 100644 index ec77632..0000000 --- a/source/serdes_sync_downstream.txt +++ /dev/null @@ -1,58 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "G8B10B" -CH0_MODE "RXTX" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "DISABLED" -CH0_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH0_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200 -CH0_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "DISABLED" -CH0_RX_FIFO "DISABLED" -CH0_TDRV "0" -#CH0_TX_FICLK_RATE 200 -#CH0_RXREFCLK_RATE "200" -#CH0_RX_FICLK_RATE 200 -CH0_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH0_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111100" -CH0_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH0_CC_MATCH4 "0100011100" -CH0_CC_MATCH_MODE "1" -CH0_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/source/tb/TB_soda_source.vhd b/source/tb/TB_soda_source.vhd deleted file mode 100644 index d1b5b46..0000000 --- a/source/tb/TB_soda_source.vhd +++ /dev/null @@ -1,162 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - ---library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; ---use work.trb3_components.all; ---use work.med_sync_define.all; ---use work.version.all; - -entity TB_soda_source is -end entity; - -architecture TestBench of TB_soda_source is - - -- Clock period definitions - constant clk_period : time := 4ns; - - -component super_burst_generator - generic( - BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts - ); -port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - SODA_BURST_PULSE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : out std_logic := '0'; - SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') - ); -end component; - -component soda_packet_builder - port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - SODA_CMD_STROBE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : in std_logic := '0'; - SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); - SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit - TX_DLM_OUT : out std_logic := '0'; -- - TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') - ); -end component; - -component soda_packet_handler -port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); - RX_DLM_IN : in std_logic - ); -end component; - ---Inputs - signal rst_S : std_logic; - signal clk_S : std_logic; - signal enable_S : std_logic := '0'; - signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0'); - signal soda_cmd_strobe_S : std_logic := '0'; - signal SOS_S : std_logic := '0'; - signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator - signal SOB_S : std_logic := '0'; - signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); - signal dlm_valid_S : std_logic; - -begin - - superburst_gen : super_burst_generator - generic map(BURST_COUNT => 16) - port map( - SYSCLK => clk_S, - RESET => rst_S, - CLEAR => '0', - CLK_EN => '0', - --Internal Connection - SODA_BURST_PULSE_IN => SOB_S, - START_OF_SUPERBURST => SOS_S, - SUPER_BURST_NR_OUT => super_burst_nr_S - ); - - packet_builder : soda_packet_builder - port map( - SYSCLK => clk_S, - RESET => rst_S, - CLEAR => '0', - CLK_EN => '0', - --Internal Connection - SODA_CMD_STROBE_IN => soda_cmd_strobe_S, - START_OF_SUPERBURST => SOS_S, - SUPER_BURST_NR_IN => super_burst_nr_S, - SODA_CMD_WORD_IN => soda_cmd_word_S, - TX_DLM_OUT => dlm_valid_S, - TX_DLM_WORD_OUT => dlm_word_S - - ); - - packet_handler : soda_packet_handler - port map( - SYSCLK => clk_S, - RESET => rst_S, - CLEAR => '0', - CLK_EN => '0', - --Internal Connection - RX_DLM_IN => dlm_valid_S, - RX_DLM_WORD_IN => dlm_word_S - ); - ------------------------------------------------------------------------------------------------------------- - -- SODA command packet ------------------------------------------------------------------------------------------------------------- - cmd_proc :process - begin - wait for 2us; - soda_cmd_word_S <= x"40000000"; - soda_cmd_strobe_S <= '1'; - wait for clk_period; - soda_cmd_strobe_S <= '0'; - wait; - end process; - ------------------------------------------------------------------------------------------------------------- - -- Clock process definitions ------------------------------------------------------------------------------------------------------------- - clk_proc :process - begin - clk_S <= '0'; - wait for clk_period/2; - clk_S <= '1'; - wait for clk_period/2; - end process; - - -- reset process - reset_proc: process - begin - rst_S <= '1'; - wait for clk_period * 5; - rst_S <= '0'; - wait; - end process; - - burst_proc :process - begin - SOB_S <= '0'; - wait for 2.35us; - SOB_S <= '1'; - wait for 50ns; - end process; - - -end TestBench; - diff --git a/trb3_soda_client.xcf b/trb3_soda_client.xcf index 4b65926..b9c0e70 100644 --- a/trb3_soda_client.xcf +++ b/trb3_soda_client.xcf @@ -47,8 +47,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140325.bit - 03/26/14 14:07:54 + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit + 05/06/14 09:58:37 Fast Program