From 0f5f9975a8a83591ab33f1757ee2f06f1b093950 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 2 Sep 2019 10:21:00 +0200 Subject: [PATCH] update TRB3sc mimosis readout code --- mimosis/settings.sh | 2 +- mimosis/trb3sc_mimosis.vhd | 49 ++++++++++++++++++++++++++++++++++---- pinout/trb3sc_mimosis.lpf | 2 +- 3 files changed, 46 insertions(+), 7 deletions(-) diff --git a/mimosis/settings.sh b/mimosis/settings.sh index 281509e..8b0d430 100755 --- a/mimosis/settings.sh +++ b/mimosis/settings.sh @@ -1,6 +1,6 @@ #!/bin/bash -export DAQOPSERVER=jspc55:82 +export DAQOPSERVER=jspc29:82 trbcmd reset trbcmd w 0xf3cb 0xa001 0x409c #40000 diff --git a/mimosis/trb3sc_mimosis.vhd b/mimosis/trb3sc_mimosis.vhd index 82ff1ff..b3b24a9 100644 --- a/mimosis/trb3sc_mimosis.vhd +++ b/mimosis/trb3sc_mimosis.vhd @@ -160,6 +160,8 @@ architecture trb3sc_arch of trb3sc_mimosis is signal input_data : std_logic_vector(18 downto 0); signal sclk_r, sclk_rr : std_logic; signal last_valid : std_logic; + signal last_flag : std_logic; + signal chiptime : unsigned(15 downto 0); attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -453,7 +455,7 @@ end generate; SPI_MISO_IN => spi_miso, SPI_CLK_OUT => spi_clk, --Header - HEADER_IO => HDR_IO, + HEADER_IO => open, --HDR_IO, --LCD LCD_DATA_IN => lcd_data, --ADC @@ -526,17 +528,28 @@ end process; --------------------------------------------------------------------------- sclk_r <= CLK_IN when rising_edge(clk_sys); sclk_rr <= sclk_r when rising_edge(clk_sys); -input_data <= VALID_IN & CMD_IN & ADDRPIX_IN when rising_edge(clk_sys); +input_data <= VALID_IN & CMD_IN(7) & '0' & CMD_IN(5 downto 4) & ADDRPIX_IN when rising_edge(clk_sys); THE_READER : process begin wait until rising_edge(clk_sys); fifo_write <= '0'; - if sclk_r = '1' and sclk_rr = '0' then + if sclk_r = '0' and sclk_rr = '1' then + last_flag <= input_data(17); + if fwd_do_send = '1' and fifo_full = '0' then + if input_data(17) = '1' and last_flag = '0' then + fifo_data_in <= x"000" & "000" & input_data(18 downto 14) & std_logic_vector(chiptime); + fifo_write <= '1'; + end if; + end if; + + elsif sclk_r = '1' and sclk_rr = '0' then last_valid <= input_data(18); + chiptime <= chiptime + 1; + if fwd_do_send = '1' and fifo_full = '0' then - if input_data(18) = '1' then - fifo_data_in <= x"0" & x"000" & input_data(17 downto 14) & "00" & input_data(13 downto 0); + if input_data(18) = '1' then + fifo_data_in <= x"000" & "000" & input_data(18 downto 14) & "00" & input_data(13 downto 0); fifo_write <= '1'; elsif last_valid = '1' then fifo_data_in <= x"0FFFFFFFF"; @@ -673,6 +686,32 @@ end process; -- Test data --------------------------------------------------------------------------- + +gen_test_pulse : if 1 = 1 generate + signal pulse, pulse_r : std_logic; + signal cnt : unsigned(1 downto 0); + signal outp : std_logic; +begin + PROC_TRG_PULSE : process begin + wait until rising_edge(clk_sys); + pulse <= CMD_IN(6); + pulse_r <= pulse; + if pulse = '0' then + outp <= '0'; + end if; + if pulse = '1' and pulse_r = '0' then + cnt <= cnt + 1; + if cnt = 3 then + outp <= '1'; + end if; + end if; + end process; + + HDR_IO(1) <= outp; + +end generate; + + end architecture; diff --git a/pinout/trb3sc_mimosis.lpf b/pinout/trb3sc_mimosis.lpf index 0cc031d..b06d967 100644 --- a/pinout/trb3sc_mimosis.lpf +++ b/pinout/trb3sc_mimosis.lpf @@ -258,7 +258,7 @@ LOCATE COMP "HDR_IO_8" SITE "AG26"; LOCATE COMP "HDR_IO_9" SITE "AM28"; LOCATE COMP "HDR_IO_10" SITE "AL28"; DEFINE PORT GROUP "HDR_group" "HDR*" ; -IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; ################################################################# -- 2.43.0