From 0fee6d675abf011bf8713a896b1b2dccd36bb964 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 21 Jan 2019 13:17:23 +0100 Subject: [PATCH] update description of simple trigger module --- trb3/TriggerModule.tex | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex index 4b9163c..c008373 100644 --- a/trb3/TriggerModule.tex +++ b/trb3/TriggerModule.tex @@ -5,13 +5,25 @@ the CTS. E.g. any input to any TDC can be used to generate the trigger in the CT The VHDL code is available in \files{trb3/base/code/input\_to\_trigger\_logic\_record.vhd} \paragraph*{Setup} -The trigger module can feature up to 32 input signals and up to 16 independent outputs. -An extension to 64 inputs (matching the maximal number of inputs to the TDC) is foreseen but not -yet implemented. +The trigger module can feature up to 96 input signals and up to 16 independent outputs. + For each output, any of the connected inputs can be enabled or disabled as well as been inverted individually. The output is an 'or' of all enabled inputs. The peripheral FPGA can send four outputs to the central FPGA. Depending on the AddOn used, additional outputs can be routed to free -I/O pins if available. +I/O pins if available. Please refer to figure \ref{fig:triggeroptions} for more details. + +\begin{itemize*} +\item A simple 'or' of all enabled inputs, with the option of stretching signals by about 20 ns.\\ +\verb! chanA or chanB or chanC or ...! +\item A multiplicity logic ("at least N channels fire") \\ +\verb! chanA + chanB + chanC + ... >= N! +\item A simple coincidence logic between two groups of inputs (e.g. for two layers of detectors that both need to have a signal)\\ +\verb!or(group1) AND or(group2)! +\item An advanced coincidence logic that allows up to 16 pairs of channels (e.g. scintillator bars read out on both ends)\\ +\verb!(chanA and chanB) or (chanC and chanD) or ...! +\end{itemize*} + +All modules have their own configuration registers and can be used in combination of individually. The central FPGA contains the same trigger logic to combine the four signals from each of the peripheral FPGAs to one common signal forwarded on the trigger output on the RJ-45 connector -- 2.43.0