From 103bef52e32c3198146f032f6c024a64881c67c8 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 11 Jan 2022 20:38:35 +0100 Subject: [PATCH] RX SerDes problem seems to be solved --- code/clock_reset_handler.vhd | 40 +++++++++++++++--------------- cts/trb3sc_cts.vhd | 13 +++------- hub/config_compile_gsi.pl | 2 +- hub/trb3sc_hub.lpf | 20 ++++++++++----- hub/trb3sc_hub.vhd | 14 +++-------- tdctemplate/trb3sc_tdctemplate.vhd | 12 +++------ 6 files changed, 47 insertions(+), 54 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 63c141f..dc98b35 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -82,26 +82,26 @@ GSR_OUT <= not pll_int_lock or clear_n_i; -- keeps everything in reset until -- if RX clock is used, just forward what is provided, adjust internal as reference --------------------------------------------------------------------------- gen_recov_clock : if USE_RXCLOCK = c_YES generate - clk_selected_full <= NET_CLK_FULL_IN; - clk_selected_half <= NET_CLK_HALF_IN; - - timer <= (others => '1'); - - gen_200rec : if USE_120_MHZ = c_NO generate - THE_INT_PLL : entity work.pll_in240_out200 - port map( - CLK => INT_CLK_IN, - CLKOP => clk_int_full, - CLKOK => clk_int_half, - LOCK => pll_int_lock - ); - clk_selected_ref <= clk_int_full; - end generate; - - gen_240rec : if USE_120_MHZ = c_YES generate - clk_selected_ref <= INT_CLK_IN; - pll_int_lock <= '1'; - end generate; +-- clk_selected_full <= NET_CLK_FULL_IN; +-- clk_selected_half <= NET_CLK_HALF_IN; +-- +-- timer <= (others => '1'); +-- +-- gen_200rec : if USE_120_MHZ = c_NO generate +-- THE_INT_PLL : entity work.pll_in240_out200 +-- port map( +-- CLK => INT_CLK_IN, +-- CLKOP => clk_int_full, +-- CLKOK => clk_int_half, +-- LOCK => pll_int_lock +-- ); +-- clk_selected_ref <= clk_int_full; +-- end generate; +-- +-- gen_240rec : if USE_120_MHZ = c_YES generate +-- clk_selected_ref <= INT_CLK_IN; +-- pll_int_lock <= '1'; +-- end generate; end generate; --------------------------------------------------------------------------- diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index f8a7f0e..0c826df 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -323,7 +323,6 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS generic map( - SIM_MODE => 0, IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER), IS_WAP_ZERO => 1 ) @@ -395,9 +394,6 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate ); THE_MAIN_TX_RST: main_tx_reset_RS - generic map( - SIM_MODE => 0 - ) port map ( CLEAR => '0', CLK_REF => clk_full_osc, @@ -1030,11 +1026,10 @@ end generate; -- LED --------------------------------------------------------------------------- --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) - LED_GREEN <= not debug_i(11); -- LFD --debug_clock_reset(0); - LED_ORANGE <= not debug_i(10); -- LHD --debug_clock_reset(1); - LED_RED <= not debug_i(8); -- LRR --not sed_error_i; - LED_YELLOW <= not debug_i(7); -- LTR --debug_clock_reset(2); - + LED_GREEN <= not debug_i(24 + 3); -- LFD --debug_clock_reset(0); + LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1); + LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; + LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); gen_leds_addon : if USE_ADDON = c_YES generate gen_hub_leds : for i in 1 to 8 generate diff --git a/hub/config_compile_gsi.pl b/hub/config_compile_gsi.pl index 5275a82..140541b 100644 --- a/hub/config_compile_gsi.pl +++ b/hub/config_compile_gsi.pl @@ -3,7 +3,7 @@ lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", lattice_path => '/opt/lattice/diamond/3.12', synplify_path => '/opt/synplicity/R-2020.09-SP1', -synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier", +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp", nodelist_file => 'nodelist.txt', #pinout_file => '', diff --git a/hub/trb3sc_hub.lpf b/hub/trb3sc_hub.lpf index 342a282..e592159 100644 --- a/hub/trb3sc_hub.lpf +++ b/hub/trb3sc_hub.lpf @@ -5,12 +5,20 @@ LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PC LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; -REGION "MEDIA_DOWN1" "R102C20D" 13 120; -LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; -LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; -LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; -LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; -LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; +#REGION "MEDIA_DOWN1" "R102C20D" 13 120; +#LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; +#LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; + +REGION "MEDIA_LEFT" "R102C17D" 13 75; +REGION "MEDIA_RIGHT" "R102C92D" 13 75; +LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_RIGHT" ; +LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT" ; +LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT" ; +LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_RIGHT" ; +LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_LEFT" ; FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz; diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index 89a12e4..8024258 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -296,7 +296,6 @@ end generate; gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS generic map( - SIM_MODE => 0, IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE), IS_WAP_ZERO => 1 ) @@ -369,9 +368,6 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate end generate; THE_MAIN_TX_RST: main_tx_reset_RS - generic map( - SIM_MODE => 0 - ) port map ( CLEAR => '0', CLK_REF => clk_full_osc, @@ -394,7 +390,6 @@ end generate; --------------------------------------------------------------------------- THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS generic map( - SIM_MODE => 0, IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER), IS_WAP_ZERO => 1 ) @@ -465,7 +460,6 @@ end generate; gen_PCSD : if INCLUDE_GBE = c_NO generate THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS generic map( - SIM_MODE => 0, IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED), IS_WAP_ZERO => 1 ) @@ -891,10 +885,10 @@ end generate; -- LED --------------------------------------------------------------------------- --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) - LED_GREEN <= not debug_i(11); -- LFD --debug_clock_reset(0); - LED_ORANGE <= not debug_i(10); -- LHD --debug_clock_reset(1); - LED_RED <= not debug_i(8); -- LRR --not sed_error_i; - LED_YELLOW <= not debug_i(7); -- LTR --debug_clock_reset(2); + LED_GREEN <= not debug_i(24 + 3); -- LFD --debug_clock_reset(0); + LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1); + LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; + LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); gen_hub_leds : for i in 0 to 6 generate LED_HUB_LINKOK(i+1) <= not med2int(i).stat_op(9); diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index a81985d..9bcf083 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -209,7 +209,6 @@ end generate; --------------------------------------------------------------------------- THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS generic map( - SIM_MODE => 0, IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE), IS_WAP_ZERO => 1 ) @@ -281,9 +280,6 @@ end generate; ); THE_MAIN_TX_RST: main_tx_reset_RS - generic map( - SIM_MODE => 0 - ) port map ( CLEAR => '0', CLK_REF => clk_full_osc, @@ -541,10 +537,10 @@ end generate; -- LED --------------------------------------------------------------------------- --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) - LED_GREEN <= not debug_i(11); -- LFD --debug_clock_reset(0); - LED_ORANGE <= not debug_i(10); -- LHD --debug_clock_reset(1); - LED_RED <= not debug_i(8); -- LRR --not sed_error_i; - LED_YELLOW <= not debug_i(7); -- LTR --debug_clock_reset(2); + LED_GREEN <= not debug_i(24 + 3); -- LFD --debug_clock_reset(0); + LED_ORANGE <= not debug_i(24 + 2); -- LHD --debug_clock_reset(1); + LED_RED <= not debug_i(24 + 1); -- LRR --not sed_error_i; + LED_YELLOW <= not debug_i(24 + 0); -- LTR --debug_clock_reset(2); LED_WHITE(0) <= time_counter(26) and time_counter(19); LED_WHITE(1) <= time_counter(20); LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status -- 2.43.0