From 1042ca44ca608a4c656f6390654334129d9cadf9 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 7 Apr 2021 08:41:16 +0200 Subject: [PATCH] additional wait state to compensate fifo read issue while write procedure via DCA --- src/cri_trbnet_dca_bridge.vhd | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd index f84303b..67df8b5 100644 --- a/src/cri_trbnet_dca_bridge.vhd +++ b/src/cri_trbnet_dca_bridge.vhd @@ -50,7 +50,7 @@ signal reset_dca : std_logic; attribute syn_encoding : string; -type dissect_states is (IDLE, GET_DCA_DATA, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, CHECK_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); +type dissect_states is (IDLE, GET_DCA_DATA, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, CHECK_RESPONSE, WAIT_CNTR, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); signal dissect_current_state, dissect_next_state : dissect_states; attribute syn_encoding of dissect_current_state: signal is "onehot"; @@ -126,6 +126,8 @@ signal preload_word_tx_fifo : std_logic; signal tx_data_out : std_logic_vector(31 downto 0); +signal wait_cnt : unsigned(1 downto 0) := "00"; + begin reset_dca <= not RST_N_DCA; @@ -371,6 +373,13 @@ begin tx_fifo_rd <= '0'; preload_word_tx_fifo <= '0'; end if; + + if (dissect_current_state = WAIT_CNTR) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= "00"; + end if; + end if; end process TX_FIFO_READ_PROC; @@ -516,9 +525,15 @@ begin when CHECK_RESPONSE => state <= x"7"; - dissect_next_state <= WAIT_FOR_LOAD; + dissect_next_state <= WAIT_CNTR; + + when WAIT_CNTR => + if wait_cnt = 2 then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= WAIT_CNTR; + end if; - when WAIT_FOR_LOAD => state <= x"8"; if preload_word_tx_fifo = '1' then -- 2.43.0