From 10939c420991aeab986e649d3eeb23ffe8f74914 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 2 Jul 2021 19:39:01 +0200 Subject: [PATCH] update OEP project --- OEP/compile.pl | 1 + OEP/config.vhd | 99 +++++++ OEP/config_compile_frankfurt.pl | 25 ++ OEP/mdcoep.lpf | 41 +++ OEP/mdcoep.prj | 220 ++++++++++++++++ OEP/mdcoep.vhd | 446 ++++++++++++++++++++++++++++++++ OEP/par.p2t | 69 +++++ pinout/oep.lpf | 40 ++- 8 files changed, 934 insertions(+), 7 deletions(-) create mode 120000 OEP/compile.pl create mode 100644 OEP/config.vhd create mode 100644 OEP/config_compile_frankfurt.pl create mode 100644 OEP/mdcoep.lpf create mode 100644 OEP/mdcoep.prj create mode 100644 OEP/mdcoep.vhd create mode 100644 OEP/par.p2t diff --git a/OEP/compile.pl b/OEP/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/OEP/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/OEP/config.vhd b/OEP/config.vhd new file mode 100644 index 0000000..7a539d5 --- /dev/null +++ b/OEP/config.vhd @@ -0,0 +1,99 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes +-- constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "45KUM"; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F60E"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"90"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + + + constant use_120_mhz : integer := 0; +--TDC settings + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 400; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A6100000"; + + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := 100; + constant MEDIA_FREQUENCY : integer := 200; + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/OEP/config_compile_frankfurt.pl b/OEP/config_compile_frankfurt.pl new file mode 100644 index 0000000..f234c89 --- /dev/null +++ b/OEP/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-45F', +Package => 'CABGA381', +Speedgrade => '8', + + +TOPNAME => "mdcoep", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'oep', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/OEP/mdcoep.lpf b/OEP/mdcoep.lpf new file mode 100644 index 0000000..fa8bc77 --- /dev/null +++ b/OEP/mdcoep.lpf @@ -0,0 +1,41 @@ +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK 200 MHz; + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_HUB/reset_i" 15 ns; +BLOCK PATH FROM CLKNET "*/sci_read_i"; +BLOCK PATH FROM CLKNET "*/sci_write_i"; + + +#MULTICYCLE TO CELL "*/sci*" 20 ns; +#MULTICYCLE FROM CELL "*/sci*" 20 ns; +#MULTICYCLE TO CELL "*/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CELL "*/sci_addr_*"; + +#FREQUENCY NET "THE_MEDIA_INTERFACE/THE_SERDES/serdes_0_inst/clk_tx_full" 200 MHz; +#FREQUENCY NET "THE_MEDIA_INTERFACE/THE_SERDES/serdes_1_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_DOWN_INTERFACE_2/gen_pcs2.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; + + +FREQUENCY NET "clk_tx_full*" 200 MHz; +FREQUENCY NET "clk_rx_full*" 200 MHz; +FREQUENCY NET "clk_tx_full[0]_45649_CH0_FF_TXI_CLK" 200 MHz; +FREQUENCY NET "clk_tx_full[1]_45664_CH1_FF_TXI_CLK" 200 MHz; +FREQUENCY NET "clk_rx_full[0]_45645_CH0_FF_RXI_CLK" 200 MHz; +FREQUENCY NET "clk_rx_full[1]_45657_CH1_FF_RXI_CLK" 200 MHz; +FREQUENCY NET "THE_DOWN_INTERFACE_2/clk_rx_full" 200 MHz; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 20 ns; +MULTICYCLE TO CELL "THE_DOWN_INTERFACE_2/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 20 ns; +MULTICYCLE TO CELL "THE_DOWN_INTERFACE_2/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 20 ns; + +REGION "MEDIA_LEFT" "R42C16D" 28 40; +REGION "MEDIA_RIGHT" "R42C58D" 28 30; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_LEFT" ; +LOCATE UGROUP "THE_DOWN_INTERFACE_2/media_interface_group" REGION "MEDIA_RIGHT" ; diff --git a/OEP/mdcoep.prj b/OEP/mdcoep.prj new file mode 100644 index 0000000..bab32a0 --- /dev/null +++ b/OEP/mdcoep.prj @@ -0,0 +1,220 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_45F +set_option -package BG381C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "mdcoep" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/mdcoep.edf" +set_option log_file "workdir/mdcoep.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_2.vhd" +#add_file -vhdl -lib work "project/oepserdes/oepserdes.vhd" +#add_file -vhdl -lib work "project/oepserdes/pcs/pcs.vhd" +#add_file -vhdl -lib work "project/oepserdes/pcs1/pcs1.vhd" +#add_file -vhdl -lib work "project/oepserdes/pcs2/pcs2.vhd" +#add_file -vhdl -lib work "project/oepserdes/pcs3/pcs3.vhd" + + +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_1.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan1_0/serdes_sync_2.vhd" + +add_file -vhdl -lib work "./project/dual_serdes/dual_serdes.vhd" +add_file -vhdl -lib work "./project/dual_serdes/serdes0/serdes0.vhd" +add_file -vhdl -lib work "./project/dual_serdes/serdes1/serdes1.vhd" +add_file -verilog -lib work "./project/dual_serdes/serdes0/serdes0_softlogic.v" +add_file -verilog -lib work "./project/dual_serdes/serdes1/serdes1_softlogic.v" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs1.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + + +add_file -vhdl -lib work "./mdcoep.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/OEP/mdcoep.vhd b/OEP/mdcoep.vhd new file mode 100644 index 0000000..2db9887 --- /dev/null +++ b/OEP/mdcoep.vhd @@ -0,0 +1,446 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; +use work.trb_net16_hub_func.all; + +entity mdcoep is + port( + CLK : in std_logic; + TRG : in std_logic; + + GPIO : inout std_logic_vector(11 downto 0); --0: Serdes in, 1: Serdes out, 2,3: trigger input 0+1 + LVDS : out std_logic_vector(5 downto 0); + + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + FLASH_SELECT : in std_logic; + FLASH_OVERRIDE : out std_logic; + PROGRAMN : out std_logic; + + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + SFP_MOD0 : in std_logic; + + ADC_MISO : in std_logic; + ADC_MOSI : out std_logic; + ADC_SCK : out std_logic; + ADC_CS : out std_logic; + + --LED + LED : out std_logic_vector(7 downto 0) + + --Other Connectors + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of mdcoep is + constant INTERFACE_NUM : integer := 3; + + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + --Media Interface + signal med2int : med2int_array_t(0 to INTERFACE_NUM-1); + signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal additional_reg : std_logic_vector ( 31 downto 0); + + signal med_dataready_out : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_data_out : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_dataready_in : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_data_in : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal rdack, wrack : std_logic; + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bussci2_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bussci2_rx, bustools_rx, bustc_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal bus_master_active : std_logic; + + signal timer : TIMERS; + signal led_off : std_logic; + + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_2 + generic map( + + IS_SYNC_SLAVE => (c_YES,c_NO) + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0 to 1), + MEDIA_INT2MED => int2med(0 to 1), + + --Sync operation +-- RX_DLM => open, +-- RX_DLM_WORD => open, +-- TX_DLM => open, +-- TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => SFP_MOD0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, + SD_PRSNT_N_IN(1) => GPIO(1), + SD_LOS_IN(1) => GPIO(1), + SD_TXDIS_OUT(1) => GPIO(0), + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx + -- Status and control port +-- STAT_DEBUG => open, --med_stat_debug(63 downto 0), +-- CTRL_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Second TrbNet Downlink +--------------------------------------------------------------------------- + THE_DOWN_INTERFACE_2 : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 2, + IS_SYNC_SLAVE => c_NO + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(2), + MEDIA_INT2MED => int2med(2), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => GPIO(5), + SD_LOS_IN => GPIO(5), + SD_TXDIS_OUT => GPIO(4), + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +-- THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record +-- generic map ( +-- ADDRESS_MASK => x"FFFF", +-- BROADCAST_BITMASK => x"FF", +-- REGIO_INIT_ENDPOINT_ID => x"0001", +-- REGIO_USE_1WIRE_INTERFACE => c_I2C, +-- TIMING_TRIGGER_RAW => c_YES, +-- --Configure data handler +-- DATA_INTERFACE_NUMBER => 1, +-- DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, +-- DATA_BUFFER_WIDTH => 32, +-- DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, +-- TRG_RELEASE_AFTER_DATA => c_YES, +-- HEADER_BUFFER_DEPTH => 9, +-- HEADER_BUFFER_FULL_THRESH => 2**9-16 +-- ) +-- +-- port map( +-- -- Misc +-- CLK => clk_sys, +-- RESET => reset_i, +-- CLK_EN => '1', +-- +-- -- Media direction port +-- MEDIA_MED2INT => med2int(0), +-- MEDIA_INT2MED => int2med(0), +-- +-- --Timing trigger in +-- TRG_TIMING_TRG_RECEIVED_IN => TRG, +-- +-- READOUT_RX => readout_rx, +-- READOUT_TX => readout_tx, +-- +-- --Slow Control Port +-- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 +-- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 +-- BUS_RX => ctrlbus_rx, +-- BUS_TX => ctrlbus_tx, +-- BUS_MASTER_IN => bus_master_in, +-- BUS_MASTER_OUT => bus_master_out, +-- BUS_MASTER_ACTIVE => bus_master_active, +-- +-- ONEWIRE_INOUT => open, +-- I2C_SCL => I2C_SCL, +-- I2C_SDA => I2C_SDA, +-- --Timing registers +-- TIMERS_OUT => timer +-- ); +-- +-- + + THE_HUB : entity work.trb_net16_hub_base + generic map( + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + MII_IS_DOWNLINK => (0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0), + MII_IS_UPLINK_ONLY => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + USE_ONEWIRE => c_I2C, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), + + COMMON_STAT_REGS => common_stat_reg, + COMMON_CTRL_REGS => common_ctrl_reg, + MY_ADDRESS_OUT => open, + --REGIO INTERFACE + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + ONEWIRE => open, + ONEWIRE_MONITOR_OUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open + ); + + gen_media_record : for i in 0 to INTERFACE_NUM-1 generate + med_data_in(i*16+15 downto i*16) <= med2int(i).data; + med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; + med_dataready_in(i) <= med2int(i).dataready; + med_read_in(i) <= med2int(i).tx_read; + med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op; + + int2med(i).data <= med_data_out(i*16+15 downto i*16); + int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); + int2med(i).dataready <= med_dataready_out(i); + int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); + end generate; + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"c000", 3 => x"b200", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 12, 3 => 9, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustdc_rx, --Clock switch + BUS_RX(3) => bussci2_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustdc_tx, + BUS_TX(3) => bussci2_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => open, + SPI_MOSI_OUT => open, + SPI_MISO_IN => open, + SPI_CLK_OUT => open, + --Header + HEADER_IO => open, + ADDITIONAL_REG => additional_reg, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCK, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i, + TRIG_GEN_INPUTS => trigger_inputs_i, + TRIG_GEN_OUTPUTS(1 downto 0) => open, --GPIO(3 downto 2), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + led_off <= additional_reg(0); + FLASH_OVERRIDE <= not additional_reg(1); + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED(0) <= (med2int(0).stat_op(10) or med2int(0).stat_op(11)) and not led_off; + LED(1) <= med2int(0).stat_op(9) and not led_off; + LED(2) <= FLASH_SELECT and not led_off; + + LED(3) <= (med2int(1).stat_op(10) or med2int(1).stat_op(11)) and not led_off; + LED(4) <= med2int(1).stat_op(9) and not led_off; + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +end architecture; + + + diff --git a/OEP/par.p2t b/OEP/par.p2t new file mode 100644 index 0000000..9e4ef4d --- /dev/null +++ b/OEP/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 2 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/pinout/oep.lpf b/pinout/oep.lpf index 9dad896..09cb07c 100644 --- a/pinout/oep.lpf +++ b/pinout/oep.lpf @@ -10,8 +10,8 @@ BLOCK PATH TO PORT "PROGRAMN"; LOCATE COMP "CLK" SITE "A4"; LOCATE COMP "TRG" SITE "B5"; -IOBUF PORT "CLK" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "TRG" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "CLK" IO_TYPE=LVDS DIFFRESISTOR=100; +IOBUF PORT "TRG" IO_TYPE=LVDS DIFFRESISTOR=100; LOCATE COMP "GPIO_0" SITE "L2"; LOCATE COMP "GPIO_1" SITE "L3"; @@ -42,14 +42,14 @@ LOCATE COMP "FLASH_HOLD" SITE "W1"; LOCATE COMP "FLASH_MISO" SITE "V2"; LOCATE COMP "FLASH_MOSI" SITE "W2"; LOCATE COMP "FLASH_OVERRIDE" SITE "U1"; -LOCATE COMP "FLASH_SCLK" SITE "U3"; +LOCATE COMP "FLASH_SCLK" SITE "U2"; LOCATE COMP "FLASH_SELECT" SITE "T1"; LOCATE COMP "FLASH_WP" SITE "Y2"; DEFINE PORT GROUP "FLASH_group" "FLASH*"; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -LOCATE COMP "FPGA_REPROGRAM" SITE "V1"; -IOBUF PORT "FPGA_REPROGRAM" IO_TYPE=LVCMOS25 ; +LOCATE COMP "PROGRAMN" SITE "V1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 ; LOCATE COMP "I2C_SCL" SITE "A14"; @@ -68,7 +68,33 @@ LOCATE COMP "LED_7" SITE "K20"; DEFINE PORT GROUP "LED_group" "LED*"; IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 ; +LOCATE COMP "TEST_1" SITE "U19"; +LOCATE COMP "TEST_2" SITE "N20"; +LOCATE COMP "TEST_3" SITE "U20"; +LOCATE COMP "TEST_4" SITE "M20"; +LOCATE COMP "TEST_5" SITE "T20"; +LOCATE COMP "TEST_6" SITE "L20"; +LOCATE COMP "TEST_7" SITE "R20"; +LOCATE COMP "TEST_8" SITE "P20"; +DEFINE PORT GROUP "TEST_group" "TEST*"; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 ; + + LOCATE COMP "TMP_ALERT" SITE "A12"; -IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +LOCATE COMP "SFP_LOS" SITE "A7"; +LOCATE COMP "SFP_TX_DIS" SITE "A8"; +LOCATE COMP "SFP_MOD0" SITE "B9"; +DEFINE PORT GROUP "SFP_group" "SFP*"; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "ADC_MISO" SITE "A17"; +LOCATE COMP "ADC_MOSI" SITE "A18"; +LOCATE COMP "ADC_SCK" SITE "A19"; +LOCATE COMP "ADC_CS" SITE "B20"; +DEFINE PORT GROUP "ADC_group" "ADC*"; +IOBUF GROUP "ADC_group" IO_TYPE=LVCMOS25 ; -- 2.43.0