From 112cdeb9719074fdd2ec3f4f20d46b31dbc5e76c Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 21 Dec 2021 13:43:02 +0100 Subject: [PATCH] reset issues to be handled --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 75 +++++++++++-------- media_interfaces/sync/main_rx_reset_RS.vhd | 2 +- media_interfaces/sync/med_sync_control_RS.vhd | 30 ++++++-- media_interfaces/sync/rx_control_RS.vhd | 6 +- media_interfaces/sync/tx_control_RS.vhd | 6 +- 5 files changed, 77 insertions(+), 42 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 7e6ec38..b4d30b4 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -37,8 +37,10 @@ entity med_ecp3_sfp_sync_all_RS is WORD_SYNC_OUT : out std_logic; -- byte alignment for DLM/RST forwarding (from slave port) MASTER_CLK_IN : in std_logic; -- recovered RX clock in (only master ports in quad) MASTER_CLK_OUT : out std_logic; -- recovered RX clock out (slave port in quad) - GLOBAL_RESET_IN : in std_logic; -- needed for MI with master port(s) only + QUAD_RST_IN : in std_logic; -- HANDLE WITH CARE GLOBAL_RESET_OUT : out std_logic; -- only available on MI with slave port + SLAVE_ACTIVE_OUT : out std_logic; -- for delaying MPs in hub + SLAVE_ACTIVE_IN : in std_logic; -- set to '1' on normal endpoints TX_PLL_LOL_IN : in std_logic; -- and'ed TX PLL LOL to sync startup TX_PLL_LOL_OUT : out std_logic; -- status signal of TX PLL TX_CLK_AVAIL_OUT : out std_logic; -- stable RX recovered clock available @@ -99,7 +101,6 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal sci_write_i : std_logic; signal wa_position_i : std_logic_vector(15 downto 0) := x"FFFF"; - signal wa_read_i : std_logic; signal stat_rx_control_i : std_logic_vector(4*32-1 downto 0); signal stat_tx_control_i : std_logic_vector(4*32-1 downto 0); @@ -134,7 +135,9 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal word_sync_i : std_logic_vector(3 downto 0); signal word_sync_sel : std_logic; - + + signal link_active_i : std_logic_vector(3 downto 0); + signal quad_mode : integer range 0 to 100; begin @@ -161,21 +164,21 @@ begin ------------------------------------------------- -- BUG: link_tx_ready(i) for master ports to be included -- BUG: slave ports need also disable with link_tx_ready(i) - SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) when IS_MODE(3) = c_IS_MASTER else - not link_rx_ready_i(3) when IS_MODE(3) = c_IS_SLAVE else - '1' when IS_MODE(3) = c_IS_UNUSED else + SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) or (not SLAVE_ACTIVE_IN) when IS_MODE(3) = c_IS_MASTER else + not link_rx_ready_i(3) when IS_MODE(3) = c_IS_SLAVE else + '1' when IS_MODE(3) = c_IS_UNUSED else '0'; - SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) when IS_MODE(2) = c_IS_MASTER else - not link_rx_ready_i(2) when IS_MODE(2) = c_IS_SLAVE else - '1' when IS_MODE(2) = c_IS_UNUSED else + SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) or (not SLAVE_ACTIVE_IN) when IS_MODE(2) = c_IS_MASTER else + not link_rx_ready_i(2) when IS_MODE(2) = c_IS_SLAVE else + '1' when IS_MODE(2) = c_IS_UNUSED else '0'; - SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) when IS_MODE(1) = c_IS_MASTER else - not link_rx_ready_i(1) when IS_MODE(1) = c_IS_SLAVE else - '1' when IS_MODE(1) = c_IS_UNUSED else + SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) or (not SLAVE_ACTIVE_IN) when IS_MODE(1) = c_IS_MASTER else + not link_rx_ready_i(1) when IS_MODE(1) = c_IS_SLAVE else + '1' when IS_MODE(1) = c_IS_UNUSED else '0'; - SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) when IS_MODE(0) = c_IS_MASTER else - not link_rx_ready_i(0) when IS_MODE(0) = c_IS_SLAVE else - '1' when IS_MODE(0) = c_IS_UNUSED else + SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) or (not SLAVE_ACTIVE_IN) when IS_MODE(0) = c_IS_MASTER else + not link_rx_ready_i(0) when IS_MODE(0) = c_IS_SLAVE else + '1' when IS_MODE(0) = c_IS_UNUSED else '0'; ------------------------------------------------- @@ -201,8 +204,8 @@ begin global_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else global_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE '0'; - -------------------------------------------------- + +------------------------------------------------- -- stable RX recovered clock available ------------------------------------------------- tx_clk_avail_sel <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else @@ -213,6 +216,15 @@ begin TX_CLK_AVAIL_OUT <= tx_clk_avail_sel; +------------------------------------------------- +-- +------------------------------------------------- + SLAVE_ACTIVE_OUT <= link_active_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + link_active_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + link_active_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + link_active_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + '0'; + ------------------------------------------------- -- byte/word alignment ------------------------------------------------- @@ -278,10 +290,10 @@ begin rx_serdes_rst_ch0_c => rx_serdes_rst(0), sb_felb_ch0_c => '0', sb_felb_rst_ch0_c => '0', - tx_pcs_rst_ch0_c => tx_pcs_rst(0), -- was wrong - tx_pwrup_ch0_c => powerup_ch(0), -- new + tx_pcs_rst_ch0_c => tx_pcs_rst(0), + tx_pwrup_ch0_c => powerup_ch(0), rx_pcs_rst_ch0_c => rx_pcs_rst(0), - rx_pwrup_ch0_c => powerup_ch(0), -- new + rx_pwrup_ch0_c => powerup_ch(0), rx_los_low_ch0_s => rx_los_low(0), lsm_status_ch0_s => lsm_status(0), rx_cdr_lol_ch0_s => rx_cdr_lol(0), @@ -309,10 +321,10 @@ begin rx_serdes_rst_ch1_c => rx_serdes_rst(1), sb_felb_ch1_c => '0', sb_felb_rst_ch1_c => '0', - tx_pcs_rst_ch1_c => tx_pcs_rst(1), -- was wrong - tx_pwrup_ch1_c => powerup_ch(1), -- new + tx_pcs_rst_ch1_c => tx_pcs_rst(1), + tx_pwrup_ch1_c => powerup_ch(1), rx_pcs_rst_ch1_c => rx_pcs_rst(1), - rx_pwrup_ch1_c => powerup_ch(1), -- new + rx_pwrup_ch1_c => powerup_ch(1), rx_los_low_ch1_s => rx_los_low(1), lsm_status_ch1_s => lsm_status(1), rx_cdr_lol_ch1_s => rx_cdr_lol(1), @@ -340,10 +352,10 @@ begin rx_serdes_rst_ch2_c => rx_serdes_rst(2), sb_felb_ch2_c => '0', sb_felb_rst_ch2_c => '0', - tx_pcs_rst_ch2_c => tx_pcs_rst(2), -- was wrong - tx_pwrup_ch2_c => powerup_ch(2), -- new + tx_pcs_rst_ch2_c => tx_pcs_rst(2), + tx_pwrup_ch2_c => powerup_ch(2), rx_pcs_rst_ch2_c => rx_pcs_rst(2), - rx_pwrup_ch2_c => powerup_ch(2), -- new + rx_pwrup_ch2_c => powerup_ch(2), rx_los_low_ch2_s => rx_los_low(2), lsm_status_ch2_s => lsm_status(2), rx_cdr_lol_ch2_s => rx_cdr_lol(2), @@ -371,10 +383,10 @@ begin rx_serdes_rst_ch3_c => rx_serdes_rst(3), sb_felb_ch3_c => '0', sb_felb_rst_ch3_c => '0', - tx_pcs_rst_ch3_c => tx_pcs_rst(3), -- was wrong - tx_pwrup_ch3_c => powerup_ch(3), -- new + tx_pcs_rst_ch3_c => tx_pcs_rst(3), + tx_pwrup_ch3_c => powerup_ch(3), rx_pcs_rst_ch3_c => rx_pcs_rst(3), - rx_pwrup_ch3_c => powerup_ch(3), -- new + rx_pwrup_ch3_c => powerup_ch(3), rx_los_low_ch3_s => rx_los_low(3), lsm_status_ch3_s => lsm_status(3), rx_cdr_lol_ch3_s => rx_cdr_lol(3), @@ -395,7 +407,7 @@ begin fpga_txrefclk => MASTER_CLK_IN, -- reference TX clock tx_serdes_rst_c => '0', tx_pll_lol_qd_s => TX_PLL_LOL_OUT, - rst_qd_c => GLOBAL_RESET_IN, + rst_qd_c => QUAD_RST_IN, serdes_rst_qd_c => '0', -- was wrong tx_sync_qd_c => SYNC_TX_PLL_IN ); @@ -442,6 +454,7 @@ gen_control : for i in 0 to 3 generate GLOBAL_RESET_OUT => global_reset_i(i), LINK_TX_READY_IN => LINK_TX_READY_IN, LINK_RX_READY_OUT => link_rx_ready_i(i), + LINK_ACTIVE_OUT => link_active_i(i), -- komma operation TX_DLM_IN => TX_DLM_IN, TX_DLM_WORD_IN => TX_DLM_WORD_IN, @@ -488,7 +501,7 @@ end generate; SCI_WR => sci_write_i, -- WAP WA_POS_OUT => wa_position_i, - WA_READ_OUT => wa_read_i, --open, + WA_READ_OUT => open, LINK_RX_READY_IN => '0', -- NOT REALLY NEEDED --Slowcontrol BUS_RX => BUS_RX, diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index 2626171..fd59d8d 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -202,7 +202,7 @@ begin RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '1'; cnt <= (others => '0'); - if( (lsm_s = '0') or (cv_s = '1') ) then + if( (lsm_s = '0') or (cv_s = '1') ) then -- DANGEROUS rx_sm <= APPLY_RXPCS_RST; end if; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index e919c47..5504afb 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -47,6 +47,7 @@ entity med_sync_control_RS is GLOBAL_RESET_OUT : out std_logic; -- global reset from slave port LINK_TX_READY_IN : in std_logic; -- LINK_RX_READY_OUT : out std_logic; -- + LINK_ACTIVE_OUT : out std_logic; -- -- komma handling TX_DLM_IN : in std_logic; -- transmit one DLM komma TX_DLM_WORD_IN : in std_logic_vector(7 downto 0); @@ -100,6 +101,8 @@ architecture med_sync_control_arch of med_sync_control_RS is signal link_tx_ready_qsys : std_logic; signal link_status : std_logic_vector(3 downto 0); signal link_status_qsys : std_logic_vector(3 downto 0); + signal link_active_i : std_logic; + signal link_active_qref : std_logic; -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; @@ -160,7 +163,7 @@ begin CV_IN => RX_CV_IN, LSM_IN => RX_LSM_IN, LOS_IN => RX_LOS_IN, - SD_LOS_IN => SFP_LOS_IN, + SD_LOS_IN => SFP_LOS_IN, -- could be "sd_los_q" (already sync'ed) WAP_ZERO_IN => is_wap_zero_i, -- outputs RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based @@ -281,7 +284,6 @@ begin led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS); - -- REMARK: RESET or reset_i? ROC_TIMER_PROC: process( CLK_SYS, RESET ) begin if ( RESET = '1' ) then @@ -313,10 +315,11 @@ begin media_med2int_i.stat_op(5) <= link_full_done_qsys; -- tx_allow media_med2int_i.stat_op(4) <= link_full_done_qsys; -- rx_allow media_med2int_i.stat_op(3 downto 0) <= link_status_qsys; - - link_status <= x"0" when ((link_half_done_i = '1') and (link_full_done_i = '1')) - else x"7"; - + + link_active_i <= link_rx_ready_i and link_tx_ready_i and link_half_done_i and link_full_done_i; + + link_status <= x"0" when (link_active_i = '1' ) else x"7"; + SYNC_MEDIA_SIGS : entity work.signal_sync generic map( WIDTH => 8, @@ -338,6 +341,21 @@ begin D_OUT(3 downto 0) => link_status_qsys ); + SYNC_LA_SIGS : entity work.signal_sync + generic map( + WIDTH => 1, + DEPTH => 3 + ) + port map( + RESET => '0', + CLK0 => CLK_REF, + CLK1 => CLK_REF, + D_IN(0) => link_active_i, + D_OUT(0) => link_active_qref + ); + + LINK_ACTIVE_OUT <= link_active_qref; + -- TEST_LINE signals DEBUG_OUT(31 downto 12) <= (others => '0'); DEBUG_OUT(11) <= link_full_done_qsys; diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 9237d4d..d703609 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -196,7 +196,8 @@ begin rst_idle0_ctr <= '1'; rst_idle1_ctr <= '1'; rst_link_state <= '1'; - if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then +-- if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then + if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) and (link_rx_ready_qrx = '1') ) then rx_state <= WAIT_1; sync_k_i <= '1'; end if; @@ -272,7 +273,8 @@ begin end case; - if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then +-- if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then + if( (RESET = '1') ) then rx_state <= SLEEP; rx_dlm_word_i <= x"00"; rx_rst_word_i <= x"00"; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index e20c766..6bf40e5 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -337,8 +337,10 @@ begin if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H) ) then - if ( link_active_qtx = '0' ) then - current_state <= SEND_IDLE_L; +-- if ( link_active_qtx = '0' ) then +-- current_state <= SEND_IDLE_L; + if ( link_tx_ready_qtx = '0' ) then + current_state <= IDLE; -- stay in reset until TX is possible elsif( send_dlm_i = '1' ) then current_state <= SEND_DLM_L; elsif( send_rst_i = '1' ) then -- 2.43.0