From 118108e0eca94a02d5a5a352f06e2e6248a52959 Mon Sep 17 00:00:00 2001
From: Tobias Weber <toweber86@gmail.com>
Date: Tue, 17 Jul 2018 10:15:13 +0200
Subject: [PATCH] test bench for link simulation.

---
 mupix/Mupix8/tb/LinkSimulationTest.vhd | 73 ++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 mupix/Mupix8/tb/LinkSimulationTest.vhd

diff --git a/mupix/Mupix8/tb/LinkSimulationTest.vhd b/mupix/Mupix8/tb/LinkSimulationTest.vhd
new file mode 100644
index 0000000..ed01e8e
--- /dev/null
+++ b/mupix/Mupix8/tb/LinkSimulationTest.vhd
@@ -0,0 +1,73 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity LinkSimulationTest is
+end entity LinkSimulationTest;
+
+architecture sim of LinkSimulationTest is
+
+  component LinkSimulation is
+    port (
+      trbclk   : in  std_logic;
+      sendclk  : in  std_logic;
+      reset    : in  std_logic;
+      data_out : out std_logic;
+      dataclk  : out std_logic);
+  end component LinkSimulation;
+
+  constant trbclk_period : time := 10 ns;
+  constant sendclk_period : time := 5 ns;
+  
+  signal trbclk   : std_logic;
+  signal sendclk  : std_logic;
+  signal reset    : std_logic := '1';
+  signal data_out : std_logic;
+  signal dataclk  : std_logic;
+
+  signal data_rev : std_logic_vector(9 downto 0);
+  
+begin  -- architecture sim
+
+  LinkSimulation_1: entity work.LinkSimulation
+    port map (
+      trbclk   => trbclk,
+      sendclk  => sendclk,
+      reset    => reset,
+      data_out => data_out,
+      dataclk  => dataclk);
+
+  trbclk_gen: process is
+  begin  -- process trbclk_gen
+    trbclk <= '1';
+    wait for trbclk_period/2;
+    trbclk <= '0';
+    wait for trbclk_period/2;
+  end process trbclk_gen;
+
+  sendclk_gen: process is
+  begin  -- process sendclk_gen
+    sendclk <= '1';
+    wait for sendclk_period/2;
+    sendclk <= '0';
+    wait for sendclk_period/2;
+  end process sendclk_gen;
+
+  receive: process (sendclk) is
+  begin  -- process receive
+    if rising_edge(sendclk) then        -- rising clock edge
+      data_rev <= data_rev(8 downto 0) & data_out;
+    end if;
+    if falling_edge(sendclk) then        -- falling clock edge
+      data_rev <= data_rev(8 downto 0) & data_out;
+    end if;
+  end process receive;
+
+  stim: process is
+  begin  -- process stim
+    wait for 100 ns;
+    reset <= '0';
+    wait;
+  end process stim;
+  
+end architecture sim;
-- 
2.43.0