From 11c9663bd85ba15e369b0dbb468482871a2990d2 Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Thu, 16 Jan 2014 16:27:47 +0100
Subject: [PATCH] added new control reg for SPI fifo

---
 xml-db/database/CbController.xml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/xml-db/database/CbController.xml b/xml-db/database/CbController.xml
index 060ede8..f88ad52 100644
--- a/xml-db/database/CbController.xml
+++ b/xml-db/database/CbController.xml
@@ -94,6 +94,12 @@
               start="0" bits="32"  mode="r"  purpose="status"  format="integer" rate="1">
       </field>
     </register>
+    <register  name="SpiFifoSelect"
+              address="0053" purpose="config" mode="rw" >
+      <description>Select a SPI channel to monitor in the Fifo</description>
+      <field name="SpiFifoSelect" start="0" bits="8" format="hex" >
+      </field>
+    </register>
     <register  name="UcReset"
               address="0060" purpose="config" mode="rw" >
       <description>Brings the uC to reset, when set Lo.</description>
-- 
2.43.0