From 1257ecee407e4b0e5ba3807d96aee8baef989c12 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 31 Mar 2010 15:37:46 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/fifo/fifo_var_oreg.vhd | 182 ++++++++++++++ lattice/ecp2m/lattice_ecp2m_fifo.vhd | 172 ++++++++++++++ special/handler_data.vhd | 277 +++++++++++++++++++++- special/handler_ipu.vhd | 11 +- special/handler_trigger_and_data.vhd | 19 +- trb_net16_endpoint_hades_full_handler.vhd | 73 +++--- trb_net_components.vhd | 271 +++++++++++++++++++++ 7 files changed, 940 insertions(+), 65 deletions(-) create mode 100644 lattice/ecp2m/fifo/fifo_var_oreg.vhd create mode 100644 lattice/ecp2m/lattice_ecp2m_fifo.vhd diff --git a/lattice/ecp2m/fifo/fifo_var_oreg.vhd b/lattice/ecp2m/fifo/fifo_var_oreg.vhd new file mode 100644 index 0000000..685861b --- /dev/null +++ b/lattice/ecp2m/fifo/fifo_var_oreg.vhd @@ -0,0 +1,182 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.lattice_ecp2m_fifo.all; + +entity fifo_var_oreg is + generic( + FIFO_WIDTH : integer range 1 to 64 := 36; + FIFO_DEPTH : integer range 1 to 16 := 8 + ); + port( + Data : in std_logic_vector(FIFO_WIDTH-1 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0); + Q : out std_logic_vector(FIFO_WIDTH-1 downto 0); + WCNT : out std_logic_vector(FIFO_DEPTH downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity; + +architecture fifo_var_oreg_arch of fifo_var_oreg is + +begin + + assert FIFO_WIDTH=36 report "Selected data buffer size not implemented" severity error; + assert (FIFO_DEPTH >= 8) and (FIFO_DEPTH <= 15) report "Selected data buffer size not implemented" severity error; + + gen_36_256 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 8 generate + THE_FIFO : fifo_36x256_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + gen_36_512 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 9 generate + THE_FIFO : fifo_36x512_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + gen_36_1k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 10 generate + THE_FIFO : fifo_36x1k_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + gen_36_2k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 11 generate + THE_FIFO : fifo_36x2k_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + gen_36_4k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 12 generate + THE_FIFO : fifo_36x4k_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + gen_36_8k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 13 generate + THE_FIFO : fifo_36x8k_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + gen_36_16k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 14 generate + THE_FIFO : fifo_36x16k_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + gen_36_32k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 15 generate + THE_FIFO : fifo_36x32k_oreg + port map( + Data => Data, + Clock => Clock, + WrEn => WrEn, + RdEn => RdEn, + Reset => Reset, + AmFullThresh => AmFullThresh, + Q => Q, + WCNT => WCNT, + Empty => Empty, + Full => Full, + AlmostFull => AlmostFull + ); + end generate; + + + + +end architecture; \ No newline at end of file diff --git a/lattice/ecp2m/lattice_ecp2m_fifo.vhd b/lattice/ecp2m/lattice_ecp2m_fifo.vhd new file mode 100644 index 0000000..2061203 --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo.vhd @@ -0,0 +1,172 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + +package lattice_ecp2m_fifo is + + component fifo_var_oreg is + generic( + FIFO_WIDTH : integer range 1 to 64 := 36; + FIFO_DEPTH : integer range 1 to 16 := 8 + ); + port( + Data : in std_logic_vector(FIFO_WIDTH-1 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0); + Q : out std_logic_vector(FIFO_WIDTH-1 downto 0); + WCNT : out std_logic_vector(FIFO_DEPTH downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + component fifo_36x256_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_36x512_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(8 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_36x1k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(9 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(10 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_36x2k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(10 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(11 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_36x4k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(11 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(12 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_36x8k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(12 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(13 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_36x16k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(12 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(13 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + component fifo_36x32k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(13 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(14 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + +end package; \ No newline at end of file diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 6b93a3d..0d1e4e2 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -5,23 +5,25 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; +use work.lattice_ecp2m_fifo.all; entity handler_data is generic( DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + DATA_BUFFER_DEPTH : integer range 8 to 15 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 31; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**8; TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; - HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + HEADER_BUFFER_DEPTH : integer range 8 to 15 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**8 ); port( CLOCK : in std_logic; RESET : in std_logic; --LVL1 Handler - LVL1_TRG_RECEIVED_IN : in std_logic; --TRG Info valid & FEE busy + LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts + LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); @@ -46,6 +48,10 @@ entity handler_data is IPU_HDR_DATA_READ_IN : in std_logic; IPU_HDR_DATA_EMPTY_OUT : out std_logic; + --Status + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); + --Debug DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -54,21 +60,272 @@ end entity; --------------------------------------------------------------------------- -- LVL1 Info FiFo ---------------------------------------------------------------------------- -- 15 - 0 : trigger number -- 23 - 16 : trigger code -- 27 - 24 : trigger type ---Fifo has an internal output register. Output is valid two clock cycles after read +-- Fifo has an internal output register. +-- Output is valid two clock cycles after read ---------------------------------------------------------------------------- -- Data FiFo ---------------------------------------------------------------------------- -- 31 - 0 : FEE data -- 35 - 32 : trigger number 3..0 +-- Fifo has an internal output register. +-- Output is valid two clock cycles after read + +-- Status Buffer Level +-- 15 - 0 : fill level +-- 16 : fifo empty +-- 17 : fifo almost full +-- 18 : fifo full +-- 19 : fifo write +-- 20 : buffer idle +-- 21 : buffer busy +-- 22 : buffer waiting +--------------------------------------------------------------------------- architecture handler_data_arch of handler_data is + constant data_width : integer := DATA_BUFFER_WIDTH + 4; + type buffer_state_t is (IDLE, BUSY, WAITING); + type lvl1_state_t is (IDLE, WAIT_BUSY, BUSY_RELEASE); + type cnt16_DAT_t is array (DATA_INTERFACE_NUMBER-1 downto 0) of unsigned(15 downto 0); + type bits3_t is array (DATA_INTERFACE_NUMBER-1 downto 0) of std_logic_vector(2 downto 0); + type buffer_state_arr_t is array (DATA_INTERFACE_NUMBER-1 downto 0) of buffer_state_t; + + + signal data_buffer_data_in : std_logic_vector(DATA_INTERFACE_NUMBER*data_width-1 downto 0); + signal data_buffer_data_out : std_logic_vector(DATA_INTERFACE_NUMBER*data_width-1 downto 0); + signal data_buffer_filllevel : std_logic_vector(DATA_INTERFACE_NUMBER*(DATA_BUFFER_DEPTH+1)-1 downto 0); + signal data_buffer_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal data_buffer_empty : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal data_buffer_almost_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + signal header_buffer_data_in : std_logic_vector(36-1 downto 0); + signal header_buffer_data_out : std_logic_vector(36-1 downto 0); + signal header_buffer_filllevel : std_logic_vector(DATA_BUFFER_DEPTH downto 0); + signal header_buffer_full : std_logic; + signal header_buffer_empty : std_logic; + signal header_buffer_almost_full : std_logic; + signal header_buffer_write : std_logic; + + signal lvl1_busy_release_i : std_logic; + signal lvl1_statusbits_i : std_logic_vector(31 downto 0); + + signal data_counter : cnt16_DAT_t; + signal buffer_state_bits : bits3_t; + signal lvl1_state_bits : std_logic_vector(2 downto 0); + + signal current_buffer_state : buffer_state_arr_t; + signal current_lvl1_state : lvl1_state_t; + + signal length_buffer_write : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + begin + assert DATA_BUFFER_FULL_THRESH < 2**DATA_BUFFER_DEPTH-2 report "Data buffer threshold too high" severity error; + assert HEADER_BUFFER_FULL_THRESH < 2**HEADER_BUFFER_DEPTH-2 report "Header buffer threshold too high" severity error; + +--------------------------------------------------------------------------- +-- FEE I/O +--------------------------------------------------------------------------- + FEE_DATA_ALMOST_FULL_OUT <= data_buffer_almost_full; + +--------------------------------------------------------------------------- +-- IPU I/O +--------------------------------------------------------------------------- + IPU_HDR_DATA_EMPTY_OUT <= header_buffer_empty; + IPU_HDR_DATA_OUT <= header_buffer_data_out; + + IPU_DATA_EMPTY_OUT <= data_buffer_empty; + + +--------------------------------------------------------------------------- +-- Generate Fifo I/O +--------------------------------------------------------------------------- + gen_fifo_io : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + + data_buffer_data_in((i+1)*data_width-1 downto i*data_width) + <= LVL1_TRG_NUMBER_IN(3 downto 0) & FEE_DATA_IN((i+1)*DATA_BUFFER_WIDTH-1 downto i*DATA_BUFFER_WIDTH); + + IPU_DATA_OUT(i*data_width+DATA_BUFFER_WIDTH-1 downto i*data_width) + <= data_buffer_data_out(i*data_width+DATA_BUFFER_WIDTH-1 downto i*data_width); + + IPU_DATA_FLAGS_OUT(i*4+3 downto i*4) + <= data_buffer_data_out((i+1)*data_width-1 downto (i+1)*data_width-4); + + end generate; + + header_buffer_data_in <= x"00" & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; + + +--------------------------------------------------------------------------- +-- Data Fifo(s) +--------------------------------------------------------------------------- + gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + THE_DAT_FIFO : fifo_var_oreg + generic map( + FIFO_WIDTH => DATA_BUFFER_WIDTH+4, + FIFO_DEPTH => DATA_BUFFER_DEPTH + ) + port map( + Data => data_buffer_data_in(i*36+35 downto i*36), + Clock => CLOCK, + WrEn => FEE_DATA_WRITE_IN(i), + RdEn => IPU_DATA_READ_IN(i), + Reset => RESET, + AmFullThresh => DATA_BUFFER_FULL_THRESH, + Q => data_buffer_data_out(i*36+35 downto i*36), + WCNT => data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)), + Empty => data_buffer_empty(i), + Full => data_buffer_full(i), + AlmostFull => data_buffer_almost_full(i) + ); + end generate; + + +--------------------------------------------------------------------------- +-- Header Fifo +--------------------------------------------------------------------------- + THE_HDR_FIFO : fifo_var_oreg + generic map( + FIFO_WIDTH => 36, + FIFO_DEPTH => HEADER_BUFFER_DEPTH + ) + port map( + Data => header_buffer_data_in, + Clock => CLOCK, + WrEn => header_buffer_write, + RdEn => IPU_HDR_DATA_READ_IN, + Reset => RESET, + AmFullThresh => HEADER_BUFFER_FULL_THRESH, + Q => header_buffer_data_out, + WCNT => header_buffer_filllevel, + Empty => header_buffer_empty, + Full => header_buffer_full, + AlmostFull => header_buffer_almost_full + ); + + +--------------------------------------------------------------------------- +-- Length FIFO +--------------------------------------------------------------------------- +-- THE_LENGTH_FIFO : + + +--------------------------------------------------------------------------- +-- Count Length +--------------------------------------------------------------------------- + gen_counter : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + proc_length_count : process (CLOCK) + begin + if rising_edge(CLOCK) then + if RESET = '1' then + current_buffer_state(i) <= IDLE; + else + length_buffer_write(i) <= '0'; + + case current_buffer_state(i) is + when IDLE => + buffer_state_bits(i) <= "001"; + data_counter(i) <= 0; + if LVL1_VALID_TRIGGER_IN = '1' then + current_buffer_state(i) <= BUSY; + end if; + + when BUSY => + buffer_state_bits(i) <= "100"; + if FEE_DATA_WRITE_IN(i) = '1' then + data_counter(i) <= data_counter(i) + to_unsigned(1,1); + elsif FEE_DATA_FINISHED_IN(i) = '1' then + current_buffer_state(i) <= WAITING; + length_buffer_write(i) <= '1'; + end if; + + when WAITING => + buffer_state_bits(i) <= "010"; + if lvl1_busy_release_i = '1' then + current_buffer_state(i) <= IDLE; + end if; + + end case; + end if; + end if; + end process; + end generate; + +--------------------------------------------------------------------------- +-- Busy Logic +--------------------------------------------------------------------------- + proc_busy_logic : process(CLOCK) + begin + if rising_edge(CLOCK) then + if RESET = '1' then + current_lvl1_state <= IDLE; + else + case current_lvl1_state is + when IDLE => + lvl1_state_bits <= "001"; + + when WAIT_BUSY => + lvl1_state_bits <= "010"; + + when BUSY_RELEASE => + lvl1_state_bits <= "100"; + + end case; + end if; + end if; + end process; + + +--------------------------------------------------------------------------- +-- Make Status Registers +--------------------------------------------------------------------------- + gen_buf_status : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + proc_data_buffer_stat : process(CLOCK) + begin + if rising_edge(CLOCK) then + STAT_DATA_BUFFER_LEVEL(i*32+31 downto i*32) + <= (others => '0'); + + STAT_DATA_BUFFER_LEVEL(i*32+DATA_BUFFER_DEPTH downto i*32) + <= data_buffer_filllevel((i+1)*(DATA_BUFFER_DEPTH+1)-1 downto i*(DATA_BUFFER_DEPTH+1)); + + STAT_DATA_BUFFER_LEVEL(i*32+18 downto i*32+16) + <= data_buffer_full(i) & data_buffer_almost_full(i) & data_buffer_empty(i); + + STAT_DATA_BUFFER_LEVEL(i*32+19) + <= FEE_DATA_WRITE_IN(i); + + STAT_DATA_BUFFER_LEVEL(i*32+22 downto i*32+20) + <= buffer_state_bits(i); + end if; + end process; + end generate; + + proc_header_buffer_stat : process(CLOCK) + begin + if rising_edge(CLOCK) then + STAT_HEADER_BUFFER_LEVEL(31 downto 0) + <= (others => '0'); + + STAT_HEADER_BUFFER_LEVEL(HEADER_BUFFER_DEPTH downto 0) + <= header_buffer_filllevel; + + STAT_HEADER_BUFFER_LEVEL(18 downto 16) + <= header_buffer_full & header_buffer_almost_full & header_buffer_empty; + + STAT_HEADER_BUFFER_LEVEL(19) + <= header_buffer_write; + + STAT_HEADER_BUFFER_LEVEL(22 downto 20) + <= lvl1_state_bits(i); + end if; + end process; + +--------------------------------------------------------------------------- +-- Debug +--------------------------------------------------------------------------- + end architecture; diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index b0f85e9..36ef167 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -24,6 +24,7 @@ entity handler_ipu is DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0); DAT_HDR_DATA_READ_OUT : out std_logic; @@ -207,7 +208,7 @@ begin begin if rising_edge(CLOCK) then if hdr_fifo_valid_read = '1' then - dat_fifo_read_length(i) <= unsigned(DAT_HDR_DATA_IN(i*18+9 downto i*18)); + dat_fifo_read_length(i) <= unsigned(DAT_DATA_LENGTH_IN(i*16+15 downto i*16)); elsif dat_fifo_read(i) = '1' then dat_fifo_read_length(i) <= dat_fifo_read_length(i) - to_unsigned(1,1); end if; @@ -285,7 +286,7 @@ begin next_total_length <= (((dat_fifo_read_length(0)) + (dat_fifo_read_length(1))) + ((dat_fifo_read_length(2)) + (dat_fifo_read_length(3)))) + (((dat_fifo_read_length(4)) + (dat_fifo_read_length(5))) + - ((dat_fifo_read_length(6))); + ((dat_fifo_read_length(6)))); end generate; @@ -299,7 +300,7 @@ begin if current_state = IDLE then error_sync <= '0'; elsif dat_fifo_valid_read = '1' then - for i in 0 to NUMBER_OF_ADC-1 loop + for i in 0 to DATA_INTERFACE_NUMBER-1 loop if DAT_HDR_DATA_IN(3 downto 0) /= DAT_DATA_FLAGS_IN(dat_fifo_number*4+3 downto dat_fifo_number*4+0) then error_sync <= '1'; end if; @@ -319,8 +320,8 @@ begin ipu_length_i <= std_logic_vector(total_length); - ADC_HDR_DATA_READ_OUT <= (others => hdr_fifo_read); - ADC_DATA_READ_OUT <= dat_fifo_read; + DAT_HDR_DATA_READ_OUT <= hdr_fifo_read; + DAT_DATA_READ_OUT <= dat_fifo_read; --------------------------------------------------------------------------- -- Error and Status Bits diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index fe5b35e..f755a97 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -109,7 +109,7 @@ begin variable tmp_statusbits : std_logic_vector(31 downto 0); begin if rising_edge(CLOCK) then - if RESET = '1' or LVL1_TRG_RECEIVED_IN = '0' then + if RESET = '1' or LVL1_VALID_TRIGGER_IN = '0' then fee_trg_statusbits <= (others => '0'); fee_trg_release <= '0'; else @@ -144,11 +144,12 @@ begin RESET => RESET, --From LVL1 Handler - LVL1_TRG_RECEIVED_IN => fee_trigger_received, - LVL1_TRG_TYPE_IN => fee_trg_type, - LVL1_TRG_INFO_IN => fee_trg_info, - LVL1_TRG_CODE_IN => fee_trg_code, - LVL1_TRG_NUMBER_IN => fee_trg_number, + LVL1_VALID_TRIGGER_IN => LVL1_VALID_TRIGGER_IN, + LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, + LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + LVL1_TRG_INFO_IN => LVL1_TRG_INFORMATION_IN, + LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, + LVL1_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, --internal number for flags LVL1_STATUSBITS_OUT => dat_lvl1_statusbits, LVL1_TRG_RELEASE_OUT => dat_lvl1_release, --From FEE @@ -213,12 +214,6 @@ begin LVL1_TRG_RELEASE_OUT <= fee_trg_release; LVL1_ERROR_PATTERN_OUT <= fee_trg_statusbits; - FEE_TIMING_TRIGGER_OUT <= LVL1_TIMING_TRG_IN; - FEE_TRG_NUMBER_OUT <= LVL1_TRG_NUMBER_IN; - FEE_TRG_RECEIVED_OUT <= LVL1_TRG_RECEIVED_IN; - FEE_TRG_TYPE_OUT <= LVL1_TRG_TYPE_IN; - FEE_TRG_INFO_OUT <= LVL1_TRG_INFORMATION_IN; - diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 32525b4..2f5c4cf 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -32,15 +32,11 @@ entity trb_net16_endpoint_hades_full_handler is --Configure data handler DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 31; DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; - TRG_RELEASE_AFTER_DATA_FINISH: integer range 0 to 1 := c_YES; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8; - --RegIO Bus Handler - PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 1; - PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); - PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8 ); port( @@ -95,16 +91,16 @@ entity trb_net16_endpoint_hades_full_handler is REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); --internal data port - BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); - BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); - BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_DATA_IN : in std_logic_vector(PORT_NUMBER*32-1 downto 0) := (others => '0'); - BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); - BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); - BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); - BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); + BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic; + BUS_WRITE_ENABLE_OUT : out std_logic; + BUS_TIMEOUT_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + BUS_DATAREADY_IN : in std_logic := '0'; + BUS_WRITE_ACK_IN : in std_logic := '0'; + BUS_NO_MORE_DATA_IN : in std_logic := '0'; + BUS_UNKNOWN_ADDR_IN : in std_logic := '0'; --Onewire ONEWIRE_INOUT : inout std_logic; --temperature sensor ONEWIRE_MONITOR_IN : in std_logic := '0'; @@ -138,6 +134,7 @@ end entity; architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_hades_full_handler is signal lvl1_data_valid_i : std_logic; + signal lvl1_valid_i : std_logic; signal lvl1_valid_timing_i : std_logic; signal lvl1_valid_notiming_i : std_logic; signal lvl1_invalid_i : std_logic; @@ -227,8 +224,8 @@ begin MED_DATA_IN => MED_DATA_IN, MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, MED_READ_OUT => MED_READ_OUT, - MED_STAT_OP_IN => MED_STAT_OP, - MED_CTRL_OP_OUT => MED_CTRL_OP, + MED_STAT_OP_IN => MED_STAT_OP_IN, + MED_CTRL_OP_OUT => MED_CTRL_OP_OUT, -- LVL1 trigger APL TRG_TIMING_TRG_RECEIVED_IN => TRG_TIMING_TRG_RECEIVED_IN, @@ -301,11 +298,11 @@ begin -- RegIO Bus Handler --------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler + THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => PORT_NUMBER, - PORT_ADDRESSES => PORT_ADDRESSES, - PORT_ADDR_MASK => PORT_ADDR_MASK + PORT_NUMBER => 1, + PORT_ADDRESSES => (0 => x"8000", others => x"0000"), + PORT_ADDR_MASK => (0 => 15, others => 0) ) port map( CLK => CLK, @@ -322,16 +319,16 @@ begin DAT_NO_MORE_DATA_OUT => regio_nomoredata_i, DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i, - BUS_READ_ENABLE_OUT => BUS_READ_ENABLE_OUT, - BUS_WRITE_ENABLE_OUT => BUS_WRITE_ENABLE_OUT, - BUS_DATA_OUT => BUS_DATA_OUT, - BUS_ADDR_OUT => BUS_ADDR_OUT, - BUS_TIMEOUT_OUT => BUS_TIMEOUT_OUT, - BUS_DATA_IN => BUS_DATA_IN, - BUS_DATAREADY_IN => BUS_DATAREADY_IN, - BUS_WRITE_ACK_IN => BUS_WRITE_ACK_IN, - BUS_NO_MORE_DATA_IN => BUS_NO_MORE_DATA_IN, - BUS_UNKNOWN_ADDR_IN => BUS_UNKNOWN_ADDR_IN + BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT, + BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT, + BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT, + BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT, + BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, + BUS_DATA_IN(31 downto 0) => BUS_DATA_IN, + BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN, + BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN, + BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN, + BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN ); --------------------------------------------------------------------------- @@ -346,10 +343,10 @@ begin DATA_BUFFER_FULL_THRESH => DATA_BUFFER_FULL_THRESH, TRG_RELEASE_AFTER_DATA => TRG_RELEASE_AFTER_DATA, HEADER_BUFFER_DEPTH => HEADER_BUFFER_DEPTH, - HEADER_BUFFER_FULL_THRESH => HEADER_BUFFER_FULL_THRESH, + HEADER_BUFFER_FULL_THRESH => HEADER_BUFFER_FULL_THRESH ) port map( - CLOCK => CLOCK, + CLOCK => CLK, RESET => RESET, --LVL1 channel @@ -384,11 +381,11 @@ begin FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT, --Status Registers - STATUS_OUT => stat_handler_i; + STATUS_OUT => stat_handler_i, --Debug - DEBUG_DATA_HANDLER_OUT => DEBUG_DATA_HANDLER_OUT, - DEBUG_IPU_HANDLER_OUT => DEBUG_IPU_HANDLER_OUT + DEBUG_DATA_HANDLER_OUT => STAT_DEBUG_DATA_HANDLER_OUT, + DEBUG_IPU_HANDLER_OUT => STAT_DEBUG_IPU_HANDLER_OUT ); diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 54168d2..723a53b 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -424,7 +424,127 @@ package trb_net_components is end component; + component trb_net16_endpoint_hades_full_handler is + generic ( + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100; + --Configure data handler + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8; + --RegIO Bus Handler + PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 1; + PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); + PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only + + --Response from FEE + FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --Slow Control Port + --common registers + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0); + REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0); + --user defined registers + REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0'); + REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0); + REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --internal data port + BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_DATA_IN : in std_logic_vector(PORT_NUMBER*32-1 downto 0) := (others => '0'); + BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); + BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); + BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); + BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); + --Onewire + ONEWIRE_INOUT : inout std_logic; --temperature sensor + ONEWIRE_MONITOR_IN : in std_logic := '0'; + ONEWIRE_MONITOR_OUT : out std_logic; + --Config endpoint id, if not statically assigned + REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0'); + + --Timing registers + TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds + TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger + TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick + + --Debugging & Status information + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0); + STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + ); + end component; component trb_net16_endpoint_hades_cts is generic( @@ -634,6 +754,157 @@ package trb_net_components is + component handler_data is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --LVL1 Handler + LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts + LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type + LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_OUT : out std_logic; + + --FEE + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --IPU Handler + IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); + IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); + + IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0); + IPU_HDR_DATA_READ_IN : in std_logic; + IPU_HDR_DATA_EMPTY_OUT : out std_logic; + + --Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + + end component; + + + + + + component handler_ipu is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --From Data Handler + DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); + DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); + DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0); + DAT_HDR_DATA_READ_OUT : out std_logic; + DAT_HDR_DATA_EMPTY_IN : in std_logic; + + --To IPU Channel + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + IPU_START_READOUT_IN : in std_logic; + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READOUT_FINISHED_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + + --Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + + end component; + + + + + component handler_trigger_and_data is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --To Endpoint + --Timing Trigger (registered) + LVL1_VALID_TRIGGER_IN : in std_logic; + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + --LVL1_handler connection + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_OUT : out std_logic; + + --IPU channel + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); + IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + IPU_START_READOUT_IN : in std_logic; + IPU_DATA_OUT : out std_logic_vector(31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READOUT_FINISHED_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + + --To FEE + --FEE to Trigger + FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + + --Data Input from FEE + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --Status Registers + STATUS_OUT : out std_logic_vector(127 downto 0); + + --Debug + DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); + DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0) + + ); + end component; + + component trb_net16_ibuf is generic ( DEPTH : integer range 0 to 7 := c_FIFO_BRAM; -- 2.43.0