From 126cd3c790440d59e0f6317d4b9be8a17c6881fd Mon Sep 17 00:00:00 2001
From: Jan Michel <michel@physik.uni-frankfurt.de>
Date: Wed, 28 Jun 2023 11:34:52 +0200
Subject: [PATCH] add long reset signal for i2c bus

---
 special/trb_net_i2cwire.vhd | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/special/trb_net_i2cwire.vhd b/special/trb_net_i2cwire.vhd
index 268ac4c..6d15a26 100644
--- a/special/trb_net_i2cwire.vhd
+++ b/special/trb_net_i2cwire.vhd
@@ -32,7 +32,7 @@ end trb_net_i2cwire;
 architecture trb_net_i2cwire_arch of trb_net_i2cwire is
 
   -- States
-  type FSM_STATES is (SLEEP, IDLE, RD_ID0, ST_ID0, RD_ID1, ST_ID1, RD_ID2, ST_ID2, WR_TMP, RD_TMP, ST_TMP, ID_DONE);
+  type FSM_STATES is (SLEEP, I2C_RESET, IDLE, RD_ID0, ST_ID0, RD_ID1, ST_ID1, RD_ID2, ST_ID2, WR_TMP, RD_TMP, ST_TMP, ID_DONE);
   signal CURRENT_STATE, NEXT_STATE: FSM_STATES;
 
   -- Signals
@@ -71,6 +71,7 @@ architecture trb_net_i2cwire_arch of trb_net_i2cwire is
 
   signal sda_drv            : std_logic;
   signal scl_drv            : std_logic;
+  signal scl_reset, scl_reset_x : std_logic;
   
   -- Components
   component i2c_slim is
@@ -114,11 +115,13 @@ begin
       ram_we        <= '0';
       temp_we       <= '0';
       i2c_go        <= '0';
+      scl_reset     <= '1';
     else
       CURRENT_STATE <= NEXT_STATE;
       ram_we        <= ram_we_x;
-      temp_we        <= temp_we_x;
+      temp_we       <= temp_we_x;
       i2c_go        <= i2c_go_x;
+      scl_reset     <= scl_reset_x;
     end if;
   end if;
 end process STATE_MEM;
@@ -132,6 +135,7 @@ begin
   temp_we_x <= '0';
   addr_int <= b"011";
   i2c_go_x <= '0';
+  scl_reset_x <= '0';
 
   i2c_action_int <= '1';
   i2c_word_int   <= '1';
@@ -141,11 +145,18 @@ begin
 
   case CURRENT_STATE is
     when SLEEP    =>
+      scl_reset_x <= '1';
       if( READOUT_ENABLE_IN = '1' ) then
-        NEXT_STATE <= IDLE;
+        NEXT_STATE <= I2C_RESET;
         rst_tc_x   <= '1';
         ram_we_x   <= '1';
       end if;
+    when I2C_RESET =>
+      scl_reset_x <= '1';
+      if( is_time_reached(timecounter,IDLE_PERIOD,CLK_PERIOD) = '1' ) then
+        NEXT_STATE  <= IDLE;
+        rst_tc_x    <= '1';
+      end if;  
     when IDLE      =>
       if( is_time_reached(timecounter,IDLE_PERIOD,CLK_PERIOD) = '1' ) then
         NEXT_STATE <= RD_ID0;
@@ -349,7 +360,7 @@ port map(
 
 -- I2C signal open collector driver
 SDA_INOUT <= '0' when (sda_drv = '0') else 'Z';
-SCL_INOUT <= '0' when (scl_drv = '0') else 'Z';
+SCL_INOUT <= '0' when (scl_drv = '0' or scl_reset = '1') else 'Z';
 
 ADDR_OUT  <= addr_int;
 DATA_OUT  <= i2c_dr_int;
@@ -358,11 +369,10 @@ WRITE_OUT <= ram_we;
 ID_OUT    <= id_int;
 TEMP_OUT  <= temp_int;
 
-STAT(31 downto 25) <= (others => '0');
-STAT(24)           <= sda_drv;
-STAT(23 downto 21) <= (others => '0');
+STAT(31 downto 22) <= (others => '0');
+STAT(21)           <= sda_drv;
 STAT(20)           <= scl_drv;
-STAT(19)           <= '0';
+STAT(19)           <= scl_reset;
 STAT(18)           <= i2c_done_int;
 STAT(17)           <= i2c_busy_int;
 STAT(16)           <= i2c_go;
-- 
2.43.0