From 12c938c01640f23546587a9a5101893448776b57 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 10 Jun 2009 13:29:14 +0000 Subject: [PATCH] *** empty log message *** --- media_interfaces/trb_net16_lsm_sfp.vhd | 2 +- media_interfaces/trb_net16_med_ecp_fot.vhd | 128 +++++++++++++------ media_interfaces/trb_net16_med_ecp_fot_4.vhd | 81 +++++++++--- media_interfaces/trb_net16_med_ecp_sfp_4.vhd | 2 + trb_net16_hub_ipu_logic.vhd | 15 ++- trb_net16_ibuf.vhd | 8 +- trb_net16_med_tlk.vhd | 4 +- trb_net16_regIO.vhd | 6 + 8 files changed, 178 insertions(+), 68 deletions(-) diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index e439905..0460625 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -238,7 +238,7 @@ begin next_align_me <= '1'; next_reset_me <= '0'; next_med_error <= ERROR_WAIT; - elsif( (sd_retry_in = '0') and ((sd_alignment_in = "10") or (sd_alignment_in = "01")) ) then + elsif( (sd_retry_in = '0') and ((sd_alignment_in = "10") or (sd_alignment_in = "01")) ) then NEXT_STATE <= WRXA; -- one komma character has been received next_reset_me <= '0'; next_med_error <= ERROR_WAIT; diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index c1bfe7c..8e5a69a 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -187,6 +187,7 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal reg_link_error : std_logic_vector(7 downto 0); signal ffs_plol : std_logic; signal link_ok : std_logic; + signal link_ok_q : std_logic; signal tx_data : std_logic_vector(8-1 downto 0); signal rx_data : std_logic_vector(8-1 downto 0); signal ff_rxfullclk : std_logic; @@ -194,7 +195,9 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal rx_k : std_logic; signal tx_k : std_logic; signal lane_rst : std_logic; + signal lane_rst_qtx : std_logic; signal quad_rst : std_logic; + signal quad_rst_qtx : std_logic; signal byte_waiting : std_logic; signal byte_buffer : std_logic_vector(8-1 downto 0); @@ -205,10 +208,11 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal tx_fifo_write_en : std_logic; signal tx_fifo_empty : std_logic; signal tx_fifo_full : std_logic; - signal last_tx_fifo_read_en : std_logic; - signal last_tx_fifo_empty : std_logic; + signal tx_fifo_valid_read : std_logic; signal tx_allow : std_logic; + signal tx_allow_del : std_logic; + signal tx_allow_qtx : std_logic; signal rx_data_reg : std_logic_vector(8-1 downto 0); signal buf_rx_data_reg : std_logic_vector(8-1 downto 0); @@ -222,6 +226,7 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal is_idle_word : std_logic; signal rx_starting : std_logic; signal rx_allow : std_logic; + signal rx_allow_del : std_logic; signal rx_allow_qrx : std_logic; signal sd_q : std_logic; signal last_rx_fifo_read_en : std_logic; @@ -229,7 +234,7 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal last_last_rx_fifo_read_en : std_logic; signal last_last_rx_fifo_empty : std_logic; signal last_rx_fifo_dout : std_logic_vector(7 downto 0); - + signal tx_fifo_valid_read_q : std_logic; signal buf_med_dataready_out : std_logic; signal buf_med_read_out : std_logic; @@ -273,8 +278,8 @@ begin ff_disp_err_ch0 => link_error(0), ff_cv_ch0 => link_error(1), ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst, --lane_rst(0), - ffc_lane_rx_rst_ch0 => lane_rst, + ffc_lane_tx_rst_ch0 => lane_rst_qtx, --lane_rst(0), + ffc_lane_rx_rst_ch0 => lane_rst_qtx, ffc_txpwdnb_ch0 => '1', ffc_rxpwdnb_ch0 => '1', ffs_rlos_lo_ch0 => link_error(2), @@ -287,7 +292,7 @@ begin oob_out_ch0 => open, ffc_macro_rst => '0', - ffc_quad_rst => quad_rst, + ffc_quad_rst => quad_rst_qtx, ffc_trst => '0', ff_txfullclk => ff_txfullclk, ffs_plol => ffs_plol @@ -337,9 +342,7 @@ begin tx_data(7 downto 0) <= x"EE"; tx_fifo_valid_read <= '0'; else - tx_fifo_read_en <= tx_allow; - last_tx_fifo_read_en <= tx_fifo_read_en; - last_tx_fifo_empty <= tx_fifo_empty; + tx_fifo_read_en <= tx_allow_qtx; tx_fifo_valid_read <= tx_fifo_read_en and not tx_fifo_empty; if( byte_waiting = '0' ) then if( (tx_fifo_valid_read = '1')) then @@ -347,13 +350,13 @@ begin byte_waiting <= '1'; tx_k <= '0'; tx_data(7 downto 0) <= tx_fifo_dout(7 downto 0); - tx_fifo_read_en <= tx_allow; + tx_fifo_read_en <= tx_allow_qtx; else byte_buffer(7 downto 0) <= x"50"; byte_waiting <= '1'; tx_k <= '1'; tx_data(7 downto 0) <= x"BC"; - tx_fifo_read_en <= tx_allow; + tx_fifo_read_en <= tx_allow_qtx; end if; else --if byte_waiting = '1' then tx_data(7 downto 0) <= byte_buffer(7 downto 0); @@ -365,7 +368,7 @@ begin end if; end process; - fifo_reset <= reset or quad_rst or not rx_allow_qrx; + fifo_reset <= reset or quad_rst or not rx_allow; --sync with SYSCLK --RX Control (25) --------------------- @@ -429,7 +432,7 @@ begin --TX Control (100) --------------------- - buf_med_read_out <= not tx_fifo_full and tx_allow; + buf_med_read_out <= not tx_fifo_full and tx_allow_del; tx_fifo_write_en <= buf_med_read_out and med_dataready_in; tx_fifo_data_in(15 downto 0) <= med_data_in(15 downto 0); med_read_out <= buf_med_read_out; @@ -464,7 +467,7 @@ begin end if; end process; - rx_fifo_read_en <= rx_allow and not rx_fifo_empty; + rx_fifo_read_en <= rx_allow_del and not rx_fifo_empty; MED_DATA_OUT(15 downto 0) <= buf_MED_DATA_OUT(15 downto 0); MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; MED_PACKET_NUM_OUT <= rx_counter; @@ -494,30 +497,66 @@ begin --------------------- - LINK_ERROR_SYNC: signal_sync + CLK_TO_TX_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 3 + ) + port map( + RESET => reset, + D_IN(0) => tx_allow, + D_IN(1) => lane_rst, + D_IN(2) => quad_rst, + CLK0 => CLK, + CLK1 => ff_txfullclk, + D_OUT(0) => tx_allow_qtx, + D_OUT(1) => lane_rst_qtx, + D_OUT(2) => quad_rst_qtx + ); + + TX_TO_CLK_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => reset, + D_IN(0) => tx_fifo_valid_read, + CLK0 => ff_txfullclk, + CLK1 => CLK, + D_OUT(0) => tx_fifo_valid_read_q + ); + + RX_TO_CLK_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 8 + WIDTH => 9 ) port map( RESET => reset, D_IN(7 downto 0) => link_error, + D_IN(8) => link_ok, CLK0 => ff_rxfullclk, CLK1 => CLK, - D_OUT(7 downto 0) => link_error_q + D_OUT(7 downto 0) => link_error_q, + D_OUT(8) => link_ok_q ); - SD_SYNC_2: signal_sync + SYNC_INPUT_TO_CLK : signal_sync generic map( DEPTH => 2, - WIDTH => 1 + WIDTH => 3 ) port map( RESET => reset, D_IN(0) => sd, - CLK0 => ff_rxfullclk, + D_IN(1) => tx_allow, + D_IN(2) => rx_allow, + CLK0 => CLK, CLK1 => CLK, - D_OUT(0) => sd_q + D_OUT(0) => sd_q, + D_OUT(1) => tx_allow_del, + D_OUT(2) => rx_allow_del ); THE_SFP_STATUS_SYNC: signal_sync @@ -528,7 +567,7 @@ begin port map( RESET => RESET, D_IN(0) => rx_allow, - CLK0 => ff_rxfullclk, + CLK0 => CLK, CLK1 => ff_rxfullclk, D_OUT(0) => rx_allow_qrx ); @@ -544,7 +583,7 @@ begin elsif( led_counter = 0 ) then rx_led <= '0'; end if; - if( tx_fifo_valid_read = '1') then + if( tx_fifo_valid_read_q = '1') then tx_led <= '1'; elsif led_counter = 0 then tx_led <= '0'; @@ -553,23 +592,9 @@ begin end process; - STAT_OP(9 downto 0) <= FSM_STAT_OP(9 downto 0); - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(15 downto 12) <= FSM_STAT_OP(15 downto 12); - - STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0); - STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0); - STAT_DEBUG(40) <= rx_fifo_write_en; - STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout; - STAT_DEBUG(63 downto 49) <= (others => '0'); - - PROC_LED : process(CLK_25) - begin - if rising_edge(CLK_25) then - buf_rx_data_reg <= rx_data_reg; - end if; - end process; +----------------------------------------------------------- +--Link State Machine +----------------------------------------------------------- THE_SFP_LSM: trb_net16_lsm_sfp port map( @@ -578,7 +603,7 @@ begin CLEAR => reset, SFP_MISSING_IN => '0', SFP_LOS_IN => sfp_los, - SD_LINK_OK_IN => link_ok, + SD_LINK_OK_IN => link_ok_q, SD_LOS_IN => link_error_q(2), SD_TXCLK_BAD_IN => ffs_plol, SD_RXCLK_BAD_IN => link_error_q(7), @@ -601,7 +626,28 @@ begin FSM_CTRL_OP <= CTRL_OP; +----------------------------------------------------------- +--Debugging +----------------------------------------------------------- + + STAT_OP(9 downto 0) <= FSM_STAT_OP(9 downto 0); + STAT_OP(10) <= rx_led; + STAT_OP(11) <= tx_led; + STAT_OP(15 downto 12) <= FSM_STAT_OP(15 downto 12); + + STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0); + STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0); + STAT_DEBUG(40) <= rx_fifo_write_en; + STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout; + STAT_DEBUG(63 downto 49) <= (others => '0'); + + PROC_LED : process(ff_rxfullclk) + begin + if rising_edge(ff_rxfullclk) then + buf_rx_data_reg <= rx_data_reg; + end if; + end process; end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_med_ecp_fot_4.vhd b/media_interfaces/trb_net16_med_ecp_fot_4.vhd index 7375921..84f1b76 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4.vhd @@ -44,6 +44,8 @@ architecture trb_net16_med_ecp_fot_4_arch of trb_net16_med_ecp_fot_4 is attribute HGROUP : string; -- for whole architecture attribute HGROUP of trb_net16_med_ecp_fot_4_arch : architecture is "GROUP_PCS"; + attribute syn_sharing : string; + attribute syn_sharing of trb_net16_med_ecp_fot_4_arch : architecture is "off"; component serdes_fot_full_quad is generic( @@ -283,6 +285,7 @@ component serdes_fot_full_quad is signal reg_link_error : link_error_t; signal ffs_plol : std_logic; signal link_ok : std_logic_vector(3 downto 0); + signal link_ok_q : std_logic_vector(3 downto 0); signal tx_data : std_logic_vector(8*4-1 downto 0); signal rx_data : std_logic_vector(8*4-1 downto 0); signal buf_rx_data_reg : std_logic_vector(8*4-1 downto 0); @@ -291,7 +294,9 @@ component serdes_fot_full_quad is signal rx_k : std_logic_vector(3 downto 0); signal tx_k : std_logic_vector(3 downto 0); signal lane_rst : std_logic_vector(3 downto 0); + signal lane_rst_qtx : std_logic_vector(3 downto 0); signal quad_rst : std_logic_vector(3 downto 0); + signal quad_rst_qtx : std_logic_vector(3 downto 0); signal byte_waiting : std_logic_vector(3 downto 0); signal byte_buffer : std_logic_vector(4*8-1 downto 0); @@ -302,10 +307,11 @@ component serdes_fot_full_quad is signal tx_fifo_write_en : std_logic_vector(3 downto 0); signal tx_fifo_empty : std_logic_vector(3 downto 0); signal tx_fifo_full : std_logic_vector(3 downto 0); - signal last_tx_fifo_read_en : std_logic_vector(3 downto 0); - signal last_tx_fifo_empty : std_logic_vector(3 downto 0); + signal tx_fifo_valid_read : std_logic_vector(3 downto 0); signal tx_allow : std_logic_vector(3 downto 0); + signal tx_allow_del : std_logic_vector(3 downto 0); + signal tx_allow_qtx : std_logic_vector(3 downto 0); signal rx_data_reg : std_logic_vector(4*8-1 downto 0); signal buf_rx_data : std_logic_vector(4*8-1 downto 0); @@ -318,6 +324,7 @@ component serdes_fot_full_quad is signal is_idle_word : std_logic_vector(3 downto 0); signal rx_starting : std_logic_vector(3 downto 0); signal rx_allow : std_logic_vector(3 downto 0); + signal rx_allow_del : std_logic_vector(3 downto 0); signal rx_allow_qrx : std_logic_vector(3 downto 0); signal sd_q : std_logic_vector(3 downto 0); signal last_rx_fifo_read_en : std_logic_vector(3 downto 0); @@ -325,6 +332,7 @@ component serdes_fot_full_quad is signal last_last_rx_fifo_read_en : std_logic_vector(3 downto 0); signal last_last_rx_fifo_empty : std_logic_vector(3 downto 0); signal last_rx_fifo_dout : std_logic_vector(4*8-1 downto 0); + signal tx_fifo_valid_read_q : std_logic_vector(3 downto 0); signal buf_med_dataready_out : std_logic_vector(3 downto 0); signal buf_med_read_out : std_logic_vector(3 downto 0); @@ -524,9 +532,7 @@ begin tx_data((i+1)*8-1 downto i*8) <= x"EE"; tx_fifo_valid_read(i) <= '0'; else - tx_fifo_read_en(i) <= tx_allow(i); - last_tx_fifo_read_en(i) <= tx_fifo_read_en(i); - last_tx_fifo_empty(i) <= tx_fifo_empty(i); + tx_fifo_read_en(i) <= tx_allow_qtx(i); tx_fifo_valid_read(i) <= tx_fifo_read_en(i) and not tx_fifo_empty(i); if( byte_waiting(i) = '0' ) then if( (tx_fifo_valid_read(i) = '1')) then @@ -534,13 +540,13 @@ begin byte_waiting(i) <= '1'; tx_k(i) <= '0'; tx_data((i+1)*8-1 downto i*8) <= tx_fifo_dout(i*16+7 downto i*16+0); - tx_fifo_read_en(i) <= tx_allow(i); + tx_fifo_read_en(i) <= tx_allow_qtx(i); else byte_buffer((i+1)*8-1 downto i*8) <= x"50"; byte_waiting(i) <= '1'; tx_k(i) <= '1'; tx_data((i+1)*8-1 downto i*8) <= x"BC"; - tx_fifo_read_en(i) <= tx_allow(i); + tx_fifo_read_en(i) <= tx_allow_qtx(i); end if; else --if byte_waiting = '1' then tx_data((i+1)*8-1 downto i*8) <= byte_buffer((i+1)*8-1 downto i*8); @@ -552,7 +558,7 @@ begin end if; end process; - fifo_reset(i) <= reset or quad_rst(0) or not rx_allow_qrx(i); + fifo_reset(i) <= reset or quad_rst(0) or not rx_allow(i); --(sync with SYSCLK) --RX Control (25) --------------------- @@ -618,7 +624,7 @@ begin --TX Control (100) --------------------- - buf_med_read_out(i) <= not tx_fifo_full(i) and tx_allow(i); + buf_med_read_out(i) <= not tx_fifo_full(i) and tx_allow_del(i); tx_fifo_write_en(i) <= buf_med_read_out(i) and med_dataready_in(i); tx_fifo_data_in(i*16+15 downto i*16) <= med_data_in(i*16+15 downto i*16); med_read_out(i) <= buf_med_read_out(i); @@ -653,7 +659,7 @@ begin end if; end process; - rx_fifo_read_en(i) <= rx_allow(i) and not rx_fifo_empty(i); + rx_fifo_read_en(i) <= rx_allow_del(i) and not rx_fifo_empty(i); MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16); MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i); MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH); @@ -683,30 +689,67 @@ begin --------------------- + CLK_TO_TX_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 3 + ) + port map( + RESET => reset, + D_IN(0) => tx_allow(i), + D_IN(1) => lane_rst(i), + D_IN(2) => quad_rst(i), + CLK0 => CLK, + CLK1 => ff_txfullclk, + D_OUT(0) => tx_allow_qtx(i), + D_OUT(1) => lane_rst_qtx(i), + D_OUT(2) => quad_rst_qtx(i) + ); + + TX_TO_CLK_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => reset, + D_IN(0) => tx_fifo_valid_read(i), + CLK0 => ff_txfullclk, + CLK1 => CLK, + D_OUT(0) => tx_fifo_valid_read_q(i) + ); + + LINK_ERROR_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 8 + WIDTH => 9 ) port map( RESET => reset, D_IN(7 downto 0) => link_error(i), + D_IN(8) => link_ok(i), CLK0 => ff_rxfullclk(i), CLK1 => CLK, - D_OUT(7 downto 0) => link_error_q(i) + D_OUT(7 downto 0) => link_error_q(i), + D_OUT(8) => link_ok_q(i) ); - SD_SYNC_2: signal_sync + SYNC_INPUT_TO_CLK : signal_sync generic map( DEPTH => 2, - WIDTH => 1 + WIDTH => 3 ) port map( RESET => reset, D_IN(0) => sd(i), - CLK0 => ff_rxfullclk(i), + D_IN(1) => tx_allow(i), + D_IN(2) => rx_allow(i), + CLK0 => CLK, CLK1 => CLK, - D_OUT(0) => sd_q(i) + D_OUT(0) => sd_q(i), + D_OUT(1) => tx_allow_del(i), + D_OUT(2) => rx_allow_del(i) ); THE_SFP_STATUS_SYNC: signal_sync @@ -717,7 +760,7 @@ begin port map( RESET => RESET, D_IN(0) => rx_allow(i), - CLK0 => ff_rxfullclk(i), + CLK0 => CLK, CLK1 => ff_rxfullclk(i), D_OUT(0) => rx_allow_qrx(i) ); @@ -733,7 +776,7 @@ begin elsif( led_counter(i) = 0 ) then rx_led(i) <= '0'; end if; - if( tx_fifo_valid_read(i) = '1') then + if( tx_fifo_valid_read_q(i) = '1') then tx_led(i) <= '1'; elsif led_counter(i) = 0 then tx_led(i) <= '0'; @@ -771,7 +814,7 @@ begin CLEAR => reset, SFP_MISSING_IN => '0', SFP_LOS_IN => sfp_los(i), - SD_LINK_OK_IN => link_ok(i), + SD_LINK_OK_IN => link_ok_q(i), SD_LOS_IN => link_error_q(i)(2), SD_TXCLK_BAD_IN => ffs_plol, SD_RXCLK_BAD_IN => link_error_q(i)(7), diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd index 69b7462..e804640 100644 --- a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd @@ -53,6 +53,8 @@ architecture med_ecp_sfp_4 of trb_net16_med_ecp_sfp_4 is attribute HGROUP : string; -- for whole architecture attribute HGROUP of med_ecp_sfp_4 : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of med_ecp_sfp_4 : architecture is "off"; component serdes_sfp_full_quad is generic( diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 07b60df..f9e143a 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -184,6 +184,8 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal next_reply_adder_final_result : std_logic_vector(15 downto 0); signal last_reply_adder_ready: std_logic; + signal last_comb_reply_pool_dataready : std_logic; + begin INIT_POOL_SBUF: trb_net16_sbuf @@ -656,12 +658,23 @@ begin if rising_edge(CLK) then if RESET = '1' or reply_data_counter_reset = '1' then reply_data_counter <= (others => '1'); - elsif comb_REPLY_POOL_DATAREADY = '1' and packet_counter(0) = '1' then + elsif last_comb_REPLY_POOL_DATAREADY = '1' and packet_counter(0) = '0' then reply_data_counter <= reply_data_counter + 1; end if; end if; end process; + PROC_REG_COMB_DATAREADY : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_comb_REPLY_POOL_DATAREADY <= '0'; + else + last_comb_REPLY_POOL_DATAREADY <= comb_REPLY_POOL_DATAREADY; + end if; + end if; + end process; + --REPLY select input ---------------------------------- REPLY_ARBITER: trb_net_priority_arbiter diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index fe0a229..3afa129 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -48,10 +48,10 @@ entity trb_net16_ibuf is end entity; architecture trb_net16_ibuf_arch of trb_net16_ibuf is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; component trb_net_CRC is port( diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index fc5db99..cfe63fa 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -467,7 +467,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); next_rx_allow <= rx_allow; next_internal_reset <= internal_reset; next_counter <= counter + 1; - counter_reset <= reg_RX_ER; + counter_reset <= reg_RX_ER and not reg_RX_DV; next_MED_ERROR_OUT <= buf_MED_ERROR_OUT; case current_state is @@ -498,7 +498,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); next_MED_ERROR_OUT <= ERROR_OK; next_internal_reset <= '0'; end case; - if reg_RX_ER = '1' and internal_reset = '0' then + if reg_RX_ER = '1' and reg_RX_DV = '0' and internal_reset = '0' then next_rx_allow <= '0'; next_tx_allow <= '0'; next_state <= WAIT_FOR_RX_LOCK; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 8211a08..a4643a7 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -93,6 +93,12 @@ end entity; architecture trb_net16_regIO_arch of trb_net16_regIO is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_regIO_arch : architecture is "RegIO_group"; + + component trb_net_pattern_gen is generic ( WIDTH : integer := 6 -- 2.43.0