From 12e20f3c9f9c05529cdfd5d43e2232be0038aa18 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 1 Jan 2020 11:25:26 +0100 Subject: [PATCH] some fixes for startup in calibration monitoring --- combiner_calib/code_EBR/Cal_Limits_v2.vhd | 90 +++++++++++++---------- combiner_calib/code_EBR/Calibration.vhd | 6 +- 2 files changed, 53 insertions(+), 43 deletions(-) diff --git a/combiner_calib/code_EBR/Cal_Limits_v2.vhd b/combiner_calib/code_EBR/Cal_Limits_v2.vhd index 8cffb61..89f44d1 100644 --- a/combiner_calib/code_EBR/Cal_Limits_v2.vhd +++ b/combiner_calib/code_EBR/Cal_Limits_v2.vhd @@ -29,7 +29,7 @@ entity Cal_Limits_v2 is chnl : in std_logic_vector( 6 downto 0); Do_Cal_in : in std_logic; chnl_cnt_in : in unsigned(19 downto 0); - BUS_Flash_value : in std_logic_vector(27 downto 0); + BUS_Flash_value : in std_logic_vector(31 downto 0); Flash_flag : in std_logic; DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); write_curr_out : out std_logic; @@ -132,6 +132,11 @@ begin else cnt_v := chnl_cnt_in; + + if (Flash_flag = '1') and (BUS_Flash_value(19 downto 0) /= x"00000") then + dflt_i(to_integer(unsigned(BUS_Flash_value( 30 downto 27))),to_integer(unsigned(BUS_Flash_value( 26 downto 20)))) <= '0'; + end if; + for i in 0 to (locBufDepth-1) loop if (EBRcntr(i)(31) = '1') and (EBRcntr(i)(29 downto 26) = FPGA) and (EBRcntr(i)(25 downto 20) = chnl(5 downto 0)) then cnt_v := unsigned(EBRcntr(i)(19 downto 0)); @@ -327,42 +332,37 @@ begin end if;--rising_edge end process; - proc_Flash_input : process (CLK) - begin - if rising_edge(CLK) then - write_default <= '0'; - if RESET = '1' then - --RESET - else - --IDEA: - -- Send Flash value of FOGA|channel to thsi location. If Flash_flag = 1 the value is written to RAM. - -- write_out is OR of this write and write from current. By default wrrite from here is 0. - if Flash_flag = '1' then - --def_value(0,to_integer(unsigned(BUS_Flash_value(27 downto 20))))( 19 downto 0) <= BUS_Flash_value(19 downto 0); - write_default <= '0';--'1'; - --min_default <= "0000010011";--BUS_Flash_value( 9 downto 0); - --max_default <= "0111111110";--BUS_Flash_value(19 downto 10); - --fpga_default <= - end if; - end if; - end if; - end process; +-- proc_Flash_input : process (CLK) +-- begin +-- if rising_edge(CLK) then +-- write_default <= '0'; +-- if RESET = '1' then +-- --RESET +-- else +-- --IDEA: +-- -- Send Flash value of FOGA|channel to thsi location. If Flash_flag = 1 the value is written to RAM. +-- -- write_out is OR of this write and write from current. By default wrrite from here is 0. +-- +-- end if; +-- end if; +-- end process; --- write_curr_out <= write_curr or write_default; --- min_curr_out <= min_default when write_default = '1' else --- min_curr; --- min_out_out <= min_default when write_default = '1' else --- min_out; --- max_curr_out <= max_default when write_default = '1' else --- max_curr; --- max_out_out <= max_default when write_default = '1' else --- max_out; - write_curr_out <= write_curr; - min_curr_out <= min_curr; - min_out_out <= min_out; - max_curr_out <= max_curr; - max_out_out <= max_out; + write_curr_out <= write_curr or write_default; + min_curr_out <= min_default when write_default = '1' else + min_curr; + min_out_out <= min_default when write_default = '1' else + min_out; + max_curr_out <= max_default when write_default = '1' else + max_curr; + max_out_out <= max_default when write_default = '1' else + max_out; + +-- write_curr_out <= write_curr; +-- min_curr_out <= min_curr; +-- min_out_out <= min_out; +-- max_curr_out <= max_curr; +-- max_out_out <= max_out; dflt_out <= dflt_i(0,3)&dflt_i(0,2)&dflt_i(0,1)&dflt_i(0,0); --synchronous output @@ -377,14 +377,24 @@ begin chnl_out_write <= chnl_r; FPGA_out_write <= fpga_r; FPGA_out <= fpga_r; - if Flash_flag = '1' then - FPGA_out_curr <= fpga_r; -- fpga number from Flash + if Flash_flag = '1' then + if BUS_Flash_value(19 downto 0) = x"00000" then + write_default <= '0';--'1'; + else + write_default <= '1';--'1'; + --dflt_i(to_integer(unsigned(BUS_Flash_value( 30 downto 27))),to_integer(unsigned(BUS_Flash_value( 26 downto 20)))) <= '0'; + end if; + min_default <= BUS_Flash_value( 9 downto 0); + max_default <= BUS_Flash_value(19 downto 10); + FPGA_out_curr <= BUS_Flash_value( 30 downto 27); -- fpga number from Flash + chnl_out <= BUS_Flash_value( 26 downto 20); + chnl_out_curr <= BUS_Flash_value( 26 downto 20); else FPGA_out_curr <= fpga_r; + chnl_out <= chnl_r; + chnl_out_curr <= chnl_r; end if; - - chnl_out <= chnl_r; - chnl_out_curr <= chnl_r; + end if; end process; diff --git a/combiner_calib/code_EBR/Calibration.vhd b/combiner_calib/code_EBR/Calibration.vhd index bd789b5..923ff83 100644 --- a/combiner_calib/code_EBR/Calibration.vhd +++ b/combiner_calib/code_EBR/Calibration.vhd @@ -111,7 +111,7 @@ architecture Behavioral of TDC_Calibration is signal Bus_max : std_logic_vector( 9 downto 0); signal FPGA_out_curr : std_logic_vector( 3 downto 0); signal chnl_out_curr : std_logic_vector( 6 downto 0); - signal BUS_Flash_value : std_logic_vector(27 downto 0); + signal BUS_Flash_value : std_logic_vector(31 downto 0); signal Flash_flag : std_logic; signal chnl_out_write_cnt : std_logic_vector( 6 downto 0); signal FPGA_out_write_cnt : std_logic_vector( 3 downto 0); @@ -200,8 +200,8 @@ begin if BUS_RX.write = '1' then BUS_TX.ack <= '1'; - if BUS_RX.addr(11 downto 0) > x"010" and BUS_RX.addr(11 downto 0) < x"0d0" then - BUS_Flash_value <= std_logic_vector(unsigned(BUS_RX.addr(7 downto 0))-7) & BUS_RX.data(19 downto 10) & BUS_RX.data(9 downto 0); + if BUS_RX.addr(11 downto 0) > x"010" and BUS_RX.addr(11 downto 0) < x"0d0" then --x"810" is upper limit + BUS_Flash_value <= std_logic_vector(unsigned(BUS_RX.addr(11 downto 0))-x"10") & BUS_RX.data(19 downto 10) & BUS_RX.data(9 downto 0); Flash_flag <= '1'; elsif BUS_RX.addr(11 downto 0) >= x"000" and BUS_RX.addr(11 downto 0) < x"010" then --standard debugg case BUS_RX.addr(11 downto 0) is -- 2.43.0