From 13171d4d9860445026eba994c209779f1d14656c Mon Sep 17 00:00:00 2001
From: Tobias Weber <webert@kph.uni-mainz.de>
Date: Tue, 24 Mar 2015 17:16:23 +0100
Subject: [PATCH] Removed async reset input in graycounter since this was not
 used anymore.

---
 mupix/sources/MuPix3_interface.vhd |  3 +--
 mupix/sources/graycounter.vhd      | 35 +++++++++++++++---------------
 mupix/sources/mupix_components.vhd |  1 -
 3 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/sources/MuPix3_interface.vhd
index 3eaa123..6d18329 100644
--- a/mupix/sources/MuPix3_interface.vhd
+++ b/mupix/sources/MuPix3_interface.vhd
@@ -513,7 +513,7 @@ begin
     end if;
   end process;
 
-  resetgraycounter <= rst or timestampreset_in;
+  resetgraycounter <= rst or timestampreset_in or timestampcontrolbits(9);
 
   grcount : Graycounter
     generic map(
@@ -522,7 +522,6 @@ begin
     port map(
       clk            => clk,
       reset          => resetgraycounter,
-      sync_reset     => timestampcontrolbits(9),
       clk_divcounter => graycounter_clkdiv_counter(7 downto 0),
       counter        => graycount
       );
diff --git a/mupix/sources/graycounter.vhd b/mupix/sources/graycounter.vhd
index 8945014..a15ad76 100644
--- a/mupix/sources/graycounter.vhd
+++ b/mupix/sources/graycounter.vhd
@@ -13,22 +13,21 @@ entity Graycounter is
     COUNTWIDTH : integer := 8
     );
   port (
-    clk        : in std_logic;          -- clock
-    reset      : in std_logic;          -- asynchronous reset
-    sync_reset : in std_logic;          -- synchronous reset
-    clk_divcounter : in std_logic_vector(7 downto 0); -- clockdivider for
-                                                      -- graycounter clock
-    counter : out std_logic_vector(COUNTWIDTH-1 downto 0)  -- counter
+    clk            : in  std_logic;     -- clock
+    reset          : in  std_logic;     -- reset
+    clk_divcounter : in  std_logic_vector(7 downto 0);  -- clockdivider for
+                                                        -- graycounter clock
+    counter        : out std_logic_vector(COUNTWIDTH-1 downto 0)  -- counter
     );
 end Graycounter;
 
 architecture rtl of Graycounter is
   
-  signal msb           : std_logic := '0';
+  signal msb           : std_logic                             := '0';
   signal counter_reg   : std_logic_vector(COUNTWIDTH downto 0) := (others => '0');
   signal no_ones_below : std_logic_vector(COUNTWIDTH downto 0) := "000000001";
-  signal clk_enable : std_logic := '0';
-  signal divcounter : unsigned(7 downto 0) := (others => '0');
+  signal clk_enable    : std_logic                             := '0';
+  signal divcounter    : unsigned(7 downto 0)                  := (others => '0');
   
 begin
   
@@ -36,7 +35,7 @@ begin
 
   msb <= counter_reg(COUNTWIDTH) or counter_reg(COUNTWIDTH-1);
 
-  clock_divider_proc: process (clk) is
+  clock_divider_proc : process (clk) is
   begin  -- process clock_divider_proc
     if rising_edge(clk) then
       if reset = '1' then
@@ -56,19 +55,19 @@ begin
   process(clk, reset)
   begin
     if (clk'event and clk = '1') then
-      if (sync_reset = '1') then
+      if (reset = '1') then
         no_ones_below(0) <= '1';
-        counter_reg    <= (others => '0');
-        counter_reg(0) <= '1';
+        counter_reg      <= (others => '0');
+        counter_reg(0)   <= '1';
       else
         if clk_enable = '1' then
           counter_reg(0) <= not counter_reg(0);
-        for i in 1 to COUNTWIDTH-1 loop
-          counter_reg(i) <= counter_reg(i) xor (counter_reg(i-1) and no_ones_below(i-1));
-        end loop;
-        counter_reg(COUNTWIDTH) <= counter_reg(COUNTWIDTH) xor (msb and no_ones_below(COUNTWIDTH-1));
+          for i in 1 to COUNTWIDTH-1 loop
+            counter_reg(i) <= counter_reg(i) xor (counter_reg(i-1) and no_ones_below(i-1));
+          end loop;
+          counter_reg(COUNTWIDTH) <= counter_reg(COUNTWIDTH) xor (msb and no_ones_below(COUNTWIDTH-1));
         else
-          counter_reg <=  counter_reg;
+          counter_reg <= counter_reg;
         end if;
       end if;
     end if;
diff --git a/mupix/sources/mupix_components.vhd b/mupix/sources/mupix_components.vhd
index 7eebcbe..4dabb44 100644
--- a/mupix/sources/mupix_components.vhd
+++ b/mupix/sources/mupix_components.vhd
@@ -156,7 +156,6 @@ package mupix_components is
     port (
       clk            : in  std_logic;
       reset          : in  std_logic;
-      sync_reset     : in  std_logic;
       clk_divcounter : in  std_logic_vector(7 downto 0);
       counter        : out std_logic_vector(COUNTWIDTH-1 downto 0));
   end component;
-- 
2.43.0