From 1338497d66a1e760165f10c0985804b4cd495911 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Tue, 6 Oct 2020 12:49:17 +0200 Subject: [PATCH] extra control for refTime channel on online calibration --- combiner_cts/code_EBR/Calibration.vhd | 60 +++++++++++++++----------- combiner_cts/code_EBR/read_cnt.vhd | 62 ++++++++++++++++----------- 2 files changed, 73 insertions(+), 49 deletions(-) diff --git a/combiner_cts/code_EBR/Calibration.vhd b/combiner_cts/code_EBR/Calibration.vhd index 892c644..77a04c3 100644 --- a/combiner_cts/code_EBR/Calibration.vhd +++ b/combiner_cts/code_EBR/Calibration.vhd @@ -139,6 +139,9 @@ architecture TDC_Calibration_arch of TDC_Calibration is signal MinMax_Monitor : MinMax_t := (others=>(others=>(others=>'0'))); signal BUS_stop_LimitGen : std_logic := '0'; signal BUS_Trig_type : std_logic_vector( 3 downto 0):="0000"; + signal BUS_stop_LimitGen_ch0 : std_logic := '0'; + signal BUS_Trig_type_ch0 : std_logic_vector( 3 downto 0):="0000"; + signal stop_Limits_r : std_logic := '0'; signal stp_Lmt_read_cnt : std_logic := '0'; signal stp_Lmt_MemCurr : std_logic := '0'; @@ -217,9 +220,11 @@ begin elsif BUS_RX.addr(11 downto 0) >= x"000" and BUS_RX.addr(11 downto 0) < x"010" then --standard debugg case BUS_RX.addr(11 downto 0) is when x"000" => - BUS_Trig_type <= BUS_RX.data(11 downto 8); - BUS_do_Cal <= BUS_RX.data(0); -- change between w/ and w/o FPGA based Calibration - BUS_stop_LimitGen <= BUS_RX.data(4); + BUS_Trig_type_ch0 <= BUS_RX.data(19 downto 16); + BUS_stop_LimitGen_ch0 <= BUS_RX.data(12); + BUS_Trig_type <= BUS_RX.data(11 downto 8); + BUS_do_Cal <= BUS_RX.data(0); -- change between w/ and w/o FPGA based Calibration + BUS_stop_LimitGen <= BUS_RX.data(4); when x"001" => Cal_Limit_reg <= unsigned(BUS_RX.data(19 downto 0)); -- Set Maximum Value for Calibration Counter when x"002" => @@ -240,7 +245,10 @@ begin BUS_TX.ack <= '1'; if BUS_RX.addr(11 downto 4) = x"00" then case BUS_RX.addr(3 downto 0) is - when x"0" => BUS_TX.data(31 downto 12) <= (others => '0'); + when x"0" => BUS_TX.data(31 downto 20) <= (others => '0'); + BUS_TX.data(19 downto 16) <= BUS_Trig_type_ch0; + BUS_TX.data(15 downto 13) <= (others => '0'); + BUS_TX.data(12) <= BUS_stop_LimitGen_ch0; BUS_TX.data(11 downto 8) <= BUS_Trig_type; BUS_TX.data( 7 downto 5) <= (others => '0'); BUS_TX.data( 4) <= BUS_stop_LimitGen; @@ -382,27 +390,29 @@ begin USE_BUSY_RELEASE => USE_BUSY_RELEASE ) port map( - CLK => CLK, - RESET => RESET, - BUS_stp_Lmt => BUS_stop_LimitGen, - BUS_Trig_type => BUS_Trig_type, - chnl => chnl_read_cnt, - FPGA_out => FPGA_o_cnt, - FPGA_in => FPGA_in, - Trigger_type => TRIGG_TYPE, - DIN => DIN_i_Mem, - DIN_ready => DIN_i_Mem_ready, - DIN_type => DIN_i_Mem_type, - DOUT => DIN_o_cnt, - DOUT_ready => DIN_o_cnt_ready, - DOUT_type => DIN_o_cnt_type, - Do_Cal => Do_Cal_read_cnt, - FPGA_cnt_mntr => FPGA_cnt_mntr, - FPGA_mntr => FPGA_mntr, - stop_Limit => stp_Lmt_read_cnt, - DIN_info => DIN_info_ready, - DOUT_info => DIN_info_rc, - ch0_onoff => ch0_onoff + CLK => CLK, + RESET => RESET, + BUS_stp_Lmt => BUS_stop_LimitGen, + BUS_Trig_type => BUS_Trig_type, + BUS_stp_Lmt_ch0 => BUS_stop_LimitGen_ch0, + BUS_Trig_type_ch0 => BUS_Trig_type_ch0, + chnl => chnl_read_cnt, + FPGA_out => FPGA_o_cnt, + FPGA_in => FPGA_in, + Trigger_type => TRIGG_TYPE, + DIN => DIN_i_Mem, + DIN_ready => DIN_i_Mem_ready, + DIN_type => DIN_i_Mem_type, + DOUT => DIN_o_cnt, + DOUT_ready => DIN_o_cnt_ready, + DOUT_type => DIN_o_cnt_type, + Do_Cal => Do_Cal_read_cnt, + FPGA_cnt_mntr => FPGA_cnt_mntr, + FPGA_mntr => FPGA_mntr, + stop_Limit => stp_Lmt_read_cnt, + DIN_info => DIN_info_ready, + DOUT_info => DIN_info_rc, + ch0_onoff => ch0_onoff ); -- end generate read_COMBINER; diff --git a/combiner_cts/code_EBR/read_cnt.vhd b/combiner_cts/code_EBR/read_cnt.vhd index 1d459ec..4128adf 100644 --- a/combiner_cts/code_EBR/read_cnt.vhd +++ b/combiner_cts/code_EBR/read_cnt.vhd @@ -11,27 +11,29 @@ entity read_cnt is USE_DATA_FINISHED : integer range 0 to 1 := c_NO; USE_BUSY_RELEASE : integer range 0 to 1 := c_NO ); port ( - CLK : in std_logic; - RESET : in std_logic; - BUS_stp_Lmt : in std_logic; - BUS_Trig_type : in std_logic_vector( 3 downto 0); - DIN : in std_logic_vector(31 downto 0); - DIN_ready : in std_logic; - DIN_type : in std_logic_vector( 3 downto 0); - FPGA_in : in std_logic_vector(15 downto 0); - Trigger_type : in std_logic_vector( 3 downto 0); - DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); - chnl : out std_logic_vector( 6 downto 0); - FPGA_out : out std_logic_vector( 3 downto 0); - DOUT : out std_logic_vector(31 downto 0); - DOUT_ready : out std_logic; - DOUT_type : out std_logic_vector( 3 downto 0); - Do_Cal : out std_logic; - FPGA_cnt_mntr : out std_logic_vector( 3 downto 0); - FPGA_mntr : out std_logic_vector(15 downto 0); - stop_Limit : out std_logic; - DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); - ch0_onoff : in std_logic_vector(15 downto 0) + CLK : in std_logic; + RESET : in std_logic; + BUS_stp_Lmt : in std_logic; + BUS_Trig_type : in std_logic_vector( 3 downto 0); + BUS_stp_Lmt_ch0 : in std_logic; + BUS_Trig_type_ch0 : in std_logic_vector( 3 downto 0); + DIN : in std_logic_vector(31 downto 0); + DIN_ready : in std_logic; + DIN_type : in std_logic_vector( 3 downto 0); + FPGA_in : in std_logic_vector(15 downto 0); + Trigger_type : in std_logic_vector( 3 downto 0); + DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); + chnl : out std_logic_vector( 6 downto 0); + FPGA_out : out std_logic_vector( 3 downto 0); + DOUT : out std_logic_vector(31 downto 0); + DOUT_ready : out std_logic; + DOUT_type : out std_logic_vector( 3 downto 0); + Do_Cal : out std_logic; + FPGA_cnt_mntr : out std_logic_vector( 3 downto 0); + FPGA_mntr : out std_logic_vector(15 downto 0); + stop_Limit : out std_logic; + DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); + ch0_onoff : in std_logic_vector(15 downto 0) ); end read_cnt; @@ -60,12 +62,24 @@ begin FPGA_out <= std_logic_vector(to_unsigned(FPGA_i,4)); if DIN(21 downto 12) /= "1111111111" then Do_Cal <= '1'; + -- stop/allow Limit generation in general for data channels with certain trigger if ((Trigger_type = BUS_Trig_type ) or (BUS_Trig_type = "0000")) then stop_Limit <= BUS_stp_Lmt; end if; - if (DIN(28 downto 22) = "0000000") and (ch0_onoff(FPGA_i) = '0') then - Do_Cal <= '0'; + + --channel 0 + if (DIN(28 downto 22) = "0000000") then + -- stop calibration for channel 0 + if (ch0_onoff(FPGA_i) = '0') then + Do_Cal <= '0'; + end if; + -- stop/allow Limit generation for channel 0 + stop_Limit <= '1'; + if ((Trigger_type = BUS_Trig_type_ch0 ) or (BUS_Trig_type_ch0 = "0000")) then + stop_Limit <= BUS_stp_Lmt_ch0; + end if; end if; + else Do_Cal <= '0'; end if; @@ -149,4 +163,4 @@ begin end if; end process; -end Behavioral; \ No newline at end of file +end Behavioral; -- 2.43.0