From 13a2b90d55314e7618d6189a27b3b89271d4086d Mon Sep 17 00:00:00 2001 From: "Hadaq@styx" Date: Thu, 21 Nov 2013 01:00:05 +0100 Subject: [PATCH] Double nx configuration --- users/cosy_test/config/hubconfig.sh | 13 +- users/cosy_test/config/nxyter.sh | 5 +- .../config/nxyter/nxsetup_0x3800.dat | 49 +++++ .../config/nxyter/nxsetup_0x3801.dat | 49 +++++ users/cosy_test/config/nxyter/registers.txt | 173 ++++++++++++------ users/cosy_test/config/nxyter/setup.sh | 20 +- .../config/nxyter/test_fifo_flush.sh | 15 -- users/cosy_test/config/nxyter/trb3_setup.sh | 49 +++++ users/cosy_test/config/padiwa_cfg.sh | 11 ++ users/cosy_test/config/startup.sh | 3 + users/cosy_test/config/trbstart.sh | 3 +- 11 files changed, 302 insertions(+), 88 deletions(-) create mode 100644 users/cosy_test/config/nxyter/nxsetup_0x3800.dat create mode 100644 users/cosy_test/config/nxyter/nxsetup_0x3801.dat delete mode 100755 users/cosy_test/config/nxyter/test_fifo_flush.sh create mode 100755 users/cosy_test/config/nxyter/trb3_setup.sh create mode 100755 users/cosy_test/config/padiwa_cfg.sh diff --git a/users/cosy_test/config/hubconfig.sh b/users/cosy_test/config/hubconfig.sh index dedd204..c836c6e 100755 --- a/users/cosy_test/config/hubconfig.sh +++ b/users/cosy_test/config/hubconfig.sh @@ -11,10 +11,15 @@ echo "Loading hub configuration" trbcmd w 0xfffe 0xc5 0x40ff #Trb3 for nxyter - trbcmd w 0x8900 0xc0 0xfff1 - trbcmd w 0x8900 0xc1 0xfff1 - trbcmd w 0x8900 0xc3 0xfff5 - +# trbcmd w 0x8900 0xc0 0xfff1 +# trbcmd w 0x8900 0xc1 0xfff1 +# trbcmd w 0x8900 0xc3 0xfff5 + + trbcmd w 0x8900 0xc0 0xfff3 + trbcmd w 0x8900 0xc1 0xfff3 + trbcmd w 0x8900 0xc3 0xfff7 + + #Gbe configuration echo "Load GbE configuration" ../../../tools/loadregisterdb.pl gbe/register_configgbe.db diff --git a/users/cosy_test/config/nxyter.sh b/users/cosy_test/config/nxyter.sh index 9bafda0..18aa09e 100755 --- a/users/cosy_test/config/nxyter.sh +++ b/users/cosy_test/config/nxyter.sh @@ -1,5 +1,8 @@ #!/bin/bash cd nxyter -./setup.sh + +./trb3_setup.sh 0x3800 +./trb3_setup.sh 0x3801 + cd .. diff --git a/users/cosy_test/config/nxyter/nxsetup_0x3800.dat b/users/cosy_test/config/nxyter/nxsetup_0x3800.dat new file mode 100644 index 0000000..65c920d --- /dev/null +++ b/users/cosy_test/config/nxyter/nxsetup_0x3800.dat @@ -0,0 +1,49 @@ +#------------------------------------------ +# Value I2C RegisterAddress +#------------------------------------------ +0x00000000 # 0 Channel Masks BEGIN +0x00000000 # 1 +0x00000000 # 2 +0x00000000 # 3 +0x00000000 # 4 +0x00000000 # 5 +0x00000000 # 6 +0x00000000 # 7 +0x00000000 # 8 +0x00000000 # 9 +0x00000000 # 10 +0x00000000 # 11 +0x00000000 # 12 +0x00000000 # 13 +0x00000000 # 14 +0x00000000 # 15 Channel Masks END +0x000000a0 # 16 +0x000000ff # 17 +0x00000041 # 18 Common Threshold, default 0x80 +0x0000001e # 19 +0x0000005f # 20 +0x0000008c # 21 +0x00000064 # 22 +0x00000089 # 23 +0x000000ff # 24 Testpulse Strength, default 0x80 +0x00000045 # 25 +0x0000000f # 26 iDUR (26) Analog dead time (changes nxtimer CVT) +0x00000036 # 27 +0x0000005c # 28 +0x00000045 # 29 +0x000000be # 30 +0x000000be # 31 +0x00000004 # 32 TestTrigger setup etc. , default 0x00 +0x00000008 # 33 clock input 256A, set bit #3, default 0x08 (normal mode) +0x000000be # 34 +0x000000be # 35 +0x000000be # 36 +0x000000be # 37 +0x00000000 # 38 +0x00000000 # 39 +0x000000be # 40 +0x000000be # 41 +0x000000be # 42 Channel shutdown register, FIFO, do not touch +0x00000000 # 43 +0x00000000 # 44 +0x000000ff # 45 diff --git a/users/cosy_test/config/nxyter/nxsetup_0x3801.dat b/users/cosy_test/config/nxyter/nxsetup_0x3801.dat new file mode 100644 index 0000000..ea8e796 --- /dev/null +++ b/users/cosy_test/config/nxyter/nxsetup_0x3801.dat @@ -0,0 +1,49 @@ +#------------------------------------------ +# Value I2C RegisterAddress +#------------------------------------------ +0x00000000 # 0 Channel Masks BEGIN +0x00000000 # 1 +0x00000000 # 2 +0x000000c8 # 3 +0x000000a8 # 4 +0x00000000 # 5 +0x00000002 # 6 +0x00000000 # 7 +0x000000ff # 8 +0x00000000 # 9 +0x0000003f # 10 +0x0000003f # 11 +0x00000001 # 12 +0x00000000 # 13 +0x00000000 # 14 +0x00000000 # 15 Channel Masks END +0x000000a0 # 16 +0x000000ff # 17 +0x0000005a # 18 Common Threshold, default 0x80 +0x0000001e # 19 +0x0000005f # 20 +0x00000057 # 21 +0x00000064 # 22 +0x00000089 # 23 +0x000000ff # 24 Testpulse Strength, default 0x80 +0x00000045 # 25 +0x0000000f # 26 iDUR (26) Analog dead time (changes nxtimer CVT) +0x00000036 # 27 +0x0000005c # 28 +0x00000045 # 29 +0x000000be # 30 +0x000000be # 31 +0x00000000 # 32 TestTrigger setup etc. , default 0x00 +0x0000000c # 33 clock input 256A, set bit #3, default 0x08 (normal mode) +0x000000be # 34 +0x000000be # 35 +0x000000be # 36 +0x000000be # 37 +0x00000000 # 38 +0x00000000 # 39 +0x000000be # 40 +0x000000be # 41 +0x000000be # 42 Channel shutdown register, FIFO, do not touch +0x00000000 # 43 +0x00000000 # 44 +0x000000ff # 45 diff --git a/users/cosy_test/config/nxyter/registers.txt b/users/cosy_test/config/nxyter/registers.txt index 5986039..1cdc7e6 100644 --- a/users/cosy_test/config/nxyter/registers.txt +++ b/users/cosy_test/config/nxyter/registers.txt @@ -2,28 +2,38 @@ 0x8100 : w w: reset I2C State Machine 0x8101 : w w: reset I2C all Register 0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA) -0x8103 : r/w Put nxyter into offline mode +0x8103 : r/w Put Nxyter into offline mode +0x8104 : r Nxyter Main Clock Lock (125 MHz) +0x8105 : r ADC Data Clock Lock (187.5MHz) +0x810a : r/w r: PLL Nxyter Main Clock NotLock Counter + w: Clear all pll_nx_clk_notlock_ctr +0x810b : r PLL ADC Data Clock NotLock Counter -- NX I2C Setup Handler 0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c) -0x8260 : r/w DAC Register Memory (Depth: 0 - 128 ... 0x82e0) -0x8240 : w Read all I2C Registers into Memory -0x8241 : w Write all Memory to I2C Registers -0x8242 : w Read Trim DAC Register(129 deep FIFO) to Memory -0x8243 : w Write Memory to Trim DAC Register(129 deep FIFO) +0x8300 : r/w DAC Register Memory (Depth: 0 - 128 ... 0x82e0) +0x8250 : r/w Enable Nxyter Clock +0x8251 : r/w Nxyter Polarity +0x8252 : r Nxyter Testpulse Polarity +0x8253 : r/w Enable Nxyter Testpulse +0x8254 : r/w Enable Nxyter Testtrigger +0x8255 : r/w Nxyter Testpulse Channels (0: 0,4,.. 1: 1,5,.. + 2: 2,6,.. 3: 3,7,..) +0x8256 : r Nxyter I2C Online +0x8260 : w Read all I2C Registers into Memory +0x8261 : w Read Trim DAC Register(129 deep FIFO) into Memory +0x8262 : w Read ALL: Read Trim DAC Register(129 deep FIFO) into Memory -- Trigger Generator -0x8140 : w If writing just start trigger cycle, keep current setting -0x8141 : r/w Bit 15-0 : periodic time (in 10ns) -0x8142 : r/w Bit0 7-0 : number of triggers to be sent consecutive -0x8143 : r/w Bit 15-0 : Length of trigger pulse (in 10ns), if 0: skip it -0x8144 : r/w Bit0 : 1: send timestamp-reset before trigger -0x8145 : r : Testpulse Rate (in Hz) +0x8140 : r/w Length of Trigger TestPulse (12 Bit, in 4ns) +0x8141 : r Testpulse Rate (in Hz) -- Trigger Handler -0x8160 : r/w Bit 7-0 : Delay Testpulse Signal after Trigger (10ns) -0x8161 : r/w Bit 0 : Enable Testpulse Signal (default: off) -0x8162 : r : Accepted Trigger Rate (in Hz) +0x8160 : r/w Enable Testpulse Signal (default: off) +0x8161 : r/w Delay Testpulse Signal after Trigger (12 Bit, in 10ns) +0x8162 : r Accepted Trigger Rate (28 Bit, in Hz) +0x8163 : r/w r: Invalid Timing Trigger Counter + w: Clear Counter -- NX Data Receiver 0x8500 : r current Timestamp FIFO value @@ -33,55 +43,86 @@ 2: fifo_almost_empty 3..29: ignore 31: nx_frame_synced - w: adc reset -0x8502 : r/w r: Resync Counter(12bit) - w: clear Resync Counter -0x8503 : r/w r: Parity Error Counter (12bit) - w: clear Parity Error Counter -0x8505 : r/w ADC CLK Delay 4ns steps (3Bit: range 0..7) - 0: 4ns after frame_valid - 1: 8ns -------"--------- - ...... -------"--------- - 6: 28ns -------"--------- - 7: 32ns -------"--------- <= this shoud be correct - i.e. 2ns before new frame clock -0x8506 : r ADC Reset Counter -0x8507 : r/w Debug Multiplexer: +0x8502 : r/w r: Resync Counter(12 Bit) + w: Clear Resync Counter +0x8503 : r/w r: Parity Error Counter (12 Bit) + w: Clear Parity Error Counter +0x8504 : r/w ADC Sampling PLL Clock Not Lock Counter + w: Clear Counter +0x8505 : r/w johnson_counter_sync (2 Bit), do not touch, experts only register +0x8506 : r/w PLL ADC Sampling Clock DPHASE (4 Bit) +0x8507 : r/w PLL ADC Sampling Clock FINEDELB (4 Bit) + +0x8508 : r current ADC FIFO value +0x8509 : r/w Enable Test ADC Input Data Error Test +0x850a : r ADC Input Data Error Counter (16 Bit) + (only valid in case of 0x8509 is 1, see line above) +0x850b : r Nxyter Data Clock Status (1 = O.K.) +0x850c : r/w r: Reset Handler Counter (16 Bit) + w: Clear Counter +0x850e : w Reset ADC Handler +0x850f : r/w Debug Multiplexer: 0: no ADC Values, normal Debug 1: ADC Value Nxyter 2: ADC Value Testchannel 3: ADC Reset Handler -0x8508 : r current ADC FIFO value - --- NX Data Delay -0x8130 : r FIFO Delay, i.e. Trigger Delay (7Bit, in 32ns, Range 1..120) -- NX Data Validate 0x8120 : r/w Invalid Frame Counter (16 bit) / w: clear all counters 0x8121 : r Overflow Counter (16 bit) 0x8122 : r Pileup Counter (16 bit) 0x8123 : r Parity Error Counter (16 bit) -0x8124 : r Trigger Rate (in Hz) +0x8124 : r Nxyter Hit Rate (in Hz) 0x8125 : r Frame Rate (in Hz) +-- NX Data Delay +0x8130 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns). + Calculation is based on CTS Trigger Delay + (see NX Trigger Validate) + -- NX Trigger Validate -0x8180 : r/w Readout Mode (0:Ref + valid + window, 1: Ref + Valid - 3: Raw and TimeStamp + valid, - 4: Raw, 5: Raw + Valid ) -0x8181 : r/w Trigger Window Delay (12 bit, in 4ns) -0x8182 : r/w Trigger Window Width (12 bit, in 4ns) -0x8183 : r/w CTS Trigger Delay (12 bit, in 4ns) -0x8184 : r/w Readout Time Max (12 bit, in 10ns) - -0x8185 : r Busy Time Counter (12 bit, in 10ns) -0x8186 : r timestamp_ref -0x8187 : r window_lower_thr -0x8188 : r window_upper_thr -0x8189 : r data_fifo_delay (7 bit, in 32ns) -0x818a : r done counter ch 0..31 -0x818b : r done counter ch 32..63 -0x818c : r done counter ch 94..95 -0x818d : r done counter ch 96..127 +0x8400 : r/w Readout Mode: 4 Bits + Bit #3: Self Trigger Mode + Bit #2: 0: activate TS Selection Window + 1: disable TS Selection Window, i.e. + data will be written to disk as long as + Readout Time Max (Reg.: 0x8184) is valid + Bit #1..0 0: TS Ovfl and Parity Bit valid + 1: TS Ovfl, Parity and Pileup Bit valid + 2: ignore TS Status Bits + 3: -------- " ------- + +0x8401 : r/w Trigger Window Offset [TS_Offset] (11 Bit signed, in 4ns) +0x8402 : r/w Trigger Window Width [TS_Width] (10 Bit, in 4ns) +0x8403 : r/w CTS Trigger Delay [CTS_Delay] (10 Bit, in 4ns) + FPGA_Timestamp = TS_Ref + Trigger Window Lower Threshold = + TS_FPGA - CTS_Delay +/- TS_Offset + Trigger Window Upper Threshold = + TS_FPGA - CTS_Delay + TS_Offset + TS_Width +0x8404 : r/w Readout Time Max (10 Bit, in 10ns) + +0x8405 : r/w FPGA Timestamp Offset (12 Bit, in 4ns) +0x8406 : r Busy Time Counter (12 Bit, in 10ns) +0x8407 : r timestamp_ref +0x8408 : r window_lower_thr +0x8409 : r/w Out of Window Error Counter (16 Bit) + w: Clear Counter +0x840a : r data_fifo_delay (7 Bit, in 32ns) +0x840b : r WAIT flags ch 0..31 +0x840c : r WAIT flags ch 32..63 +0x840d : r WAIT flags ch 94..95 +0x840e : r WAIT flags ch 96..127 +0x840f : r HIT flags ch 0..31 +0x8410 : r HIT flags ch 32..63 +0x8411 : r HIT flags ch 94..95 +0x8412 : r HIT flags ch 96..127 +0x8413 : r DONE flags ch 0..31 +0x8414 : r DONE flags ch 32..63 +0x8415 : r DONE flags ch 94..95 +0x8416 : r DONE flags ch 96..127 +0x8417 : r channel_all_done +0x8418 : r EVT_BUFFER_FULL_IN -- Event Data Buffer 0x8600 : r read FIFO buffer @@ -103,7 +144,7 @@ 0x8800 : r/w r: Read Channel Statistic (128 channel in a row) w: reset all Histograms 0x8880 : r Read Channel Trigger Rate (128 channel in a row, 1/s) -0x3800 : r Read Channel ADC Value (128 channel in a row) +0x8900 : r Read Channel ADC Value (128 channel in a row) -- Debug Multiplexer 0x8020 : r/w Select Debug Entity @@ -121,3 +162,31 @@ 11: nx_event_buffer 12: nx_histograms + +--- Trigger Selction Window Setup + + _ +Physics Trigger [PT] _______________| |___________________________________ + _ +NX_TS_Trigger [NXT] ____________________| |______________________________ + _ +CTS Trigger [CT] _____________________________________| |_____________ + _ +FPGA TS Trigger [FT] _________________________________________| |_________ + | +CTS+FPGA Trigger Delay |--------------------| + | +FPGA TS-Ref stored | +in Event Header -----------|--------------------| + | +Trigger Window Offset(-) |----------| | +Trigger Window Width(-) |----------------| | +Timestamps stored in Event(-) |--|---|--|-||--|---------------| + | | + | | +Trigger Window Offset(+) |-----| | +Trigger Window Width(+) |---------| | +Timestamps stored in Event(+) -----------------|--||--|-|-----| + + ---------------------------------------------------------------> Time t + diff --git a/users/cosy_test/config/nxyter/setup.sh b/users/cosy_test/config/nxyter/setup.sh index 79dc9e0..213463c 100755 --- a/users/cosy_test/config/nxyter/setup.sh +++ b/users/cosy_test/config/nxyter/setup.sh @@ -9,18 +9,8 @@ trbcmd w 0x3800 0x8101 0x01 # Write nxsetup.dat to memory and transfer to nx-i2c-registers trbcmd wm 0x3800 0x8200 0 nxsetup.dat -trbcmd w 0x3800 0x8241 1 -#enable Testmode -#trb_i2c w 0x3800 0x08 0x20 0x08 # bit0: enable test pulse - # bit2: test-polarity 0: negativ 1:positiv - # bit 3: enable test_trigger -#trb_i2c w 0x3800 0x08 0x21 0x0d # bit3: must be 1, bit 2: nxyter-polarity, - # bit 0-1: test puls channels: 0: 0,4, - # 1:1,5, 2:2,6, 3:3,7 - -# Threshold setting -#trb_i2c w 0x3800 0x08 18 0x80 +trbcmd w 0x3800 0x8212 150 # nx_ts_reset_start trbcmd w 0x3800 0x8102 0x01 @@ -30,10 +20,10 @@ echo "clear data fifo" trbcmd rm 0x3800 0x8600 4000 2>/dev/null # Set readout Mode -trbcmd w 0x3800 0x8180 0x00 # 0: normal mode 4: no TS Window mode -trbcmd w 0x3800 0x8181 50 # window offset 200ns -trbcmd w 0x3800 0x8182 200 # window width 800ns -trbcmd w 0x3800 0x8183 100 # CTS-Delay 400ns +trbcmd w 0x3800 0x8400 0x00 # 0: normal mode 4: no TS Window mode +trbcmd w 0x3800 0x8401 50 # window offset 200ns +trbcmd w 0x3800 0x8402 200 # window width 800ns +trbcmd w 0x3800 0x8403 100 # CTS-Delay 400ns # Decoder Settings trbcmd w 0x3800 0x8120 0 # reset all counters diff --git a/users/cosy_test/config/nxyter/test_fifo_flush.sh b/users/cosy_test/config/nxyter/test_fifo_flush.sh deleted file mode 100755 index bd1c48e..0000000 --- a/users/cosy_test/config/nxyter/test_fifo_flush.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -export PATH=/home/rich/TRB/trbsoft/trbnettools/binlocal:${PATH} - -./setup.sh -./disable_all.sh -./enable_channel.sh 0 -./enable_channel.sh 1 -./enable_channel.sh 2 -./enable_channel.sh 3 - -trbcmd w 0x3800 0x8180 4 - -./enable_testtrigger.sh -./display_channels.sh diff --git a/users/cosy_test/config/nxyter/trb3_setup.sh b/users/cosy_test/config/nxyter/trb3_setup.sh new file mode 100755 index 0000000..801366a --- /dev/null +++ b/users/cosy_test/config/nxyter/trb3_setup.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +echo "Loading nxyter read-out configuration" + +case $1 in + 0x38*) + board=$1 + ;; + *) + echo "Wrong board!" + exit + ;; +esac + + + +# i2c_sm_reset +trbcmd w $board 0x8100 0x01 +# i2c_reg_reset_start +trbcmd w $board 0x8101 0x01 + +# Write nxsetup.dat to memory and transfer to nx-i2c-registers +trbcmd wm $board 0x8200 0 nxsetup_$board.dat + +#trbcmd w $board 0x8212 150 # threshold, load from dat file + +# nx_ts_reset_start +trbcmd w $board 0x8102 0x01 + +# reset counters, flush FIFO +echo "clear data fifo" +trbcmd rm $board 0x8600 4000 2>/dev/null + +# Set readout Mode +trbcmd w $board 0x8400 0x00 # 0: normal mode 4: no TS Window mode +trbcmd w $board 0x8401 0 # window offset 200ns +trbcmd w $board 0x8402 250 # window width 800ns +trbcmd w $board 0x8403 125 # CTS-Delay 400ns + +# Decoder Settings +trbcmd w $board 0x8120 0 # reset all counters + +# Enable nxyter +trbcmd w $board 0x8103 0 + +#Debugging to test ADC alignment / reset feature +# sleep 1; +# trbcmd w $board 0x8501 1 + diff --git a/users/cosy_test/config/padiwa_cfg.sh b/users/cosy_test/config/padiwa_cfg.sh new file mode 100755 index 0000000..446fb42 --- /dev/null +++ b/users/cosy_test/config/padiwa_cfg.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +~/trbsoft/daqtools/padiwa.pl 0x3802 0 disable 0xfffe #only first channel active +~/trbsoft/daqtools/padiwa.pl 0x3802 0 monitor 0x18 #use or of all inputs, stretched to >16ns as trigger out +~/trbsoft/daqtools/padiwa.pl 0x3802 0 comp 0 #no temperature compensation +~/trbsoft/daqtools/padiwa.pl 0x3802 0 invert 0 #no inverter on inputs +~/trbsoft/daqtools/padiwa.pl 0x3802 0 stretch 0 #no stretching of raw signals +~/trbsoft/daqtools/padiwa.pl 0x3802 0 pwm 0 8a00 #pwm of first channel to 1.778mV + + + diff --git a/users/cosy_test/config/startup.sh b/users/cosy_test/config/startup.sh index f34edda..00ec78c 100755 --- a/users/cosy_test/config/startup.sh +++ b/users/cosy_test/config/startup.sh @@ -20,4 +20,7 @@ echo "++ nXYTER" echo "++ CTS" ./cts.sh echo "================================" +trbcmd i 0xffff +echo "================================" + echo "done, hit Enter to exit" diff --git a/users/cosy_test/config/trbstart.sh b/users/cosy_test/config/trbstart.sh index 6d12a46..609e9d5 100755 --- a/users/cosy_test/config/trbstart.sh +++ b/users/cosy_test/config/trbstart.sh @@ -8,7 +8,8 @@ echo "Setting up Start TRB" TRBNUM=129 #../../../tools/command_client.pl -e etraxp$TRBNUM -c 'spi_trbv2_rl /home/hadaq/start_and_veto/thresholds_test' -../../../tools/command_client.pl -e etraxp$TRBNUM -c 'spi_trbv2_rl /home/hadaq/start/run.cfg' +#../../../tools/command_client.pl -e etraxp$TRBNUM -c 'spi_trbv2_rl /home/hadaq/start/run.cfg' +../../../tools/command_client.pl -e etraxp$TRBNUM -c 'spi_trbv2_rl /home/hadaq/start/all_pmt.cfg' ../../../tools/command_client.pl -e etraxp$TRBNUM -c "cd /home/hadaq/scripts/; ./trbv2_TDCs_configure.sh ${TRBNUM}" -- 2.43.0