From 1400d8f4cb136b578c7a39db78bea775b93dfc9d Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 5 Feb 2010 11:07:48 +0000 Subject: [PATCH] *** empty log message *** --- pinout/shower_fpga3.lpf | 9 ++- special/spi_master.vhd | 5 +- trb_net16_endpoint_hades_cts.vhd | 5 +- trb_net16_endpoint_hades_full.vhd | 6 +- trb_net16_hub_base.vhd | 10 +-- trb_net16_hub_func.vhd | 2 + trb_net16_hub_streaming_port.vhd | 2 + trb_net16_regio_bus_handler.vhd | 4 ++ trb_net_components.vhd | 101 +++++++++++++++++++++++++++++- 9 files changed, 131 insertions(+), 13 deletions(-) diff --git a/pinout/shower_fpga3.lpf b/pinout/shower_fpga3.lpf index 5ae0967..90fa22d 100644 --- a/pinout/shower_fpga3.lpf +++ b/pinout/shower_fpga3.lpf @@ -1,3 +1,8 @@ +##################################################################### +# Default +##################################################################### + IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; + ##################################################################### # Clocks & Resets ##################################################################### @@ -397,7 +402,7 @@ ##################################################################### # Flash & Reboot Control ##################################################################### - LOCATE COMP "PROGRAMb" SITE "AG30"; # PGRAMN_F_3 + LOCATE COMP "PROGRAMb" SITE "D11"; # PGRAMN_F_3 IOBUF PORT "PROGRAMb" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "SPI_CLK_OUT" SITE "E20"; # L3_SPI_F3CLK @@ -440,6 +445,7 @@ # LOCATE COMP "INITN_F_3" SITE "AC24"; # LOCATE COMP "DONE_F_3" SITE "AF27"; # +#These pins are mirrored in RX/TX! VHDL uses right names. # LOCATE COMP "F1_100_RXN" SITE "B23"; # LOCATE COMP "F1_100_RXP" SITE "A23"; # LOCATE COMP "F1_100_TXN" SITE "B20"; @@ -464,5 +470,6 @@ COMMERCIAL ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; + BLOCK RD_DURING_WR_PATHS ; diff --git a/special/spi_master.vhd b/special/spi_master.vhd index 614690f..aa2519b 100755 --- a/special/spi_master.vhd +++ b/special/spi_master.vhd @@ -35,7 +35,10 @@ entity spi_master is end entity; architecture Behavioral of spi_master is - + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of Behavioral : architecture is "SPI_group"; -- Signals type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); diff --git a/trb_net16_endpoint_hades_cts.vhd b/trb_net16_endpoint_hades_cts.vhd index 86564ce..58fb7af 100644 --- a/trb_net16_endpoint_hades_cts.vhd +++ b/trb_net16_endpoint_hades_cts.vhd @@ -101,7 +101,7 @@ entity trb_net16_endpoint_hades_cts is GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick STAT_DEBUG_1 : out std_logic_vector(31 downto 0); STAT_DEBUG_2 : out std_logic_vector(31 downto 0) ); @@ -664,7 +664,8 @@ begin GLOBAL_TIME => GLOBAL_TIME_OUT, LOCAL_TIME => LOCAL_TIME_OUT, TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT, - TIMER_US_TICK => TIMER_US_TICK_OUT, + TIMER_US_TICK => TIMER_TICKS_OUT(0), + TIMER_MS_TICK => TIMER_TICKS_OUT(1), --Common Register in / out COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, COMMON_CTRL_REG_OUT => buf_REGIO_COMMON_CTRL_REG_OUT, diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 000eed7..bfd7377 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -128,8 +128,7 @@ entity trb_net16_endpoint_hades_full is GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond - + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick --Debugging & Status information STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); STAT_DEBUG_1 : out std_logic_vector (31 downto 0); @@ -535,7 +534,8 @@ begin GLOBAL_TIME => GLOBAL_TIME_OUT, LOCAL_TIME => LOCAL_TIME_OUT, TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT, - TIMER_US_TICK => TIMER_US_TICK_OUT, + TIMER_US_TICK => TIMER_TICKS_OUT(0), + TIMER_MS_TICK => TIMER_TICKS_OUT(1), --Common Register in / out COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, COMMON_CTRL_REG_OUT => buf_REGIO_COMMON_CTRL_REG_OUT, diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 2aa4c29..985fcb2 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -70,7 +70,7 @@ entity trb_net16_hub_base is INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); ONEWIRE : inout std_logic; - ONEWIRE_MONITOR_IN : in std_logic; + ONEWIRE_MONITOR_IN : in std_logic := '0'; ONEWIRE_MONITOR_OUT : out std_logic; COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs @@ -713,7 +713,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; ) port map( CLK => CLK, - RESET => RESET, + RESET => reset_i, CLK_EN => CLK_EN, INIT_DATAREADY_IN => HUB_INIT_DATAREADY_IN(next_point_num-1 downto first_point_num), INIT_DATA_IN => HUB_INIT_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH), @@ -884,12 +884,12 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 1, - PORT_ADDRESSES => (0 => x"C000", others => x"0000"), - PORT_ADDR_MASK => (0 => 14, others => 0) + PORT_ADDRESSES => (0 => x"8000", others => x"0000"), + PORT_ADDR_MASK => (0 => 15, others => 0) ) port map( CLK => CLK, - RESET => RESET, + RESET => reset_i, DAT_ADDR_IN => DAT_ADDR_OUT, DAT_DATA_IN => DAT_DATA_OUT, diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 829cd6b..70de52b 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -247,6 +247,8 @@ component trb_net16_hub_streaming_port is COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs ONEWIRE : inout std_logic; ONEWIRE_MONITOR_IN : in std_logic; + ONEWIRE_MONITOR_OUT : out std_logic; + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); --REGIO INTERFACE REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd index 3fa6337..cbb2774 100644 --- a/trb_net16_hub_streaming_port.vhd +++ b/trb_net16_hub_streaming_port.vhd @@ -80,6 +80,7 @@ entity trb_net16_hub_streaming_port is COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs ONEWIRE : inout std_logic; ONEWIRE_MONITOR_IN : in std_logic; + ONEWIRE_MONITOR_OUT : out std_logic; MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); --REGIO INTERFACE @@ -276,6 +277,7 @@ begin ONEWIRE => ONEWIRE, ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT, MY_ADDRESS_OUT => my_address, COMMON_CTRL_REGS => common_ctrl, COMMON_STAT_REGS => common_stat, diff --git a/trb_net16_regio_bus_handler.vhd b/trb_net16_regio_bus_handler.vhd index d51dff4..a08a0d7 100644 --- a/trb_net16_regio_bus_handler.vhd +++ b/trb_net16_regio_bus_handler.vhd @@ -46,6 +46,10 @@ end entity; architecture regio_bus_handler_arch of trb_net16_regio_bus_handler is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of regio_bus_handler_arch : architecture is "Bus_handler_group"; signal port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS; signal next_port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 1396e6f..68ff206 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -404,7 +404,7 @@ package trb_net_components is GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick --Debugging & Status information STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); @@ -421,7 +421,106 @@ package trb_net_components is + component trb_net16_endpoint_hades_cts is + generic( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + IBUF_DEPTH : channel_config_t := (1,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6); + INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR + CLOCK_FREQUENCY : integer range 1 to 200 := 100 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + --LVL1 trigger + TRG_SEND_IN : in std_logic; + TRG_TYPE_IN : in std_logic_vector (3 downto 0); + TRG_NUMBER_IN : in std_logic_vector (15 downto 0); + TRG_INFORMATION_IN : in std_logic_vector (23 downto 0); + TRG_RND_CODE_IN : in std_logic_vector (7 downto 0); + TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + TRG_BUSY_OUT : out std_logic; + + --IPU Channel + IPU_SEND_IN : in std_logic; + IPU_TYPE_IN : in std_logic_vector (3 downto 0); + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + IPU_RND_CODE_IN : in std_logic_vector (7 downto 0); + -- Receiver port + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + IPU_BUSY_OUT : out std_logic; + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + REGIO_ONEWIRE_INOUT : inout std_logic; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + REGIO_ONEWIRE_MONITOR_IN : in std_logic; + TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick + STAT_DEBUG_1 : out std_logic_vector(31 downto 0); + STAT_DEBUG_2 : out std_logic_vector(31 downto 0) + ); + + end component; -- 2.43.0