From 152349af0a3071cf28c8c9f41eb1af9c235e4ff8 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 23 Jun 2015 15:52:28 +0200 Subject: [PATCH] updated tdc slow control registers. made small corrections. --- trb3/TdcBuildingBlocks.tex | 2 ++ trb3/TdcDataFormat.tex | 2 +- trb3/TdcFeatures.tex | 2 +- trb3/TdcSlowControl.tex | 15 +++++++++------ trb3/TdcVersion.tex | 2 ++ 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/trb3/TdcBuildingBlocks.tex b/trb3/TdcBuildingBlocks.tex index ccc8547..026ccda 100644 --- a/trb3/TdcBuildingBlocks.tex +++ b/trb3/TdcBuildingBlocks.tex @@ -152,6 +152,8 @@ calibration. It is advised to separate the calibration data taking and physical event data taking, as the first event generated by the physical trigger after the calibration trigger might still have calibration data. + + This problem is fixed with the TDC version 2.1.2 \end{information} diff --git a/trb3/TdcDataFormat.tex b/trb3/TdcDataFormat.tex index 902f222..a12d3b4 100644 --- a/trb3/TdcDataFormat.tex +++ b/trb3/TdcDataFormat.tex @@ -155,7 +155,7 @@ The debug information sent is given in Table \ref{tab:tdcDebugWords}. \end{table} The debug words sent with DAQ can be accessed also via slow control registers -(see Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}). +(see Table \ref{tab:tdcStatusReg1}). \newpage diff --git a/trb3/TdcFeatures.tex b/trb3/TdcFeatures.tex index 6dffe20..1dfd23d 100644 --- a/trb3/TdcFeatures.tex +++ b/trb3/TdcFeatures.tex @@ -22,4 +22,4 @@ mode ('1'), the epoch and coarse counters are reset after each trigger window. If this bit is set to trigger-less mode ('0'), the epoch and coarse counters are never reset, unless there is a system wide reset. They will run until they have an overflow. \textbf{This feature is disabled the after tdc -version 2.0.0} +version 2.0.0, as it is obsolete for the analysis software.} diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex index 074d0c8..90a9fce 100644 --- a/trb3/TdcSlowControl.tex +++ b/trb3/TdcSlowControl.tex @@ -30,7 +30,7 @@ the control registers are given in Table \ref{tab:tdcControlReg}. & & 7-6 & reserved.\\ & & 8 & Resets the internal counters (active high).\\ & & 11-9 & reserved.\\ - & & 12 & Used to select the trigger mode. \textbf{0:} with trigger mode; \textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}). This feature is disabled after tdc\_v2.0.\\ + & & 12 & Used to select the trigger mode. \textbf{0:} with trigger mode; \textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}). \textbf{This feature is disabled after tdc\_v2.0.}\\ & & 13 & Used to reset the coarse counters. Setting this bit signals for the coarse counter reset but the action will take place with the arrival of the next valid trigger in order to synchronise the coarse counters in a large system.\\ & & 27-14 & reserved.\\ & & 31-28 & Used to divide the calibration hit frequency.\\ @@ -60,6 +60,10 @@ the control registers are given in Table \ref{tab:tdcControlReg}. & & & Possible values 0-124\\ & & 31-7 & reserved.\\ \hline + 0xc805 & Channel invert 1 & 31-0 & Invert channels 1-32\\ + \hline + 0xc806 & Channel invert 2 & 31-0 & Invert channels 33-64\\ + \hline \end{longtable} \end{center} @@ -189,11 +193,12 @@ The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1}. & & 7-4 & Debug word of the TDC write-out FSM (see \ref{tab:tdcWriteoutFsm})\\ & & 15-8 & Implemented channel number.\\ & & 16 & Reference time synchronised to 100~MHz TrbNet clock.\\ - & & 27-17 & reserved\\ + & & 27-17 & TDC version number\\ & & 31-28 & Trigger type\\ \hline - 0xc101 & Empty channels 1 & 31-0 & Empty signals of the channels 32-1\\ \hline - 0xc102 & Empty channels 2 & 31-0 & Empty signals of the channels 64-33\\ \hline + 0xc101 & Debug register & 3-0 & Debug word of the Trigger Handler FSM\\ \hline + & & 31-4 & reserved\\ \hline + 0xc102 & Trigger time & 31-0 & The first 32 bits of the trigger time (epoch \& coarse counter combination) measured by the reference channel\\ \hline 0xc103 & Trigger window controls & 10-0 & Trigger window width before the trigger with granularity of 5~ns\\ & & 15-11 & reserved\\ & & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\ @@ -229,8 +234,6 @@ The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1}. & & 31-24 & reserved\\ \hline 0xc112 & Finished number & 23-0 & Number of sent finished signals\\ & & 31-24 & reserved\\ \hline - 0xc113 & READ FSM history & 31-0 & History register for the last 8 states of the READ FSM debug word.\\ \hline - 0xc114 & WRITE FSM history & 31-0 & History register for the last 8 states of the WRITE FSM debug word.\\ \hline diff --git a/trb3/TdcVersion.tex b/trb3/TdcVersion.tex index de49fdc..02976af 100644 --- a/trb3/TdcVersion.tex +++ b/trb3/TdcVersion.tex @@ -13,6 +13,8 @@ \endlastfoot \hline tdc\_v2.2* & 08.03.2015 & Faster clock (400 MHz) for the delay line is used. \\ +\hline + tdc\_v2.1.5 & 22.06.2015 & Extra coarse counter reset register for higher frequency. \\ \hline tdc\_v2.1.4 & 17.06.2015 & Several bug fixes for the stretcher option. \\ \hline -- 2.43.0