From 1563b1811bf3ea630a9f0191ccf1bbcda062cf82 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Mon, 20 Apr 2015 18:51:12 +0200 Subject: [PATCH] Refine delay --- ADC/source/adc_processor_cfd_ch.vhd | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd index 82980b0..85b6b69 100644 --- a/ADC/source/adc_processor_cfd_ch.vhd +++ b/ADC/source/adc_processor_cfd_ch.vhd @@ -78,6 +78,9 @@ architecture arch of adc_processor_cfd_ch is signal delay_cfd_in : signed(RESOLUTION_SUB - 1 downto 0) := (others => '0'); signal delay_cfd_out : signed(RESOLUTION_SUB - 1 downto 0) := (others => '0'); + type delay_sub_t is array (1 downto 0) of subtracted_thresh_t; + signal delay_sub : delay_sub_t := (others => subtracted_thresh_t_INIT); + signal prod, prod_invert : product_thresh_t := product_thresh_t_INIT; signal prod_delay : signed(RESOLUTION_PROD - 1 downto 0) := (others => '0'); @@ -200,13 +203,17 @@ begin prod_delay <= resize(prod_delay_s, RESOLUTION_PROD); -- get rid of extra bit again -- undelayed chain: input is subtracted signal + -- however, undelayed chain is also a little bit delayed + -- to account for in/out registers of delay chain above + delay_sub(0) <= subtracted; + delay_sub(1) <= delay_sub(0); mult_s := signed(resize(CONF.CFDMult, CONF.CFDMult'length + 1)); -- add extra zero sign bit - prod_s := mult_s * subtracted.value; + prod_s := mult_s * delay_sub(1).value; prod.value <= resize(prod_s, RESOLUTION_PROD); -- get rid of extra bit again - prod.thresh <= subtracted.thresh; - + prod.thresh <= delay_sub(1).thresh; + -- invert - prod_invert.value <= -prod.value; + prod_invert.value <= -delay_prod.value; prod_invert.thresh <= prod.thresh; -- add both signals to generate the bipolar cfd signal -- 2.43.0