From 15b0cbc2263aafdee4b1f9af881c0a44c0163f36 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 15 Dec 2006 13:41:34 +0000 Subject: [PATCH] working from home, most likely not working, Ingo --- testbench/trb_net_dummy_apl.vhd | 54 ++- .../trb_net_dummy_apl_api_chain_testbench.vhd | 327 ++++++++++++++++++ trb_net_active_api.vhd | 3 +- 3 files changed, 379 insertions(+), 5 deletions(-) create mode 100644 testbench/trb_net_dummy_apl_api_chain_testbench.vhd diff --git a/testbench/trb_net_dummy_apl.vhd b/testbench/trb_net_dummy_apl.vhd index 4adb0db..c8f8c82 100644 --- a/testbench/trb_net_dummy_apl.vhd +++ b/testbench/trb_net_dummy_apl.vhd @@ -10,8 +10,9 @@ use work.trb_net_std.all; entity trb_net_dummy_apl is - generic (TARGET_ADDRESS : integer := x"ffff"; -- - COUNTER_WIDTH : integer := 3); -- width of dummy data + generic (TARGET_ADDRESS : integer := x"ffff"; + PREFILL_LENGTH : integer := 3; + TRANSFER_LENGTH : integer := 6); -- length of dummy data port( -- Misc @@ -46,7 +47,9 @@ END trb_net_dummy_apl; architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is - type SENDER_STATE is (IDLE, RUNNING, WAITING, READING, MY_ERROR); + type SENDER_STATE is (IDLE, RUNNING, WAITING, MY_ERROR); + signal current_state, next_state : SENDER_STATE; + signal next_counter, reg_counter : std_logic_vector(47 downto 0); begin @@ -54,7 +57,50 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is APL_DTYPE_OUT <= x"01"; APL_ERROR_PATTERN_OUT <= x"12345678"; APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; - + APL_DATA_OUT <= reg_counter; + APL_SHORT_TRANSFER_OUT <= '0'; + SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN) + begin -- process + APL_SEND_OUT = '0'; + next_state = MY_ERROR; + next_counter = reg_counter; + APL_WRITE_OUT = '0'; +------------------------------------------------------------------------- +-- IDLE +------------------------------------------------------------------------- + if current_state = IDLE then + if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then + next_state = RUNNING; + else + next_state = IDLE; + next_counter = reg_counter +1; + APL_WRITE_OUT = '1'; + end if; +----------------------------------------------------------------------- +-- RUNNING +----------------------------------------------------------------------- + elsif current_state = RUNNING then + APL_SEND_OUT = '1'; + if reg_counter = TRANSFER_LENGTH then + next_state = WAITING; + else + next_state = RUNNING; + if APL_FIFO_FULL_IN = '0' then + next_counter = reg_counter +1; + APL_WRITE_OUT = '1'; + end if; + end if; +----------------------------------------------------------------------- +-- WAITING +----------------------------------------------------------------------- + elsif current_state = WAITING then + if APL_RUN_IN = '1' then + next_state = WAITING; + else + next_state = IDLE; + end if; + end if; -- end state switch + end process; end trb_net_dummy_apl_arch; diff --git a/testbench/trb_net_dummy_apl_api_chain_testbench.vhd b/testbench/trb_net_dummy_apl_api_chain_testbench.vhd new file mode 100644 index 0000000..0b6c265 --- /dev/null +++ b/testbench/trb_net_dummy_apl_api_chain_testbench.vhd @@ -0,0 +1,327 @@ +library ieee; + +use ieee.std_logic_1164.all; + +USE ieee.std_logic_signed.ALL; + +USE ieee.std_logic_arith.ALL; + +USE std.textio.ALL; +USE ieee.std_logic_textio.ALL; + +entity trb_net_dummy_apl_api_chain_testbench is + +end trb_net_dummy_apl_api_chain_testbench; + +architecture trb_net_dummy_apl_api_chain_testbench_arch of trb_net_dummy_apl_api_chain_testbench is + + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + +component trb_net_active_api + + generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- + APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out + APL_READ_IN: in STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running + APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_INIT_DATAREADY_OUT: out STD_LOGIC; + INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_IN: in STD_LOGIC; + INT_INIT_DATAREADY_IN: in STD_LOGIC; + INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_OUT: out STD_LOGIC; + + INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out STD_LOGIC; + INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_IN: in STD_LOGIC; + INT_REPLY_DATAREADY_IN: in STD_LOGIC; + INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_OUT: out STD_LOGIC; + -- Status and control port + + -- not needed now, but later + + ); +END component; + +component trb_net_dummy_apl + generic (TARGET_ADDRESS : integer := x"ffff"; + PREFILL_LENGTH : integer := 3; + TRANSFER_LENGTH : integer := 6); -- length of dummy data + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_OUT: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_OUT: in STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_IN: out STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_OUT: in STD_LOGIC; -- + APL_DTYPE_OUT: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_OUT: in STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_IN: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_IN: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_IN: out STD_LOGIC; -- Data word is valid and might be read out + APL_READ_OUT: in STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_IN: out STD_LOGIC; -- Data transfer is running + APL_SEQNR_IN: out STD_LOGIC_VECTOR (7 downto 0); + ); +END component; + +signal apl_data_out_apl1: STD_LOGIC_VECTOR (47 downto 0); +signal apl_write_apl1: STD_LOGIC; +signal apl_fifo_full_apl1: STD_LOGIC; +signal apl_short_transfer_apl1: STD_LOGIC; +signal apl_dtype_apl1: STD_LOGIC_VECTOR (3 downto 0); +signal apl_error_pattern_apl1: STD_LOGIC_VECTOR (31 downto 0); +signal apl_send_apl1: STD_LOGIC; +signal apl_target_adress_apl1: STD_LOGIC_VECTOR (15 downto 0); +signal apl_data_in_apl1: STD_LOGIC_VECTOR (47 downto 0); +signal apl_typ_apl1: STD_LOGIC_VECTOR (2 downto 0); +signal apl_dataready_apl1: STD_LOGIC; +signal apl_read_apl1: STD_LOGIC; +signal apl_run_apl1: STD_LOGIC; +signal apl_seqnr_apl1: STD_LOGIC_VECTOR (7 downto 0); + +signal apl_data_out_apl2: STD_LOGIC_VECTOR (47 downto 0); +signal apl_write_apl2: STD_LOGIC; +signal apl_fifo_full_apl2: STD_LOGIC; +signal apl_short_transfer_apl2: STD_LOGIC; +signal apl_dtype_apl2: STD_LOGIC_VECTOR (3 downto 0); +signal apl_error_pattern_apl2: STD_LOGIC_VECTOR (31 downto 0); +signal apl_send_apl2: STD_LOGIC; +signal apl_target_adress_apl2: STD_LOGIC_VECTOR (15 downto 0); +signal apl_data_in_apl2: STD_LOGIC_VECTOR (47 downto 0); +signal apl_typ_apl2: STD_LOGIC_VECTOR (2 downto 0); +signal apl_dataready_apl2: STD_LOGIC; +signal apl_read_apl2: STD_LOGIC; +signal apl_run_apl2: STD_LOGIC; +signal apl_seqnr_apl2: STD_LOGIC_VECTOR (7 downto 0); + +begin + + + clk <= not clk after 10ns; + + + + DO_RESET : process + begin + reset <= '1'; + wait for 30ns; + reset <= '0'; + wait; + end process DO_RESET; + +------------------------------------------------------------------------------- +-- the 2 APLs +------------------------------------------------------------------------------- + +APL1: trb_net_dummy_apl + generic map ( + TARGET_ADDRESS => 1, + PREFILL_LENGTH => 0, + TRANSFER_LENGTH => 2) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- APL Transmitter port + APL_DATA_OUT => apl_data_out_apl1, + APL_WRITE_OUT => apl_write_apl1, + APL_FIFO_FULL_IN => apl_fifo_full_apl1, + APL_SHORT_TRANSFER_OUT => apl_short_transfer_apl1, + APL_DTYPE_OUT => apl_dtype_apl1, + APL_ERROR_PATTERN_OUT => apl_error_pattern_apl1, + APL_SEND_OUT => apl_send_apl1, + APL_TARGET_ADDRESS_OUT => apl_target_adress_apl1, + + -- Receiver port + APL_DATA_IN => apl_data_in_apl1, + APL_TYP_IN => apl_typ_apl1, + APL_DATAREADY_IN => apl_dataready_apl1, + APL_READ_OUT => apl_read_apl1, + + -- APL Control port + APL_RUN_IN => apl_run_apl1, + APL_SEQNR_IN => apl_seqnr_apl1 + ); + +APL2: trb_net_dummy_apl + generic map ( + TARGET_ADDRESS => 1, + PREFILL_LENGTH => 0, + TRANSFER_LENGTH => 2) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- APL Transmitter port + APL_DATA_OUT => apl_data_out_apl2, + APL_WRITE_OUT => apl_write_apl2, + APL_FIFO_FULL_IN => apl_fifo_full_apl2, + APL_SHORT_TRANSFER_OUT => apl_short_transfer_apl2, + APL_DTYPE_OUT => apl_dtype_apl2, + APL_ERROR_PATTERN_OUT => apl_error_pattern_apl2, + APL_SEND_OUT => apl_send_apl2, + APL_TARGET_ADDRESS_OUT => apl_target_adress_apl2, + + -- Receiver port + APL_DATA_IN => apl_data_in_apl2, + APL_TYP_IN => apl_typ_apl2, + APL_DATAREADY_IN => apl_dataready_apl2, + APL_READ_OUT => apl_read_apl2, + + -- APL Control port + APL_RUN_IN => apl_run_apl2, + APL_SEQNR_IN => apl_seqnr_apl2 + ); + +------------------------------------------------------------------------------- +-- the 2 APIs +------------------------------------------------------------------------------- + +API1: trb_net_active_api + generic map ( + TRANSFER_LENGTH => 2) + port map ( + -- APL Transmitter port + APL_DATA_IN => apl_data_out_apl1, + APL_WRITE_IN => apl_write_apl1, + APL_FIFO_FULL_OUT => apl_fifo_full_apl1, + APL_SHORT_TRANSFER_IN => apl_short_transfer_apl1, + APL_DTYPE_IN => apl_dtype_apl1, + APL_ERROR_PATTERN_IN => apl_error_pattern_apl1, + APL_SEND_IN => apl_send_apl1, + APL_TARGET_ADDRESS_IN => apl_target_adress_apl1, + + -- Receiver port + APL_DATA_OUT => apl_data_in_apl1, + APL_TYP_OUT => apl_typ_apl1, + APL_DATAREADY_OUT => apl_dataready_apl1, + APL_READ_IN => apl_read_apl1, + + -- APL Control port + APL_RUN_OUT => apl_run_apl1, + APL_SEQNR_OUT => apl_seqnr_apl1, + + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_1_to_2, + INT_INIT_DATA_OUT => INT_INIT_DATA_1_to_2, + INT_INIT_READ_IN => INT_INIT_READ_1_to_2, + INT_INIT_DATAREADY_IN => INT_INIT_DATAREADY_2_to_1, + INT_INIT_DATA_IN => INT_INIT_DATA_2_to_1, + INT_INIT_READ_OUT => INT_INIT_READ_2_to_1, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_1_to_2, + INT_REPLY_DATA_OUT => INT_REPLY_DATA_1_to_2, + INT_REPLY_READ_IN => INT_REPLY_READ_1_to_2, + INT_REPLY_DATAREADY_IN => INT_REPLY_DATAREADY_2_to_1, + INT_REPLY_DATA_IN => INT_REPLY_DATA_2_to_1, + INT_REPLY_READ_OUT => INT_REPLY_READ_2_to_1 + ); + +API2: trb_net_active_api + generic map ( + TRANSFER_LENGTH => 2) + port map ( + -- APL Transmitter port + APL_DATA_IN => apl_data_out_apl2, + APL_WRITE_IN => apl_write_apl2, + APL_FIFO_FULL_OUT => apl_fifo_full_apl2, + APL_SHORT_TRANSFER_IN => apl_short_transfer_apl2, + APL_DTYPE_IN => apl_dtype_apl2, + APL_ERROR_PATTERN_IN => apl_error_pattern_apl2, + APL_SEND_IN => apl_send_apl2, + APL_TARGET_ADDRESS_IN => apl_target_adress_apl2, + + -- Receiver port + APL_DATA_OUT => apl_data_in_apl2, + APL_TYP_OUT => apl_typ_apl2, + APL_DATAREADY_OUT => apl_dataready_apl2, + APL_READ_IN => apl_read_apl2, + + -- APL Control port + APL_RUN_OUT => apl_run_apl2, + APL_SEQNR_OUT => apl_seqnr_apl2, + + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_2_to_1, + INT_INIT_DATA_OUT => INT_INIT_DATA_2_to_1, + INT_INIT_READ_IN => INT_INIT_READ_2_to_1, + INT_INIT_DATAREADY_IN => INT_INIT_DATAREADY_1_to_2, + INT_INIT_DATA_IN => INT_INIT_DATA_1_to_2, + INT_INIT_READ_OUT => INT_INIT_READ_1_to_2, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_2_to_1, + INT_REPLY_DATA_OUT => INT_REPLY_DATA_2_to_1, + INT_REPLY_READ_IN => INT_REPLY_READ_2_to_1, + INT_REPLY_DATAREADY_IN => INT_REPLY_DATAREADY_1_to_2, + INT_REPLY_DATA_IN => INT_REPLY_DATA_1_to_2, + INT_REPLY_READ_OUT => INT_REPLY_READ_1_to_2 + ); + +end trb_net_dummy_apl_api_chain_testbench_arch; + + +-- fuse -prj trb_net_active_api_testbench_beh.prj -top trb_net_active_api_testbench -o trb_net_active_api_testbench + +-- trb_net_active_api_testbench -tclbatch testsim.tcl + +-- ntrace select -o on -m / -l this +-- ntrace start +-- run 1000 ns +-- quit + +-- isimwave isimwavedata.xwv + diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd index 5a879ec..239a80b 100644 --- a/trb_net_active_api.vhd +++ b/trb_net_active_api.vhd @@ -192,7 +192,8 @@ CHECK_BUFFER: if FIFO_TERM_BUFFER_DEPTH >0 generate end generate CHECK_BUFFER; FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_INIT_DATA_IN, - INT_INIT_DATAREADY_IN, tb_next_registered_trailer, tb_registered_trailer, + INT_INIT_DATAREADY_IN, tb_next_registered_trailer, + tb_registered_trailer, fifo_term_buffer_empty, fifo_term_buffer_data_out, INT_REPLY_READ_IN, tb_registered_target) begin -- process -- 2.43.0