From 15f8d66b588fc9945e2053ed2ba4020de5fce9ac Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Wed, 15 Oct 2014 12:07:58 +0200 Subject: [PATCH] CBMNet: Test design adopted to new cbmnet_bridge component --- cbmnet/trb3_periph_cbmnet.lpf | 74 --- cbmnet/trb3_periph_cbmnet.prj | 67 +- cbmnet/trb3_periph_cbmnet.vhd | 743 +++++----------------- cbmnet/trb3_periph_cbmnet_constraints.lpf | 355 +---------- cbmnet/trb3_periph_cbmnet_syn.fdc | 60 ++ cts/compile_constraints.pl | 2 +- 6 files changed, 275 insertions(+), 1026 deletions(-) delete mode 100644 cbmnet/trb3_periph_cbmnet.lpf create mode 100644 cbmnet/trb3_periph_cbmnet_syn.fdc diff --git a/cbmnet/trb3_periph_cbmnet.lpf b/cbmnet/trb3_periph_cbmnet.lpf deleted file mode 100644 index a4f272d..0000000 --- a/cbmnet/trb3_periph_cbmnet.lpf +++ /dev/null @@ -1,74 +0,0 @@ -SYSCONFIG MCCLK_FREQ=20 ; -# FREQUENCY NET "THE_CBM_PHY/CLK_TX_FULL_I" 250 MHz; -#FREQUENCY NET "THE_CBM_PHY/RCLK_250_I" 250.000000 MHz ; -#Change the next two lines to the clk_fast signal of the ADC -# USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0"; -# USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0"; -#USE PRIMARY NET "CLK_GPLL_LEFT" ; -# USE PRIMARY NET "THE_CBM_PHY/RCLK_250_I"; -# USE SECONDARY NET "THE_CBM_PHY/CLK_TX_FULL_I"; -################################################################# -# Reset Nets -################################################################# -#GSR_NET NET "GSR_N"; -################################################################ -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ; -REGION "MEDIA_UPLINK" "R102C95D" 13 25 DEVSIZE; -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; -LOCATE COMP "THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSB" ; -#LOCATE COMP "THE_CBM_PHY/GEN_EASY_SERDES/THE_EASY_SERDES/PCSD_INST" SITE "PCSB" ; - -REGION "CBM_PHY" "R102C49D" 13 30; -LOCATE UGROUP "THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY"; - - - -################################################################# -# Relax some of the timing constraints -################################################################# - -FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ; -FREQUENCY PORT "CLK_GPLL_LEFT" 125.0 MHz; -FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; -FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; -FREQUENCY NET "THE_CBM_PHY/THE_RX_GEAR/rclk_125_i_c" 125.0 MHz; -FREQUENCY NET "THE_CBM_PHY/CLK_RX_FULL_OUT" 250.0 MHz; -FREQUENCY NET "THE_CBM_PHY/clk_tx_full_i" 250.0 MHz; -FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/un1_THE_MEDIA_UPLINK_1_c" 100.0 MHz; -FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; -FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; -FREQUENCY PORT "TRIGGER_LEFT" 125.0 MHz; - -DEFINE BUS "rx_data" NET "THE_CBM_PHY/rx_data_from_serdes_i[0]" NET "THE_CBM_PHY/rx_data_from_serdes_i[1]" NET "THE_CBM_PHY/rx_data_from_serdes_i[2]" NET "THE_CBM_PHY/rx_data_from_serdes_i[3]" NET "THE_CBM_PHY/rx_data_from_serdes_i[4]" NET "THE_CBM_PHY/rx_data_from_serdes_i[5]" NET "THE_CBM_PHY/rx_data_from_serdes_i[6]" NET "THE_CBM_PHY/rx_data_from_serdes_i[7]" NET "THE_CBM_PHY/rx_data_from_serdes_i[8]"; -DEFINE BUS "tx_data" NET "THE_CBM_PHY/tx_data_to_serdes_i[0]" NET "THE_CBM_PHY/tx_data_to_serdes_i[1]" NET "THE_CBM_PHY/tx_data_to_serdes_i[2]" NET "THE_CBM_PHY/tx_data_to_serdes_i[3]" NET "THE_CBM_PHY/tx_data_to_serdes_i[4]" NET "THE_CBM_PHY/tx_data_to_serdes_i[5]" NET "THE_CBM_PHY/tx_data_to_serdes_i[6]" NET "THE_CBM_PHY/tx_data_to_serdes_i[7]" NET "THE_CBM_PHY/tx_data_to_serdes_i[8]"; - -PRIORITIZE BUS "rx_data" 100; -PRIORITIZE BUS "tx_data" 100; - -#MULTICYCLE TO CELL "THE_CBM_PHY/THE_TX_GEAR/data_in_buf250_0_i*" 2 X; -#MULTICYCLE TO CELL "THE_CBM_PHY/THE_RX_GEAR/delay_clock_buf_i" 2 X; -#MULTICYCLE TO CELL "THE_CBM_PHY/THE_RX_GEAR/data_out_buf125_i*" 2 X; - - -#PROHIBIT PRIMARY NET "THE_CBM_PHY/un1_THE_CBM_PHY" ; -#PROHIBIT SECONDARY NET "THE_CBM_PHY/un1_THE_CBM_PHY" ; -#PROHIBIT PRIMARY NET "THE_CBM_PHY/clk_tx_full_i" ; -#PROHIBIT SECONDARY NET "THE_CBM_PHY/clk_tx_full_i" ; - -UGROUP "CBM_PHY_UGROUP" BBOX 13 26 - BLKNAME THE_CBM_PHY - BLKNAME THE_CBM_PHY/THE_RX_GEAR - BLKNAME THE_CBM_PHY/THE_TX_GEAR; -LOCATE UGROUP "CBM_PHY_UGROUP" SITE "R105C110D" ; - -UGROUP "CBMNET_group" BBOX 36 50 -# BLKNAME THE_CBMNET_READOUT - BLKNAME THE_CBM_ENDPOINT - BLKNAME THE_DLM_REFLECT - BLKNAME THE_SYNC_MODULE; -LOCATE UGROUP "CBMNET_group" SITE "R80C85D" ; - - -BLOCK PATH TO CELL "phy_debug_i_buf*" ; \ No newline at end of file diff --git a/cbmnet/trb3_periph_cbmnet.prj b/cbmnet/trb3_periph_cbmnet.prj index 583a9b6..472a322 100755 --- a/cbmnet/trb3_periph_cbmnet.prj +++ b/cbmnet/trb3_periph_cbmnet.prj @@ -41,31 +41,31 @@ add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_init add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_wrapper.v" add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_async_input_sync.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/dlm_reflect.v" - - -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_crc_generator.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_in.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_out.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in_decode.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init_fsm.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_out.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_packet_gen.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_buffer.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_fsm.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service_ctrl.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_slave_top.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_top.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer_fsm.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_fsm.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v" -add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/dlm_mixed/dlm_reflect.v" + +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_crc_gen.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_init_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_init.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer_read_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer_read.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer_write_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_dlm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_service.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_top.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_buffer_read_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_buffer.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_buffer_write_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_dlm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_out_arbiter_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_out.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_service.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx.v" + +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_random_stopper.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_send_fsm.v" +add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_fe.v" add_file -vhdl -lib work "./version.vhd" @@ -179,7 +179,12 @@ add_file -vhdl -lib work "./code/cbmnet_readout_tx_fifo.vhd" add_file -vhdl -lib work "./code/cbmnet_readout_obuf.vhd" add_file -vhdl -lib work "./code/cbmnet_readout.vhd" -add_file -fpga_constraint "./project/trb3_periph_cbmnet_syn.fdc" +add_file -vhdl -lib work "./code/pos_edge_strech_sync.vhd" +add_file -vhdl -lib work "./code/cbmnet_sync_module.vhd" +add_file -vhdl -lib work "./code/cbmnet_bridge.vhd" + + +add_file -fpga_constraint "./trb3_periph_cbmnet_syn.fdc" #implementation: "workdir" @@ -209,10 +214,10 @@ set_option -write_verilog 0 set_option -write_vhdl 1 # Lattice XP -set_option -maxfan 100 +set_option -maxfan 500 set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 0 +set_option -retiming 1 +set_option -pipe 1 set_option -forcegsr false set_option -fixgatedclocks 0 set_option -fixgeneratedclocks 0 @@ -220,7 +225,7 @@ set_option -update_models_cp 0 # NFilter set_option -popfeed 0 -set_option -constprop 0 +set_option -constprop 1 set_option -createhierarchy 0 # sequential_optimization_options @@ -231,7 +236,7 @@ set_option -compiler_compatible 1 set_option -resource_sharing 0 #automatic place and route (vendor) options -set_option -write_apr_constraint 0 +set_option -write_apr_constraint 1 #set result format/file last project -result_file "./workdir/trb3_periph_cbmnet.edf" diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd index f684680..cecfb98 100755 --- a/cbmnet/trb3_periph_cbmnet.vhd +++ b/cbmnet/trb3_periph_cbmnet.vhd @@ -254,53 +254,9 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal time_counter : unsigned(31 downto 0); -- CBMNet signals - constant NUM_LANES : integer := 1; signal cbm_res_n : std_logic; -- Active low reset; can be changed by define signal cbm_link_active : std_logic; -- link is active and can send and receive data - signal cbm_ctrl2send_stop : std_logic := '0'; -- send control interface - signal cbm_ctrl2send_start : std_logic := '0'; - signal cbm_ctrl2send_end : std_logic := '0'; - signal cbm_ctrl2send : std_logic_vector(15 downto 0) := (others => '0'); - - signal cbm_data2send_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); -- send data interface - signal cbm_data2send_start : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); - signal cbm_data2send_end : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); - signal cbm_data2send : std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0'); - - signal cbm_data2send_start1 : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); - signal cbm_data2send_end1 : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); - signal cbm_data2send1 : std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0'); - - signal cbm_data2send_start2 : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); - signal cbm_data2send_end2 : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); - signal cbm_data2send2 : std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0'); - - - signal cbm_dlm2send_va : std_logic := '0'; -- send dlm interface - signal cbm_dlm2send : std_logic_vector(3 downto 0) := (others => '0'); - - signal cbm_dlm_rec_type : std_logic_vector(3 downto 0) := (others => '0'); -- receive dlm interface - signal cbm_dlm_rec_va : std_logic := '0'; - - signal cbm_data_rec : std_logic_vector((16*NUM_LANES)-1 downto 0); -- receive data interface - signal cbm_data_rec_start : std_logic_vector(NUM_LANES-1 downto 0); - signal cbm_data_rec_end : std_logic_vector(NUM_LANES-1 downto 0); - signal cbm_data_rec_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others =>'0'); - - signal cbm_ctrl_rec : std_logic_vector(15 downto 0); -- receive control interface - signal cbm_ctrl_rec_start : std_logic; - signal cbm_ctrl_rec_end : std_logic; - signal cbm_ctrl_rec_stop : std_logic; - - signal cbm_data_from_link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface from the PHY - signal cbm_data2link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface to the PHY - - signal cbm_link_activeovr : std_logic := '0'; -- Overrides; set 0 by default - signal cbm_link_readyovr : std_logic := '0'; - - signal cbm_SERDES_ready : std_logic; -- signalize when PHY ready - signal phy_stat_op, phy_ctrl_op : std_logic_vector(15 downto 0) := (others => '0'); signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0'); @@ -309,27 +265,8 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal tp_mux_i : std_logic; --- Link Tester - signal link_tester_ctrl_en :std_logic; - signal link_tester_dlm_en :std_logic; - signal link_tester_data_en :std_logic; - - signal link_tester_data_stop :std_logic; - signal link_tester_ctrl_stop :std_logic; - - signal link_tester_data_valid:std_logic; - signal link_tester_ctrl_valid:std_logic; - signal link_tester_dlm_valid :std_logic; - - - signal link_tester_ctrl : std_logic_vector(31 downto 0) := (others => '0'); - signal link_tester_stat : std_logic_vector(31 downto 0) := (others => '0'); - signal dummy : std_logic; - type SEND_FSM_T is (START, SEND_HEADER, SEND_PACK_NUM, SEND_LENGTH, SEND_DATA, SEND_FOOTER, AFTER_SEND_WAIT); - signal send_fsm_i : SEND_FSM_T; --- signal send_length_i : unsigned(4 downto 0); signal send_num_pack_counter_i : unsigned(15 downto 0); signal send_enabled_i : std_logic := '0'; @@ -342,53 +279,6 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal dlm_counter_i : unsigned(31 downto 0); signal dlm_glob_counter_i : unsigned(31 downto 0); - - -- diagnostics Lane0 - signal cbm_crc_error_cntr_flag_0 : std_logic; - signal cbm_retrans_cntr_flag_0 : std_logic; - signal cbm_retrans_error_cntr_flag_0 : std_logic; - signal cbm_crc_error_cntr_0 : std_logic_vector(15 downto 0); - signal cbm_retrans_cntr_0 : std_logic_vector(15 downto 0); - signal cbm_retrans_error_cntr_0 : std_logic_vector(15 downto 0); - signal cbm_crc_error_cntr_clr_0 : std_logic; - signal cbm_retrans_cntr_clr_0 : std_logic; - signal cbm_retrans_error_cntr_clr_0 : std_logic; - - -- diagnostics Lane1 - signal cbm_crc_error_cntr_flag_1 : std_logic; - signal cbm_retrans_cntr_flag_1 : std_logic; - signal cbm_retrans_error_cntr_flag_1 : std_logic; - signal cbm_crc_error_cntr_1 : std_logic_vector(15 downto 0); - signal cbm_retrans_cntr_1 : std_logic_vector(15 downto 0); - signal cbm_retrans_error_cntr_1 : std_logic_vector(15 downto 0); - signal cbm_crc_error_cntr_clr_1 : std_logic; - signal cbm_retrans_cntr_clr_1 : std_logic; - signal cbm_retrans_error_cntr_clr_1 : std_logic; - - -- diagnostics Lane2 - signal cbm_crc_error_cntr_flag_2 : std_logic; - signal cbm_retrans_cntr_flag_2 : std_logic; - signal cbm_retrans_error_cntr_flag_2 : std_logic; - signal cbm_crc_error_cntr_2 : std_logic_vector(15 downto 0); - signal cbm_retrans_cntr_2 : std_logic_vector(15 downto 0); - signal cbm_retrans_error_cntr_2 : std_logic_vector(15 downto 0); - signal cbm_crc_error_cntr_clr_2 : std_logic; - signal cbm_retrans_cntr_clr_2 : std_logic; - signal cbm_retrans_error_cntr_clr_2 : std_logic; - - -- diagnostics Lane3 - signal cbm_crc_error_cntr_flag_3 : std_logic; - signal cbm_retrans_cntr_flag_3 : std_logic; - signal cbm_retrans_error_cntr_flag_3 : std_logic; - signal cbm_crc_error_cntr_3 : std_logic_vector(15 downto 0); - signal cbm_retrans_cntr_3 : std_logic_vector(15 downto 0); - signal cbm_retrans_error_cntr_3 : std_logic_vector(15 downto 0); - signal cbm_crc_error_cntr_clr_3 : std_logic; - signal cbm_retrans_cntr_clr_3 : std_logic; - signal cbm_retrans_error_cntr_clr_3 : std_logic; - - signal cbm_debug_overrides_i : std_logic_vector(1 downto 0) := "00"; - signal etm_trigger_i : std_logic; @@ -417,37 +307,11 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal gbe_fee_read : std_logic; signal gbe_fee_status_bits : std_logic_vector(31 downto 0); signal gbe_fee_busy : std_logic; - - - signal cbm_rdo_regio_addr_i : std_logic_vector(15 downto 0); - signal cbm_rdo_regio_data_status_i : std_logic_vector(31 downto 0); - signal cbm_rdo_regio_read_enable_i : std_logic; - signal cbm_rdo_regio_write_enable_i : std_logic; - signal cbm_rdo_regio_data_ctrl_i : std_logic_vector(31 downto 0); - signal cbm_rdo_regio_dataready_i : std_logic; - signal cbm_rdo_regio_write_ack_i : std_logic; - signal cbm_rdo_regio_unknown_addr_i : std_logic; - signal event_id : unsigned(31 downto 0); - signal send_length_i1 : unsigned(15 downto 0); - signal send_length_i2 : unsigned(15 downto 0); signal send_counter_i : unsigned(15 downto 0); - signal send_length_min_i : unsigned(15 downto 0); - signal send_length_max_i : unsigned(15 downto 0); - signal send_length_step_i : unsigned(15 downto 0); - signal send_length_cnt_i : unsigned(15 downto 0); - signal send_real_time_i : unsigned(31 downto 0); - signal send_real_time_buf_i : unsigned(31 downto 0); - - signal send_real_time125_i : unsigned(31 downto 0); - signal send_real_time125_xfer_i : unsigned(31 downto 0); - signal send_real_time125_buf_i : unsigned(31 downto 0); - - signal event_gap_i : unsigned(31 downto 0); - signal event_gap_cnt_i : unsigned(31 downto 0); type TRB_FSM_T is (IDLE, START_READOUT, START_READOUT_WAIT, FEE_BUSY, SEND_EINF_H, SEND_EINF_L, SEND_LENGTH, SEND_SOURCE, SEND_SOURCE_WAIT, @@ -456,73 +320,141 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is SEND_PAYLOAD_H, SEND_PAYLOAD_L, COMPL_WAIT, COMPL_NOT_BUSY_WAIT, EVT_WAIT); signal trb_fsm_i : TRB_FSM_T; + +signal event_id : unsigned(31 downto 0); +signal event_gap_i : unsigned(31 downto 0); +signal event_gap_cnt_i : unsigned(31 downto 0); + +signal send_length_min_i : unsigned(15 downto 0); +signal send_length_max_i : unsigned(15 downto 0); +signal send_length_step_i : unsigned(15 downto 0); +signal send_length_cnt_i : unsigned(15 downto 0); - signal rdo_send_length_min_i : unsigned(31 downto 0); - signal rdo_send_length_max_i : unsigned(31 downto 0); - signal rdo_send_length_inc_i : unsigned(31 downto 0); - signal rdo_send_length_cur_i : unsigned(31 downto 0); - type RDO_FSM_STATES_T is (UPDATE_LENGTH, WAIT_FOR_TRIGGER, SEND_RT_100, SEND_RT_125, SEND_TESTPATTERN, COMPLETE); - signal rdo_fsm_i : RDO_FSM_STATES_T; signal do_reboot_i : std_logic; - signal cbm_do_reboot_i : std_logic; - signal trb_crs_cbm_do_reboot_i : std_logic; + signal cbm_clk_i : std_logic; + signal cbm_reset_i : std_logic; + + signal cbm_sync_dlm_sensed_i : std_logic; + signal cbm_sync_pulser_i : std_logic; + signal cbm_sync_timing_trigger_i : std_logic; + + signal cbm_regio_addr_i : std_logic_vector(15 downto 0); + signal cbm_regio_status_data_i : std_logic_vector(31 downto 0); + signal cbm_regio_read_enable_i : std_logic; + signal cbm_regio_write_enable_i : std_logic; + signal cbm_regio_timeout_i : std_logic; + signal cbm_regio_control_data_i : std_logic_vector(31 downto 0); + signal cbm_regio_dataready_i : std_logic; + signal cbm_regio_write_ack_i : std_logic; + signal cbm_regio_no_more_data_i : std_logic; + signal cbm_regio_unknown_addr_i : std_logic; + -begin --- RDO_PROC: process is --- begin --- wait until rising_edge(clk_100_i); --- --- if reset_i='1' then --- rdo_fsm_i <= WAIT_FOR_TRIGGER; --- rdo_send_length_cur_i <= rdo_send_length_min_i; --- --- else --- case(rdo_fsm_i) is --- case UPDATE_LENGTH => --- case WAIT_FOR_TRIGGER => --- case SEND_RT_100 => --- case SEND_RT_125 => --- case SEND_TESTPATTERN => --- case COMPLETE => --- end case; --- end if; --- end process; + signal cbm_dbg_addr_i : std_logic_vector(15 downto 0); + signal cbm_dbg_status_data_i : std_logic_vector(31 downto 0); + signal cbm_dbg_read_enable_i : std_logic; + signal cbm_dbg_write_enable_i : std_logic; + signal cbm_dbg_timeout_i : std_logic; + signal cbm_dbg_control_data_i : std_logic_vector(31 downto 0); + signal cbm_dbg_dataready_i : std_logic; + signal cbm_dbg_write_ack_i : std_logic; + signal cbm_dbg_no_more_data_i : std_logic; + signal cbm_dbg_unknown_addr_i : std_logic; + + + +begin + PROC_RDO: process is + variable address : integer; + begin + wait until rising_edge(clk_100_i); + + address := to_integer(UNSIGNED(cbm_dbg_addr_i)); + + cbm_dbg_dataready_i <= cbm_dbg_read_enable_i; + cbm_dbg_write_ack_i <= cbm_dbg_write_enable_i; + cbm_dbg_unknown_addr_i <= '0'; + cbm_dbg_no_more_data_i <= '0'; + cbm_dbg_status_data_i <= (others => '0'); + + if reset_i = '1' then + send_length_min_i <= x"0010"; + send_length_max_i <= x"0800"; + send_length_step_i <= x"0001"; + send_enabled_i <= '0'; + event_gap_i <= x"00001000"; + + else + case address is + when 0 => + cbm_dbg_status_data_i(0) <= send_enabled_i; + cbm_dbg_status_data_i(1) <= cbm_link_active; + + when 1 => + cbm_dbg_status_data_i(15 downto 0) <= send_length_min_i; + + when 2 => + cbm_dbg_status_data_i(15 downto 0) <= send_length_max_i; + + when 3 => + cbm_dbg_status_data_i(15 downto 0) <= send_length_step_i; + + when 4 => + cbm_dbg_status_data_i <= event_id; + + when 5 => + cbm_dbg_status_data_i <= event_gap_i; + + when others => + cbm_dbg_unknown_addr_i <= '1'; + end case; + + if cbm_dbg_write_enable_i = '1' then + case address is + when 0 => + send_enabled_i <= cbm_dbg_status_data_i(0); + + when 1 => + send_length_min_i <= cbm_dbg_status_data_i(15 downto 0); + + when 2 => + send_length_max_i <= cbm_dbg_status_data_i(15 downto 0); + + when 3 => + send_length_step_i <= cbm_dbg_status_data_i(15 downto 0); + + when 5 => + event_gap_i <= cbm_dbg_status_data_i; + + when others => + cbm_dbg_write_ack_i <= '0'; + + end case; + end if; + end if; + end process; + clk_125_i <= CLK_GPLL_LEFT; assert(INCLUDE_TRBNET = c_YES); - - ---------------------------------------------------------------------------- --- CBMNet and PHY ---------------------------------------------------------------------------- - THE_CBM_PHY: cbmnet_phy_ecp3 - generic map (IS_SYNC_SLAVE => CBM_FEE_MODE, DETERMINISTIC_LATENCY => c_YES) + + THE_CBM_BRIDGE: cbmnet_bridge port map ( - CLK => clk_125_i, - RESET => reset_i, - CLEAR => '0', - - --Internal Connection TX - PHY_TXDATA_IN => cbm_data2link(15 downto 0), - PHY_TXDATA_K_IN => cbm_data2link(17 downto 16), + -- clock and reset + CLK125_IN => clk_125_i, -- in std_logic; + ASYNC_RESET_IN => clear_i, + TRB_CLK_IN => clk_100_i, -- in std_logic; + TRB_RESET_IN => reset_i, -- in std_logic; - --Internal Connection RX - PHY_RXDATA_OUT => cbm_data_from_link(15 downto 0), - PHY_RXDATA_K_OUT => cbm_data_from_link(17 downto 16), + CBM_CLK_OUT => cbm_clk_i, -- out std_logic; + CBM_RESET_OUT=> cbm_reset_i, -- out std_logic; - CLK_RX_HALF_OUT => rclk_125_i, - CLK_RX_FULL_OUT => rclk_250_i, - CLK_RX_RESET_OUT => rreset_i, - - LINK_ACTIVE_OUT => open, - SERDES_ready => cbm_SERDES_ready, - - --SFP Connection + -- Media Interface SD_RXD_P_IN => SD_RXD_P_IN, SD_RXD_N_IN => SD_RXD_N_IN, SD_TXD_P_OUT => SD_TXD_P_OUT, @@ -536,19 +468,13 @@ begin LED_TX_OUT => LED_TX(1), LED_OK_OUT => LED_LINKOK(1), - -- Status and control port - STAT_OP => phy_stat_op, - CTRL_OP => phy_ctrl_op, - DEBUG_OUT => phy_debug_i - ); - - TEST_LINE(2 downto 0) <= sync_pulser & sync_dlm_sense & trb_trigger; - + -- Status and strobes + CBM_LINK_ACTIVE_OUT => cbm_link_active, + CBM_DLM_OUT => cbm_sync_dlm_sensed_i, -- out std_logic; + CBM_TIMING_TRIGGER_OUT => cbm_sync_timing_trigger_i, -- out std_logic; + CBM_SYNC_PULSER_OUT => cbm_sync_pulser_i, -- out std_logic; - THE_SYNC_MODULE: cbmnet_sync_module port map ( - -- TRB - TRB_CLK_IN => clk_100_i, -- in std_logic; - TRB_RESET_IN => reset_i, -- in std_logic; + -- TRBNet Terminal TRB_TRIGGER_OUT => trb_trigger, -- out std_logic; --data output for read-out @@ -561,184 +487,7 @@ begin TRB_RDO_WRITE_OUT => fee_data_write_i, -- out std_logic; TRB_RDO_STATUSBIT_OUT => fee_trg_statusbits_i, -- out std_logic_vector(31 downto 0); TRB_RDO_FINISHED_OUT => fee_data_finished_i, -- out std_logic; - - -- reg io - TRB_REGIO_ADDR_IN(15 downto 4) => x"000", - TRB_REGIO_ADDR_IN(3 downto 0) => sync_regio_addr, -- in std_logic_vector(15 downto 0); - TRB_REGIO_DATA_IN => sync_regio_config_data, -- in std_logic_vector(31 downto 0); - TRB_REGIO_READ_ENABLE_IN => sync_regio_read_en, -- in std_logic; - TRB_REGIO_WRITE_ENABLE_IN => sync_regio_write_en, -- in std_logic; - TRB_REGIO_DATA_OUT => sync_regio_status_data, -- out std_logic_vector(31 downto 0); - TRB_REGIO_DATAREADY_OUT => sync_regio_read_ack, -- out std_logic; - TRB_REGIO_WRITE_ACK_OUT => sync_regio_write_ack, -- out std_logic; - TRB_REGIO_UNKNOWN_ADDR_OUT => sync_regio_unknown, -- out std_logic; - - -- CBMNET - CBM_CLK_IN => rclk_125_i, -- in std_logic; - CBM_CLK_250_IN => rclk_250_i, - CBM_LINK_ACTIVE_IN => cbm_link_active, - CBM_RESET_IN => rreset_i, -- in std_logic; - CBM_PHY_BARREL_SHIFTER_POS_IN => x"0", -- in std_logic_vector(3 downto 0); - - CBM_TIMING_TRIGGER_OUT => open, - - -- DLM port - CBM_DLM_REC_IN => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0); - CBM_DLM_REC_VALID_IN => cbm_dlm_rec_va, -- in std_logic; - CBM_DLM_SENSE_OUT => sync_dlm_sense, -- out std_logic; - CBM_PULSER_OUT => sync_pulser, -- out std_logic; -- connect to TDC - - -- Ctrl port - CBM_CTRL_DATA_IN => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0); - CBM_CTRL_DATA_START_IN => cbm_ctrl_rec_start, -- in std_logic; - CBM_CTRL_DATA_END_IN => cbm_ctrl_rec_end, -- in std_logic; - CBM_CTRL_DATA_STOP_OUT => cbm_ctrl_rec_stop, -- out std_logic; - - DEBUG_OUT => open -- out std_logic_vector(31 downto 0) - ); - - fee_trg_release_i <= fee_data_finished_i; - SFP_RATESEL <= (others => '0'); - - --TEST_LINE(1 downto 0) <= cbm_dlm2send_va & cbm_dlm_rec_va; - --- process is --- variable counter_v : unsigned(20 downto 0); --- begin --- wait until rising_edge(rclk_125_i); --- counter_v := counter_v + to_unsigned(1,1); --- cbm_dlm2send_va <= '0'; --- if counter_v = 0 then --- cbm_dlm2send_va <= '1'; --- end if; --- end process; --- - --- cbm_data2link <= "00" & x"dead"; - THE_CBM_ENDPOINT: lp_top - generic map ( - NUM_LANES => 1, - TX_SLAVE => 0 - ) - port map ( - -- Clk & Reset - clk => rclk_125_i, - res_n => cbm_res_n, - - -- Phy - data_from_link => cbm_data_from_link, - data2link => cbm_data2link, - link_activeovr => '0', --cbm_debug_overrides_i(0), - link_readyovr => '0', --cbm_debug_overrides_i(1), - SERDES_ready => cbm_SERDES_ready, - - -- CBMNet Interface - link_active => cbm_link_active, - ctrl2send_stop => cbm_ctrl2send_stop, - ctrl2send_start => cbm_ctrl2send_start, - ctrl2send_end => cbm_ctrl2send_end, - ctrl2send => cbm_ctrl2send, - - data2send_stop => cbm_data2send_stop, - data2send_start => cbm_data2send_start, - data2send_end => cbm_data2send_end, - data2send => cbm_data2send, - - dlm2send_va => cbm_dlm2send_va, - dlm2send => cbm_dlm2send, - - dlm_rec_type => cbm_dlm_rec_type, - dlm_rec_va => cbm_dlm_rec_va, - - data_rec => cbm_data_rec, - data_rec_start => cbm_data_rec_start, - data_rec_end => cbm_data_rec_end, - data_rec_stop => cbm_data_rec_stop, - - ctrl_rec => cbm_ctrl_rec, - ctrl_rec_start => cbm_ctrl_rec_start, - ctrl_rec_end => cbm_ctrl_rec_end, - ctrl_rec_stop => cbm_ctrl_rec_stop, - - -- diagnostics Lane0 - crc_error_cntr_flag_0 => cbm_crc_error_cntr_flag_0, -- out std_logic; - retrans_cntr_flag_0 => cbm_retrans_cntr_flag_0, -- out std_logic; - retrans_error_cntr_flag_0 => cbm_retrans_error_cntr_flag_0, -- out std_logic; - crc_error_cntr_0 => cbm_crc_error_cntr_0, -- out std_logic_vector(15 downto 0); - retrans_cntr_0 => cbm_retrans_cntr_0, -- out std_logic_vector(15 downto 0); - retrans_error_cntr_0 => cbm_retrans_error_cntr_0, -- out std_logic_vector(15 downto 0); - crc_error_cntr_clr_0 => cbm_crc_error_cntr_clr_0, -- in std_logic; - retrans_cntr_clr_0 => cbm_retrans_cntr_clr_0, -- in std_logic; - retrans_error_cntr_clr_0 => cbm_retrans_error_cntr_clr_0, -- in std_logic; - - -- diagnostics Lane1 - crc_error_cntr_flag_1 => open, -- out std_logic; - retrans_cntr_flag_1 => open, -- out std_logic; - retrans_error_cntr_flag_1 => open, -- out std_logic; - crc_error_cntr_1 => open, -- out std_logic_vector(15 downto 0); - retrans_cntr_1 => open, -- out std_logic_vector(15 downto 0); - retrans_error_cntr_1 => open, -- out std_logic_vector(15 downto 0); - crc_error_cntr_clr_1 => '0', -- in std_logic; - retrans_cntr_clr_1 => '0', -- in std_logic; - retrans_error_cntr_clr_1 => '0', -- in std_logic; - - -- diagnostics Lane2 - crc_error_cntr_flag_2 => open, -- out std_logic; - retrans_cntr_flag_2 => open, -- out std_logic; - retrans_error_cntr_flag_2 => open, -- out std_logic; - crc_error_cntr_2 => open, -- out std_logic_vector(15 downto 0); - retrans_cntr_2 => open, -- out std_logic_vector(15 downto 0); - retrans_error_cntr_2 => open, -- out std_logic_vector(15 downto 0); - crc_error_cntr_clr_2 => '0', -- in std_logic; - retrans_cntr_clr_2 => '0', -- in std_logic; - retrans_error_cntr_clr_2 => '0', -- in std_logic; - - -- diagnostics Lane3 - crc_error_cntr_flag_3 => open, -- out std_logic; - retrans_cntr_flag_3 => open, -- out std_logic; - retrans_error_cntr_flag_3 => open, -- out std_logic; - crc_error_cntr_3 => open, -- out std_logic_vector(15 downto 0); - retrans_cntr_3 => open, -- out std_logic_vector(15 downto 0); - retrans_error_cntr_3 => open, -- out std_logic_vector(15 downto 0); - crc_error_cntr_clr_3 => '0', -- in std_logic; - retrans_cntr_clr_3 => '0', -- in std_logic; - retrans_error_cntr_clr_3 => '0' -- in std_logic - - - ); - cbm_res_n <= not rreset_i when rising_edge(rclk_125_i); - - cbm_crc_error_cntr_clr_0 <= reset_i; - cbm_retrans_cntr_clr_0 <= reset_i; - cbm_retrans_error_cntr_clr_0 <= reset_i; - cbm_crc_error_cntr_clr_1 <= reset_i; - cbm_retrans_cntr_clr_1 <= reset_i; - cbm_retrans_error_cntr_clr_1 <= reset_i; - cbm_crc_error_cntr_clr_2 <= reset_i; - cbm_retrans_cntr_clr_2 <= reset_i; - cbm_retrans_error_cntr_clr_2 <= reset_i; - cbm_crc_error_cntr_clr_3 <= reset_i; - cbm_retrans_cntr_clr_3 <= reset_i; - cbm_retrans_error_cntr_clr_3 <= reset_i; - - THE_DLM_REFLECT: dlm_reflect port map ( - clk => rclk_125_i, -- in std_logic; - res_n => cbm_res_n, -- in std_logic; - dlm_rec_in => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0); - dlm_rec_va_in => cbm_dlm_rec_va, -- in std_logic; - dlm_rec_out => open, -- out std_logic_vector(3 downto 0); - dlm_rec_va_out => open, -- out std_logic; - dlm2send_va => cbm_dlm2send_va, -- out std_logic; - dlm2send => cbm_dlm2send -- out std_logic_vector(3 downto 0) - ); - - THE_CBMNET_READOUT: cbmnet_readout - port map ( - CLK_IN => clk_100_i, -- in std_logic; - RESET_IN => reset_i, -- in std_logic; - - -- connect to hub HUB_CTS_NUMBER_IN => hub_cts_number, -- in std_logic_vector (15 downto 0); HUB_CTS_CODE_IN => hub_cts_code, -- in std_logic_vector (7 downto 0); HUB_CTS_INFORMATION_IN => hub_cts_information, -- in std_logic_vector (7 downto 0); @@ -767,30 +516,26 @@ begin GBE_FEE_BUSY_OUT => gbe_fee_busy, -- out std_logic; -- reg io - REGIO_ADDR_IN => cbm_rdo_regio_addr_i, -- in std_logic_vector(15 downto 0); - REGIO_DATA_IN => cbm_rdo_regio_data_ctrl_i, -- in std_logic_vector(31 downto 0); - REGIO_READ_ENABLE_IN => cbm_rdo_regio_read_enable_i, -- in std_logic; - REGIO_WRITE_ENABLE_IN => cbm_rdo_regio_write_enable_i, -- in std_logic; - REGIO_DATA_OUT => cbm_rdo_regio_data_status_i, -- out std_logic_vector(31 downto 0); - REGIO_DATAREADY_OUT => cbm_rdo_regio_dataready_i, -- out std_logic; - REGIO_WRITE_ACK_OUT => cbm_rdo_regio_write_ack_i, -- out std_logic; - REGIO_UNKNOWN_ADDR_OUT => cbm_rdo_regio_unknown_addr_i, -- out std_logic; - - -- CBMNet - CBMNET_CLK_IN => rclk_125_i, -- in std_logic; - CBMNET_RESET_IN => rreset_i, -- in std_logic; - CBMNET_LINK_ACTIVE_IN => cbm_link_active, -- in std_logic; - - CBMNET_DATA2SEND_STOP_IN => cbm_data2send_stop(0), -- in std_logic; - CBMNET_DATA2SEND_START_OUT => cbm_data2send_start1(0), -- out std_logic; - CBMNET_DATA2SEND_END_OUT => cbm_data2send_end1(0), -- out std_logic; - CBMNET_DATA2SEND_DATA_OUT => cbm_data2send1 -- out std_logic_vector(15 downto 0) + REGIO_ADDR_IN => cbm_regio_addr_i, -- in std_logic_vector(15 downto 0); + REGIO_DATA_IN => cbm_regio_control_data_i, -- in std_logic_vector(31 downto 0); + REGIO_TIMEOUT_IN => cbm_regio_timeout_i, -- in std_logic; + REGIO_READ_ENABLE_IN => cbm_regio_read_enable_i, -- in std_logic; + REGIO_WRITE_ENABLE_IN => cbm_regio_write_enable_i, -- in std_logic; + REGIO_DATA_OUT => cbm_regio_status_data_i, -- out std_logic_vector(31 downto 0); + REGIO_DATAREADY_OUT => cbm_regio_dataready_i, -- out std_logic; + REGIO_WRITE_ACK_OUT => cbm_regio_write_ack_i, -- out std_logic; + REGIO_NO_MORE_DATA_OUT => cbm_regio_no_more_data_i, -- out std_logic; + REGIO_UNKNOWN_ADDR_OUT => cbm_regio_unknown_addr_i -- out std_logic; ); + + fee_trg_release_i <= fee_data_finished_i; + + SFP_RATESEL <= (others => '0'); gbe_fee_read <= '1'; gbe_cts_status_bits <= x"beafc0de"; - process is + PROC_TRB_DATA: process is variable wait_cnt_v : integer range 0 to 15 := 0; begin wait until rising_edge(clk_100_i); @@ -825,7 +570,6 @@ begin wait_cnt_v := 10; HUB_FEE_BUSY <= '0'; event_id <= event_id + 1; - send_real_time_buf_i <= send_real_time_i; when START_READOUT_WAIT => if wait_cnt_v = 0 then @@ -882,12 +626,12 @@ begin trb_fsm_i <= SEND_PAYLOAD_RT_H; when SEND_PAYLOAD_RT_H => - HUB_FEE_DATA <= std_logic_vector(send_real_time_buf_i(31 downto 16)); + HUB_FEE_DATA <= x"dead"; HUB_FEE_DATAREADY <= '1'; trb_fsm_i <= SEND_PAYLOAD_RT_L; when SEND_PAYLOAD_RT_L => - HUB_FEE_DATA <= std_logic_vector(send_real_time_buf_i(15 downto 0)); + HUB_FEE_DATA <= x"c0de"; HUB_FEE_DATAREADY <= '1'; trb_fsm_i <= SEND_PAYLOAD_H; send_counter_i <= send_counter_i - 1; @@ -951,158 +695,7 @@ begin end if; end process; - proc_real_time: process is - begin - wait until rising_edge(clk_100_i); - - if reset_i='1' then - send_real_time_i <= (others => '0'); - else - send_real_time_i <= send_real_time_i + 1; - end if; - end process; - - proc_real_time125: process is - begin - wait until rising_edge(rclk_125_i); - - if rreset_i='1' then - send_real_time125_i <= (others => '0'); - else - send_real_time125_i <= send_real_time125_i +1; - end if; - end process; - send_real_time125_xfer_i <= send_real_time125_i when rising_edge(clk_100_i); - - cbm_data2send <= cbm_data2send1; -- when tp_mux_i = '0' else cbm_data2send2; - cbm_data2send_start <= cbm_data2send_start1; -- when tp_mux_i = '0' else cbm_data2send_start2; - cbm_data2send_end <= cbm_data2send_end1; -- when tp_mux_i = '0' else cbm_data2send_end2; - - PROC_DLM_COUNTER: process is - variable dlm_type_v : integer range 15 downto 0; - begin - wait until rising_edge(rclk_125_i); - - if rreset_i = '1' then - dlm_counter_i <= (others => '0'); - dlm_glob_counter_i <= (others => '0'); - elsif cbm_dlm_rec_va = '1' then - dlm_glob_counter_i <= dlm_glob_counter_i + TO_UNSIGNED(1,1); - - dlm_type_v := to_integer(unsigned(cbm_dlm_rec_type)); - for i in 0 to 15 loop - if dlm_type_v = i then - dlm_counter_i(1+i*2 downto i*2) <= dlm_counter_i(1+i*2 downto i*2) + TO_UNSIGNED(1,1); - end if; - end loop; - end if; - end process; - - phy_debug_i_buf <= phy_debug_i when rising_edge(clk_100_i); - - - PROC_REGIO_DEBUG: process is - variable address : integer range 0 to 255; - begin - wait until rising_edge(clk_100_i); - address := to_integer(unsigned(debug_addr)); - - debug_data_out <= x"00000000"; - - debug_ack <= debug_read_en or debug_write_en; - case address is - when 16#0# => debug_data_out <= x"0000" & phy_stat_op; - when 16#1# => debug_data_out <= x"0000" & phy_ctrl_op; - when 16#2# => debug_data_out <= phy_stat_debug(31 downto 0); - when 16#3# => debug_data_out <= phy_stat_debug(63 downto 32); - when 16#4# => debug_data_out <= phy_ctrl_debug(31 downto 0); - when 16#5# => debug_data_out <= phy_ctrl_debug(63 downto 32); - when 16#6# => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32)); - - when 16#0f# => debug_data_out(15 downto 0) <= send_length_i1; - when 16#10# => debug_data_out <= event_gap_i; - when 16#11# => debug_data_out <= event_id; - - when 16#12# => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter_i); - when 16#13# => debug_data_out <= STD_LOGIC_VECTOR(dlm_glob_counter_i); - when 16#14# => - debug_data_out(21 downto 20) <= cbm_debug_overrides_i; - debug_data_out(19 downto 16) <= tp_mux_i & send_enabled_i & cbm_data2send_stop & cbm_link_active; - debug_data_out(15 downto 0) <= STD_LOGIC_VECTOR(send_num_pack_counter_i); - - - when 16#15# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_0; - when 16#16# => debug_data_out <= cbm_retrans_error_cntr_0 & cbm_retrans_cntr_0; - when 16#17# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_1; - when 16#18# => debug_data_out <= cbm_retrans_error_cntr_1 & cbm_retrans_cntr_1; - when 16#19# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_2; - when 16#1a# => debug_data_out <= cbm_retrans_error_cntr_2 & cbm_retrans_cntr_2; - when 16#1b# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_3; - when 16#1c# => debug_data_out <= cbm_retrans_error_cntr_3 & cbm_retrans_cntr_3; - - when 16#20# => debug_data_out <= phy_debug_i_buf(31+32*0 downto 32*0); - when 16#21# => debug_data_out <= phy_debug_i_buf(31+32*1 downto 32*1); - when 16#22# => debug_data_out <= phy_debug_i_buf(31+32*2 downto 32*2); - when 16#23# => debug_data_out <= phy_debug_i_buf(31+32*3 downto 32*3); - when 16#24# => debug_data_out <= phy_debug_i_buf(31+32*4 downto 32*4); - when 16#25# => debug_data_out <= phy_debug_i_buf(31+32*5 downto 32*5); - when 16#26# => debug_data_out <= phy_debug_i_buf(31+32*6 downto 32*6); - when 16#27# => debug_data_out <= phy_debug_i_buf(31+32*7 downto 32*7); - when 16#28# => debug_data_out <= phy_debug_i_buf(31+32*8 downto 32*8); - when 16#29# => debug_data_out <= phy_debug_i_buf(31+32*9 downto 32*9); - when 16#2a# => debug_data_out <= phy_debug_i_buf(31+32*10 downto 32*10); - when 16#2b# => debug_data_out <= phy_debug_i_buf(31+32*11 downto 32*11); - when 16#2c# => debug_data_out <= phy_debug_i_buf(31+32*12 downto 32*12); - when 16#2d# => debug_data_out <= phy_debug_i_buf(31+32*13 downto 32*13); - when 16#2e# => debug_data_out <= phy_debug_i_buf(31+32*14 downto 32*14); - when 16#2f# => debug_data_out <= phy_debug_i_buf(31+32*15 downto 32*15); - - when 16#30# => debug_data_out <= x"0000" & STD_LOGIC_VECTOR( send_length_min_i ); - when 16#31# => debug_data_out <= x"0000" & STD_LOGIC_VECTOR(send_length_max_i ); - when 16#32# => debug_data_out <= x"0000" & STD_LOGIC_VECTOR(send_length_step_i ); - when 16#33# => debug_data_out <= send_real_time_i; - send_real_time125_buf_i <= send_real_time125_xfer_i; - when 16#34# => debug_data_out <= send_real_time125_buf_i; - - when others => debug_ack <= '0'; - end case; - - if debug_write_en = '1' then - case (address) is - when 16#01# => phy_ctrl_op <= debug_data_in(15 downto 0); - when 16#04# => phy_ctrl_debug(31 downto 0) <= debug_data_in; - when 16#05# => phy_ctrl_debug(63 downto 32) <= debug_data_in; - when 16#0f# => - send_burst_threshold_i <= debug_data_in; - send_length_i1 <= debug_data_in(15 downto 0); - when 16#10# => event_gap_i <= debug_data_in; - when 16#14# => - send_enabled_i <= debug_data_in(18); - tp_mux_i <= debug_data_in(19); - --cbm_debug_overrides_i <= debug_data_in(21 downto 20); - - when 16#30# => - if UNSIGNED(debug_data_in(15 downto 0)) > 1 then - send_length_min_i <= UNSIGNED(debug_data_in(15 downto 0)); - end if; - when 16#31# => - if UNSIGNED(debug_data_in(15 downto 0)) < 1019 then - send_length_max_i <= UNSIGNED(debug_data_in(15 downto 0)); - end if; - - when 16#32# => - send_length_step_i <= UNSIGNED(debug_data_in(15 downto 0)); - when others => debug_ack <= '0'; - end case; - end if; - - if reset_i='1' then - send_length_step_i <= TO_UNSIGNED( 1, 16); - send_length_min_i <= TO_UNSIGNED( 2, 16); - send_length_max_i <= TO_UNSIGNED(200, 16); - end if; - end process; --------------------------------------------------------------------------- -- Reset Generation @@ -1310,8 +903,8 @@ begin THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"a000", 3=>x"a800", 4=>x"a900", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 6, 3=>6, 4=>4, others => 0) + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"a000", 3=>x"a800", 4=>x"aa00", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 6, 3=> 9, 4=>4, others => 0) ) port map( CLK => clk_100_i, @@ -1368,30 +961,30 @@ begin BUS_UNKNOWN_ADDR_IN(2) => '0', --CBMNet (read-out) - BUS_READ_ENABLE_OUT(3) => cbm_rdo_regio_read_enable_i, - BUS_WRITE_ENABLE_OUT(3) => cbm_rdo_regio_write_enable_i, - BUS_DATA_OUT(3*32+31 downto 3*32) => cbm_rdo_regio_data_ctrl_i, - BUS_ADDR_OUT(3*16+15 downto 3*16) => cbm_rdo_regio_addr_i, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => cbm_rdo_regio_data_status_i, - BUS_DATAREADY_IN(3) => cbm_rdo_regio_dataready_i, - BUS_WRITE_ACK_IN(3) => cbm_rdo_regio_write_ack_i, - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => cbm_rdo_regio_unknown_addr_i, + BUS_READ_ENABLE_OUT(3) => cbm_regio_read_enable_i, + BUS_WRITE_ENABLE_OUT(3) => cbm_regio_write_enable_i, + BUS_DATA_OUT(3*32+31 downto 3*32) => cbm_regio_control_data_i, + BUS_ADDR_OUT(3*16+15 downto 3*16) => cbm_regio_addr_i, + BUS_TIMEOUT_OUT(3) => cbm_regio_timeout_i, + BUS_DATA_IN(3*32+31 downto 3*32) => cbm_regio_status_data_i, + BUS_DATAREADY_IN(3) => cbm_regio_dataready_i, + BUS_WRITE_ACK_IN(3) => cbm_regio_write_ack_i, + BUS_NO_MORE_DATA_IN(3) => cbm_regio_no_more_data_i, + BUS_UNKNOWN_ADDR_IN(3) => cbm_regio_unknown_addr_i, + --CBMNet (read-out) - BUS_READ_ENABLE_OUT(4) => sync_regio_read_en, - BUS_WRITE_ENABLE_OUT(4) => sync_regio_write_en, - BUS_DATA_OUT(4*32+31 downto 4*32) => sync_regio_config_data, - BUS_ADDR_OUT(4*16+3 downto 4*16) => sync_regio_addr, - BUS_ADDR_OUT(4*16+15 downto 4*16+4) => open, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => sync_regio_status_data, - BUS_DATAREADY_IN(4) => sync_regio_read_ack, - BUS_WRITE_ACK_IN(4) => sync_regio_write_ack, - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => sync_regio_unknown, - + BUS_READ_ENABLE_OUT(4) => cbm_dbg_read_enable_i, + BUS_WRITE_ENABLE_OUT(4) => cbm_dbg_write_enable_i, + BUS_DATA_OUT(4*32+31 downto 4*32) => cbm_dbg_control_data_i, + BUS_ADDR_OUT(4*16+15 downto 4*16) => cbm_dbg_addr_i, + BUS_TIMEOUT_OUT(4) => cbm_dbg_timeout_i, + BUS_DATA_IN(4*32+31 downto 4*32) => cbm_dbg_status_data_i, + BUS_DATAREADY_IN(4) => cbm_dbg_dataready_i, + BUS_WRITE_ACK_IN(4) => cbm_dbg_write_ack_i, + BUS_NO_MORE_DATA_IN(4) => cbm_dbg_no_more_data_i, + BUS_UNKNOWN_ADDR_IN(4) => cbm_dbg_unknown_addr_i, + STAT_DEBUG => open ); diff --git a/cbmnet/trb3_periph_cbmnet_constraints.lpf b/cbmnet/trb3_periph_cbmnet_constraints.lpf index d69cd0a..21cce26 100755 --- a/cbmnet/trb3_periph_cbmnet_constraints.lpf +++ b/cbmnet/trb3_periph_cbmnet_constraints.lpf @@ -1,359 +1,24 @@ -# BLOCK RESETPATHS ; -# BLOCK ASYNCPATHS ; -# BLOCK RD_DURING_WR_PATHS ; - -################################################################# -# Basic Settings -################################################################# - - SYSCONFIG MCCLK_FREQ = 20; - -# FREQUENCY NET "THE_CBM_PHY/CLK_TX_FULL_I" 250 MHz; - -#Change the next two lines to the clk_fast signal of the ADC -# USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0"; -# USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0"; - -# USE PRIMARY NET "CLK_GPLL_LEFT"; -# USE PRIMARY NET "THE_CBM_PHY/RCLK_250_I"; -# USE SECONDARY NET "THE_CBM_PHY/CLK_TX_FULL_I"; - -################################################################# -# Reset Nets -################################################################# -GSR_NET NET "GSR_N"; - - - +SYSCONFIG MCCLK_FREQ=20 ; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ; REGION "MEDIA_UPLINK" "R102C95D" 13 25 DEVSIZE; LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; -LOCATE COMP "THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSB" ; -#LOCATE COMP "THE_CBM_PHY/GEN_EASY_SERDES/THE_EASY_SERDES/PCSD_INST" SITE "PCSB" - -REGION "CBM_PHY" "R102C49D" 13 25; -LOCATE UGROUP "THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY"; - -REGION "CBM_PHY_RX_GEAR" "R102C50D" 13 15 DEVSIZE; -LOCATE UGROUP "THE_CBM_PHY/THE_RX_GEAR/cbmnet_phy_rx_gear" REGION "CBM_PHY_RX_GEAR" ; - -REGION "CBM_PHY_TX_GEAR" "R102C50D" 13 15 DEVSIZE; -LOCATE UGROUP "THE_CBM_PHY/THE_TX_GEAR/cbmnet_phy_tx_gear" REGION "CBM_PHY_TX_GEAR" ; ################################################################# # Relax some of the timing constraints ################################################################# -DEFINE BUS "rx_data" NET "THE_CBM_PHY/rx_data_from_serdes_i[0]" NET "THE_CBM_PHY/rx_data_from_serdes_i[1]" NET "THE_CBM_PHY/rx_data_from_serdes_i[2]" NET "THE_CBM_PHY/rx_data_from_serdes_i[3]" NET "THE_CBM_PHY/rx_data_from_serdes_i[4]" NET "THE_CBM_PHY/rx_data_from_serdes_i[5]" NET "THE_CBM_PHY/rx_data_from_serdes_i[6]" NET "THE_CBM_PHY/rx_data_from_serdes_i[7]" NET "THE_CBM_PHY/rx_data_from_serdes_i[8]"; -DEFINE BUS "tx_data" NET "THE_CBM_PHY/tx_data_to_serdes_i[0]" NET "THE_CBM_PHY/tx_data_to_serdes_i[1]" NET "THE_CBM_PHY/tx_data_to_serdes_i[2]" NET "THE_CBM_PHY/tx_data_to_serdes_i[3]" NET "THE_CBM_PHY/tx_data_to_serdes_i[4]" NET "THE_CBM_PHY/tx_data_to_serdes_i[5]" NET "THE_CBM_PHY/tx_data_to_serdes_i[6]" NET "THE_CBM_PHY/tx_data_to_serdes_i[7]" NET "THE_CBM_PHY/tx_data_to_serdes_i[8]"; - -PRIORITIZE BUS "rx_data" 51; -PRIORITIZE BUS "tx_data" 50; - FREQUENCY PORT "CLK_GPLL_LEFT" 125.0 MHz; +FREQUENCY PORT "TRIGGER_LEFT" 100.0 MHz; FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; -FREQUENCY NET "THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUT" 250.0 MHz; -FREQUENCY NET "THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; -FREQUENCY NET "THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 125.0 MHz; +FREQUENCY NET "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUT" 250.0 MHz; +FREQUENCY NET "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/un1_THE_MEDIA_UPLINK_c" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; +FREQUENCY NET "THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 250.0 MHz; - -# Output Constraints - -# Input Constraints - -# Point-to-point Delay Constraints - - -BLOCK PATH TO CELL "phy_debug_i_buf[0]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[1]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[2]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[3]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[4]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[5]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[6]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[7]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[8]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[9]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[10]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[11]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[12]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[13]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[14]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[15]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[16]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[17]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[20]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[21]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[22]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[24]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[25]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[26]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[27]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[28]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[29]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[30]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[31]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[32]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[33]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[34]" ; 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"phy_debug_i_buf[63]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[64]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[65]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[68]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[69]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[70]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[96]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[97]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[98]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[99]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[100]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[101]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[102]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[103]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[104]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[105]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[106]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[107]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[108]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[109]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[110]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[111]" ; -BLOCK PATH TO CELL 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"phy_debug_i_buf[134]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[135]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[136]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[137]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[138]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[139]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[148]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[149]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[150]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[151]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[152]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[153]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[154]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[155]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[156]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[157]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[158]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[159]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[160]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[161]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[162]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[163]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[164]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[165]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[166]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[167]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[168]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[169]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[170]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[171]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[172]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[173]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[174]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[175]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[176]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[177]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[178]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[179]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[180]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[181]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[182]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[183]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[184]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[185]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[186]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[187]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[188]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[189]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[190]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[191]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[192]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[193]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[194]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[195]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[196]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[197]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[198]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[199]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[200]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[201]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[202]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[203]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[204]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[205]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[206]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[207]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[208]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[209]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[210]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[211]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[244]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[245]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[246]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[247]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[248]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[249]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[250]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[251]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[252]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[253]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[254]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[255]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[256]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[257]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[258]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[259]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[260]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[261]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[262]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[263]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[264]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[265]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[266]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[267]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[268]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[269]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[270]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[271]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[272]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[273]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[274]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[275]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[276]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[277]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[278]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[279]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[280]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[281]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[282]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[283]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[284]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[285]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[286]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[287]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[288]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[289]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[290]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[291]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[292]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[293]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[294]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[295]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[296]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[297]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[298]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[299]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[300]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[301]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[302]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[303]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[304]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[305]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[306]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[307]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[308]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[309]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[310]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[311]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[312]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[313]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[314]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[315]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[316]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[317]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[318]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[319]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[320]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[321]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[322]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[323]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[324]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[325]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[326]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[327]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[328]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[329]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[330]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[331]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[332]" ; -BLOCK PATH TO CELL "phy_debug_i_buf[333]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[0]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[1]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[2]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[3]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[4]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[5]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[6]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[7]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[8]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[9]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[10]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[11]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[12]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[13]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[14]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[15]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[16]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[17]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[18]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[19]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[20]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[21]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[22]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[23]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[24]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[25]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[26]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[27]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[28]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[29]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[30]" ; -BLOCK PATH TO CELL "PROC_REGIO_DEBUG.debug_data_out[31]" ; +LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R105C110D"; +LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R80C85D"; +LOCATE COMP "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSB" ; diff --git a/cbmnet/trb3_periph_cbmnet_syn.fdc b/cbmnet/trb3_periph_cbmnet_syn.fdc new file mode 100644 index 0000000..ed9729a --- /dev/null +++ b/cbmnet/trb3_periph_cbmnet_syn.fdc @@ -0,0 +1,60 @@ +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /d/jspc29/mpenschuck/trb3/cbmnet/project/trb3_periph_cbmnet_syn.fdc +# Written on Fri Aug 8 13:40:28 2014 +# by Synplify Pro, I-2013.09-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +###==== END Collections + +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock {n:THE_MAIN_PLL.CLKOP} -period {10} +create_clock {n:THE_MAIN_PLL.CLKOK} -period {5} +create_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -period {10} +create_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -period {10} +create_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -period {10} +create_clock {p:CLK_GPLL_LEFT} -period {8} +create_clock {p:TRIGGER_LEFT} -period {10} + +create_clock -name {rclk125} {n:THE_CBM_BRIDGE.THE_CBM_PHY.THE_RX_GEAR.CLK_125_OUT} -period {8} +create_clock {n:THE_CBM_BRIDGE.THE_CBM_PHY.THE_SERDES.rx_full_clk_ch0} -period {4} +create_clock {n:THE_CBM_BRIDGE.THE_CBM_PHY.THE_SERDES.tx_full_clk_ch0} -period {4} + + +###==== END Clocks + +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" + +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs + +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" + +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes + +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" + +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + + + + + + + + + + + + diff --git a/cts/compile_constraints.pl b/cts/compile_constraints.pl index 606dd14..31eaf23 100755 --- a/cts/compile_constraints.pl +++ b/cts/compile_constraints.pl @@ -66,7 +66,7 @@ open FILE, "<$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!"; my $lpf = join('', ); close FILE; -$lpf =~ s#THE_CBM_BRIDGE/#GEN_CBM.THE_CBM_BRIDGE/#g; +$lpf =~ s#THE_CBM_BRIDGE/#GEN_CBMNET.THE_CBM_BRIDGE/#g; $lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g; -- 2.43.0