From 16c47a9a9ef65ef1d90ea14100529c5aa84bb98b Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Fri, 25 Aug 2017 16:58:46 +0200 Subject: [PATCH] small change for new flash ctrl, IF --- thresholds/thresholds.vhd | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 86a45ec..cd82592 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -33,7 +33,7 @@ architecture arch of thresholds is signal bus_read : std_logic := '0'; signal bus_write : std_logic := '0'; signal bus_ready : std_logic; - --signal spi_busy : std_logic; + signal bus_busy : std_logic; signal spi_data_out : std_logic_vector(15 downto 0); signal spi_data_in : std_logic_vector(15 downto 0); @@ -41,7 +41,7 @@ architecture arch of thresholds is signal spi_write_out : std_logic; signal spi_read_out : std_logic; signal spi_ready_in : std_logic; - + signal spi_busy_out : std_logic; signal sed_error : std_logic; signal sed_debug : std_logic_vector(31 downto 0); @@ -121,13 +121,15 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl SPI_WRITE_IN => spi_write_out, SPI_READ_IN => spi_read_out, SPI_READY_OUT => spi_ready_in, + SPI_BUSY_IN => spi_busy_out, LOC_DATA_OUT => spi_rx_data, LOC_DATA_IN => spi_tx_data, LOC_ADDR_OUT => spi_addr, LOC_WRITE_OUT => bus_write, LOC_READ_OUT => bus_read, - LOC_READY_IN => bus_ready + LOC_READY_IN => bus_ready, + LOC_BUSY_OUT => bus_busy ); -- 2.43.0