From 16db24f64ca7808113ced185727263c0387ff1d9 Mon Sep 17 00:00:00 2001 From: Hadaq in Frankfurt Date: Fri, 15 Mar 2013 13:28:39 +0100 Subject: [PATCH] latest changes, JM --- vhdl/code/jtag_cmd_m26c.vhd | 1 + vhdl/code/jtag_mvd.vhd | 1099 ++++++++++++----------------------- 2 files changed, 364 insertions(+), 736 deletions(-) diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd index 7c70b19..5351213 100644 --- a/vhdl/code/jtag_cmd_m26c.vhd +++ b/vhdl/code/jtag_cmd_m26c.vhd @@ -2764,6 +2764,7 @@ begin request_reset_next <= '1'; m26cs_state_next <= M26CSS_REQUEST_RESET_WAIT; when M26CSS_REQUEST_RESET_WAIT => + request_reset_next <= '0'; reset_wait_next <= RESET_WAIT_DURATION; m26cs_state_next <= M26CSS_REQUESTED_RESET_WAIT; when M26CSS_REQUESTED_RESET_WAIT => diff --git a/vhdl/code/jtag_mvd.vhd b/vhdl/code/jtag_mvd.vhd index 2539c37..ef0e510 100644 --- a/vhdl/code/jtag_mvd.vhd +++ b/vhdl/code/jtag_mvd.vhd @@ -4,6 +4,7 @@ use ieee.numeric_std.all; library work; use work.jtag_constants.all; +use work.trb3_components.all; use work.trb_net_components.all; use work.trb_net_std.all; @@ -17,6 +18,7 @@ entity jtag_mvd is ); port( CLK_IN : in std_logic; + CLK_MAPS_IN : in std_logic; --200 MHz for PLL! RESET : in std_logic; MAPS_CLK_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); @@ -49,12 +51,14 @@ end entity; architecture jtag_mvd_arch of jtag_mvd is - + signal clk_sys : std_logic; signal clk_maps : std_logic; + signal reset_i : std_logic; + signal reset_i_mclk : std_logic; -- COM_SETTINGS signals: for settings in this entity - signal com_settings_addr_in : std_logic_vector(15 downto 0); + signal com_settings_addr_in : std_logic_vector(7 downto 0); signal com_settings_data_in : std_logic_vector(31 downto 0); signal com_settings_read_enable_in : std_logic; signal com_settings_write_enable_in : std_logic; @@ -92,11 +96,15 @@ architecture jtag_mvd_arch of jtag_mvd is signal jtagcmd_last_read_errors_out : std_logic_vector(num_chaINS-1 downto 0); signal run_jtag : std_logic_vector(NUM_CHAINS-1 downto 0); + signal run_jtag_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); signal trbnet_trigger_jtag_write_once : std_logic_vector(NUM_CHAINS-1 downto 0); signal idle_out : std_logic_vector(NUM_CHAINS-1 downto 0); signal request_reset : std_logic_vector(NUM_CHAINS-1 downto 0); + signal request_reset_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); signal prog_jtag_finished : std_logic_vector(NUM_CHAINS-1 downto 0); - + signal idle_out_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal prog_jtag_finished_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal clk_maps_tmp_p : std_logic_vector(NUM_CHAINS-1 downto 0); signal clk_maps_tmp_n : std_logic_vector(NUM_CHAINS-1 downto 0); @@ -110,9 +118,61 @@ architecture jtag_mvd_arch of jtag_mvd is type sig_inv_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(13 downto 0); signal signals_invert : sig_inv_t; + + attribute ODDRAPPS : string; + attribute ODDRAPPS of THE_CLK_OUT: label is "SCLK_ALIGNED"; + + signal trbnet_trigger_allchains_init_seq : std_logic; + signal trbnet_trigger_allchains_reset_pulse : std_logic; + signal trbnet_trigger_allchains_start_pulse : std_logic; + signal trbnet_trigger_init_seq : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trbnet_trigger_reset_pulse : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trbnet_trigger_start_pulse : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trbnet_trigger_jtag_run_noreset : std_logic_vector(NUM_CHAINS-1 downto 0); + signal resetafterfirstwrite : std_logic_vector(NUM_CHAINS-1 downto 0); + signal resetbeforeinit : std_logic_vector(NUM_CHAINS-1 downto 0); + + signal trbnet_trigger_allchains_init_seq_mclk : std_logic; + signal trbnet_trigger_allchains_reset_pulse_mclk : std_logic; + signal trbnet_trigger_allchains_start_pulse_mclk : std_logic; + signal trbnet_trigger_init_seq_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trbnet_trigger_reset_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trbnet_trigger_start_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trbnet_trigger_jtag_run_noreset_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + + signal trigger_reset_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trigger2_reset_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trigger_start_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trigger_allchains_start_pulse_mclk : std_logic; + signal trigger_jtag_run_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + signal trigger_jtag_run2_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); + + type maps_reset_cnt_t is array (NUM_CHAINS-1 downto 0) of unsigned(6 downto 0); + signal maps_reset_count : maps_reset_cnt_t; + signal maps_start_count : maps_reset_cnt_t; + + type init_seq_t is (isIDLE, isRUN_JTAG_WAIT1, isRUN_JTAG_WAIT2, isRUN_JTAG_WAIT3, + isRUN_JTAG_WAIT4, isRUN_JTAG_WAIT5, isRUN_JTAG_WAIT6, isRUN_JTAG_WAIT7, isRUN_JTAG, isWAITBEFORESTART ); + type init_seq_mult_t is array (NUM_CHAINS-1 downto 0) of init_seq_t; + signal init_seq_mclk : init_seq_mult_t; + signal init_seq_allchains_mclk : init_seq_t; + + type cnt_t is array (0 to NUM_CHAINS-1) of unsigned(27 downto 0); + signal waitbeforestart_counter : cnt_t; + signal waitbeforestart : unsigned(27 downto 0); + signal waitbeforestart_counter_allchains : unsigned(27 downto 0); begin +--------------------------------------------------------------------------- +-- Clock & Reset +--------------------------------------------------------------------------- + clk_sys <= CLK_IN; +-- clk_maps <= CLK_MAPS_IN; + reset_i <= RESET when rising_edge(clk_sys); + reset_i_mclk <= reset_i when rising_edge(clk_maps); + + --------------------------------------------------------------------------- -- The JTAG Bus Handler 0: control registers, 1-N: JTAG controllers --------------------------------------------------------------------------- @@ -124,8 +184,8 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler PORT_ADDR_MASK => (0 => 8, others => 9) ) port map( - CLK => CLK_IN, - RESET => RESET, + CLK => clk_sys, + RESET => reset_i, DAT_ADDR_IN(12 downto 0) => BUS_ADDR_IN, DAT_ADDR_IN(15 downto 13)=> "000", @@ -140,16 +200,17 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_OUT, --Common Registers - BUS_READ_ENABLE_OUT(0) => com_settings_read_enable_in, - BUS_WRITE_ENABLE_OUT(0) => com_settings_write_enable_in, - BUS_DATA_OUT(0*32+31 downto 0*32) => com_settings_data_in, - BUS_ADDR_OUT(0*16+15 downto 0*16) => com_settings_addr_in, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => com_settings_data_out, - BUS_DATAREADY_IN(0) => com_settings_dataready_out, - BUS_WRITE_ACK_IN(0) => com_settings_write_ack_out, - BUS_NO_MORE_DATA_IN(0) => com_settings_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(0) => com_settings_unknown_addr_out, + BUS_READ_ENABLE_OUT(0) => com_settings_read_enable_in, + BUS_WRITE_ENABLE_OUT(0) => com_settings_write_enable_in, + BUS_DATA_OUT(0*32+31 downto 0*32) => com_settings_data_in, + BUS_ADDR_OUT(0*16+7 downto 0*16) => com_settings_addr_in, + BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => com_settings_data_out, + BUS_DATAREADY_IN(0) => com_settings_dataready_out, + BUS_WRITE_ACK_IN(0) => com_settings_write_ack_out, + BUS_NO_MORE_DATA_IN(0) => com_settings_no_more_data_out, + BUS_UNKNOWN_ADDR_IN(0) => com_settings_unknown_addr_out, --JTAG chains BUS_READ_ENABLE_OUT(NUM_CHAINS downto 1) => jtag_cmd_m26c_read_enable_in, @@ -173,7 +234,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler THE_MAPS_PLL : entity work.pll_in100_out80 port map( - CLK => CLK_IN, + CLK => CLK_MAPS_IN, CLKOP => clk_maps, LOCK => open ); @@ -202,20 +263,20 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler MAPS_START_OUT(i) <= (maps_start(i) xor signals_invert(i)(8)) when signals_invert(i)(9) = '1' else signals_invert(i)(8); JTAG_TCK_OUT(i) <= (jtag_tck(i) xor signals_invert(i)(6)) when signals_invert(i)(7) = '1' else signals_invert(i)(6); JTAG_TMS_OUT(i) <= (jtag_tms(i) xor signals_invert(i)(4)) when signals_invert(i)(5) = '1' else signals_invert(i)(4); - JTAG_TDI_OUT(i) <= (jtag_tms(i) xor signals_invert(i)(2)) when signals_invert(i)(3) = '1' else signals_invert(i)(2); + JTAG_TDI_OUT(i) <= (jtag_tdi(i) xor signals_invert(i)(2)) when signals_invert(i)(3) = '1' else signals_invert(i)(2); jtag_tdo(i) <= (JTAG_TDO_IN(i) xor signals_invert(i)(0)) when signals_invert(i)(1) = '1' else signals_invert(i)(0); clk_maps_tmp_p(i) <= signals_invert(i)(12) when signals_invert(i)(13) = '1' else signals_invert(i)(12); clk_maps_tmp_n(i) <= not signals_invert(i)(12) when signals_invert(i)(13) = '1' else signals_invert(i)(12); - THE_CLK_OUT : ODDRXD1 port map( - SCLK => clk_maps, - DA => clk_maps_tmp_p(i), - DB => clk_maps_tmp_n(i), - Q => MAPS_CLK_OUT(i) + sclk => clk_maps, + da => clk_maps_tmp_p(i), + db => clk_maps_tmp_n(i), + q => MAPS_CLK_OUT(i) ); + end generate; @@ -225,8 +286,8 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler gen_chains : for i in 0 to NUM_CHAINS-1 generate THE_JTAG_CMD_M26C : entity work.jtag_cmd_m26c port map( - CLK_IN => CLK_IN, - RESET_IN => RESET, + CLK_IN => clk_sys, + RESET_IN => reset_i, JTAG_TMS_OUT => jtag_tms(i), JTAG_TCK_OUT => jtag_tck(i), @@ -270,728 +331,294 @@ end generate; --------------------------------------------------------------------------- -- Clock domain transfers --------------------------------------------------------------------------- --- Reset Requests from JTAG_CMD_M26C entities are two clock cycles long pulses that are synchronized to 80 MHz clock --- request_reset_MAPS_CLK <= request_reset when rising_edge(MAPS_CLK); - + gen_sync_per_chain : for i in 0 to NUM_CHAINS-1 generate + ps00 : pulse_sync port map(clk_sys, reset_i, request_reset(i), + clk_maps, reset_i_mclk, request_reset_mclk(i)); + ps01 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_init_seq(i), + clk_maps, reset_i_mclk, trbnet_trigger_init_seq_mclk(i)); + ps02 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_reset_pulse(i), + clk_maps, reset_i_mclk, trbnet_trigger_reset_pulse_mclk(i)); + ps03 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_start_pulse(i), + clk_maps, reset_i_mclk, trbnet_trigger_start_pulse_mclk(i)); + ps04 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_jtag_run_noreset(i), + clk_maps, reset_i_mclk, trbnet_trigger_jtag_run_noreset_mclk(i)); + end generate; + + ps11 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_allchains_init_seq, + clk_maps, reset_i_mclk, trbnet_trigger_allchains_init_seq_mclk); + ps12 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_allchains_reset_pulse, + clk_maps, reset_i_mclk, trbnet_trigger_allchains_reset_pulse_mclk); + ps13 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_allchains_start_pulse, + clk_maps, reset_i_mclk, trbnet_trigger_allchains_start_pulse_mclk); + + + idle_out_mclk <= idle_out when rising_edge(clk_maps); + prog_jtag_finished_mclk <= prog_jtag_finished when rising_edge(clk_maps); + + +--------------------------------------------------------------------------- +-- Generate control signals for MAPS +---------------------------------------------------- ----------------------- + gen_maps_signals : for i in 0 to NUM_CHAINS-1 generate + MAPS_RESET_PULSE : process + begin + wait until rising_edge(clk_maps); + if(maps_reset_count(i) = 0 or reset_i_mclk = '1') then + maps_reset(i) <= '0'; + else + maps_reset_count(i) <= maps_reset_count(i) - 1; + end if; + + if ( trbnet_trigger_reset_pulse_mclk(i) = '1' + or trigger_reset_pulse_mclk(i) = '1' + or trigger2_reset_pulse_mclk(i) = '1' + or trbnet_trigger_allchains_reset_pulse_mclk = '1') then + maps_reset_count(i) <= "1100100"; -- 101 clock cycles reset (on for 100,...,4,3,2,1,0) + maps_reset(i) <= '1'; + end if; + end process; + + MAPS_START_PULSE : process + begin + wait until rising_edge(clk_maps); + if(maps_start_count(i) = 0 or reset_i_mclk = '1') then + maps_start(i) <= '0'; + else + maps_start_count(i) <= maps_start_count(i) - 1; + end if; + + if ( trbnet_trigger_start_pulse_mclk(i) = '1' + or trigger_start_pulse_mclk(i) = '1' + or trbnet_trigger_allchains_start_pulse_mclk = '1' + or trigger_allchains_start_pulse_mclk = '1') then + maps_start_count(i) <= "1000000"; -- 65 clock cycles start (on for 64,...,4,3,2,1,0) + maps_start(i) <= '1'; + end if; + + end process; + + end generate; + + --JTAG_RUN_NORESET / RUN_JTAG_SYNC + run_jtag_mclk <= trbnet_trigger_jtag_run_noreset_mclk or trigger_jtag_run_mclk or trigger_jtag_run2_mclk when rising_edge(clk_maps); + run_jtag <= run_jtag_mclk when rising_edge(clk_sys); + + + gen_init_sequence : for i in 0 to NUM_CHAINS-1 generate + TRIGGER_INITIALIZATION_SEQUENCE_PULSE : process(clk_maps) + begin + if(rising_edge(clk_maps)) then + trigger_start_pulse_mclk(i) <= '0'; + trigger_reset_pulse_mclk(i) <= '0'; + trigger_jtag_run_mclk(i) <= '0'; + case init_seq_mclk(i) is + when isIDLE => + when isRUN_JTAG_WAIT1 => + init_seq_mclk(i) <= isRUN_JTAG_WAIT2; + when isRUN_JTAG_WAIT2 => + init_seq_mclk(i) <= isRUN_JTAG_WAIT3; + when isRUN_JTAG_WAIT3 => + init_seq_mclk(i) <= isRUN_JTAG_WAIT4; + when isRUN_JTAG_WAIT4 => + init_seq_mclk(i) <= isRUN_JTAG_WAIT5; + when isRUN_JTAG_WAIT5 => + init_seq_mclk(i) <= isRUN_JTAG_WAIT6; + when isRUN_JTAG_WAIT6 => + init_seq_mclk(i) <= isRUN_JTAG_WAIT7; + when isRUN_JTAG_WAIT7 => + init_seq_mclk(i) <= isRUN_JTAG; + when isRUN_JTAG => + if(resetafterfirstwrite(i) = '1') then + if(request_reset(i) = '1') then + trigger_reset_pulse_mclk(i) <= '1'; + end if; + end if; + -- wait for completion of potential copy ram request and then finishing of run + if(idle_out_mclk(i) = '1') then + init_seq_mclk(i) <= isWAITBEFORESTART; + waitbeforestart_counter(i) <= waitbeforestart; + end if; + when isWAITBEFORESTART => + waitbeforestart_counter(i) <= waitbeforestart_counter(i) -1; + if(waitbeforestart_counter(i) = 0) then + trigger_start_pulse_mclk(i) <= '1'; + init_seq_mclk(i) <= isIDLE; + end if; + end case; + + if(trbnet_trigger_init_seq_mclk(i) = '1') then + if(resetbeforeinit(i) = '1') then + trigger_reset_pulse_mclk(i) <= '1'; + end if; + trigger_jtag_run_mclk(i) <= '1'; + init_seq_mclk(i) <= isRUN_JTAG_WAIT1; + end if; + if(reset_i_mclk = '1') then + init_seq_mclk(i) <= isIDLE; + end if; + end if; + end process; + end generate; + + TRIGGER_ALLCHAINS_INITIALIZATION_SEQUENCE_PULSE : process(clk_maps) + begin + if(rising_edge(clk_maps)) then + trigger2_reset_pulse_mclk <= (others => '0'); + trigger_jtag_run2_mclk <= (others => '0'); + trigger_allchains_start_pulse_mclk <= '0'; + case init_seq_allchains_mclk is + when isIDLE => + when isRUN_JTAG_WAIT1 => + init_seq_allchains_mclk <= isRUN_JTAG_WAIT2; + when isRUN_JTAG_WAIT2 => + init_seq_allchains_mclk <= isRUN_JTAG_WAIT3; + when isRUN_JTAG_WAIT3 => + init_seq_allchains_mclk <= isRUN_JTAG_WAIT4; + when isRUN_JTAG_WAIT4 => + init_seq_allchains_mclk <= isRUN_JTAG_WAIT5; + when isRUN_JTAG_WAIT5 => + init_seq_allchains_mclk <= isRUN_JTAG_WAIT6; + when isRUN_JTAG_WAIT6 => + init_seq_allchains_mclk <= isRUN_JTAG_WAIT7; + when isRUN_JTAG_WAIT7 => + init_seq_allchains_mclk <= isRUN_JTAG; + when isRUN_JTAG => + trigger2_reset_pulse_mclk <= resetafterfirstwrite and request_reset_mclk; + + if(and_all(idle_out_mclk) = '1') then + init_seq_allchains_mclk <= isWAITBEFORESTART; + waitbeforestart_counter_allchains <= waitbeforestart; + end if; + when isWAITBEFORESTART => + waitbeforestart_counter_allchains <= waitbeforestart_counter_allchains -1; + if(waitbeforestart_counter_allchains = 0) then + trigger_allchains_start_pulse_mclk <= '1'; + init_seq_allchains_mclk <= isIDLE; + end if; + end case; + if(trbnet_trigger_allchains_init_seq_mclk = '1') then + trigger2_reset_pulse_mclk <= resetbeforeinit; + trigger_jtag_run2_mclk <= (others => '1'); + init_seq_allchains_mclk <= isRUN_JTAG_WAIT1; + end if; + + if(reset_i_mclk = '1') then + init_seq_allchains_mclk <= isIDLE; + end if; + end if; + end process; + + +-- 3: trbnet_trigger_allchains_init_seq nodata +-- 6,8,9: signals_invert 14bit / N regs -> move to 0x20... 0x2F +-- 7: waitbeforestart 28bit +-- a: trbnet_trigger_allchains_reset_pulse nodata +-- b: trbnet_trigger_allchains_start_pulse nodata +-- c: trbnet_trigger_init_seq N bit +-- d: trbnet_trigger_reset_pulse N bit +-- e: trbnet_trigger_start_pulse N bit +-- f: trbnet_trigger_jtag_run_noreset N bit +-- 10: resetbeforeinit N bit +-- 11: resetafterfirstwrite N bit +-- 14: trbnet_trigger_jtag_write_once N bit + + +--------------------------------------------------------------------------- +-- Control Registers +--------------------------------------------------------------------------- + com_settings_all : process + begin + wait until rising_edge(clk_sys); + com_settings_write_ack_out <= '0'; + com_settings_dataready_out <= '0'; + com_settings_unknown_addr_out <= '0'; + com_settings_no_more_data_out <= '0'; + -- MUST NOW BE 1 CYCLE ONLY. Before it was: + -- reset triggers after 2 clock cycles at 100 MHz, to be able to sample at 80 MHz + trbnet_trigger_allchains_init_seq <= '0'; + trbnet_trigger_allchains_reset_pulse <= '0'; + trbnet_trigger_allchains_start_pulse <= '0'; + trbnet_trigger_init_seq <= (others => '0'); + trbnet_trigger_reset_pulse <= (others => '0'); + trbnet_trigger_start_pulse <= (others => '0'); + trbnet_trigger_jtag_run_noreset <= (others => '0'); + trbnet_trigger_jtag_write_once <= (others => '0'); + + if(com_settings_write_enable_in = '1') then + com_settings_write_ack_out <= '1'; + if (com_settings_addr_in = x"03") then + trbnet_trigger_allchains_init_seq <= '1'; + elsif(com_settings_addr_in = x"07") then + waitbeforestart <= unsigned(com_settings_data_in(27 downto 0)); + elsif(com_settings_addr_in = x"0a") then + trbnet_trigger_allchains_reset_pulse <= com_settings_data_in(0); + elsif(com_settings_addr_in = x"0b") then + trbnet_trigger_allchains_start_pulse <= com_settings_data_in(0); + elsif(com_settings_addr_in = x"0c") then + trbnet_trigger_init_seq <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in = x"0d") then + trbnet_trigger_reset_pulse <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in = x"0e") then + trbnet_trigger_start_pulse <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in = x"0f") then + trbnet_trigger_jtag_run_noreset <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in = x"10") then + resetbeforeinit <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in = x"11") then + resetafterfirstwrite <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in = x"14") then + trbnet_trigger_jtag_write_once <= com_settings_data_in(NUM_CHAINS-1 downto 0); + elsif(com_settings_addr_in(7 downto 4) = x"2" and com_settings_addr_in(3 downto 0) < std_logic_vector(to_unsigned(NUM_CHAINS,4))) then + signals_invert(to_integer(unsigned(com_settings_addr_in(3 downto 0)))) <= com_settings_data_in(13 downto 0); + else + com_settings_write_ack_out <= '0'; + com_settings_unknown_addr_out <= '1'; + end if; + + + elsif(com_settings_read_enable_in = '1') then + com_settings_dataready_out <= '1'; + com_settings_data_out <= (others => '0'); + if (com_settings_addr_in = x"07") then + com_settings_data_out(27 downto 0) <= std_logic_vector(waitbeforestart); + elsif(com_settings_addr_in = x"10") then + com_settings_data_out(NUM_CHAINS-1 downto 0) <= resetbeforeinit; + elsif(com_settings_addr_in = x"11") then + com_settings_data_out(NUM_CHAINS-1 downto 0) <= resetafterfirstwrite; + elsif(com_settings_addr_in = x"12") then + com_settings_data_out(6 downto 0) <= std_logic_vector(maps_reset_count(0)(6 downto 0)); + elsif(com_settings_addr_in = x"13") then + com_settings_data_out(6 downto 0) <= std_logic_vector(maps_start_count(0)(6 downto 0)); + elsif(com_settings_addr_in(7 downto 4) = x"2" and com_settings_addr_in(3 downto 0) < std_logic_vector(to_unsigned(NUM_CHAINS,4))) then + com_settings_data_out(13 downto 0) <= signals_invert(to_integer(unsigned(com_settings_addr_in(3 downto 0)))); + else + com_settings_dataready_out <= '0'; + com_settings_unknown_addr_out <= '1'; + end if; + end if; + + if(reset_i = '1') then + resetbeforeinit <= (others => '0'); + resetafterfirstwrite <= (others => '0'); + waitbeforestart <= (others => '0'); + + com_settings_dataready_out <= '0'; + com_settings_write_ack_out <= '0'; + com_settings_no_more_data_out <= '0'; + com_settings_unknown_addr_out <= '0'; + end if; + end process; + --------------------------------------------------------------------------- -- Here be dragons (the stuff I didn't touch yet) --------------------------------------------------------------------------- --- --- SYNC_TRBNET_TRIGGERS: process (MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- -- allchains_initialization_sequence --- trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK <= trbnet_trigger_allchains_initialization_sequence; --- trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK <= trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK; --- -- reset pulse --- trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK <= trbnet_trigger_allchains_reset_pulse; --- trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK <= trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK; --- --- -- start pulse --- trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK <= trbnet_trigger_allchains_start_pulse; --- trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK <= trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK; --- --- for i in 2 downto 0 loop --- -- initialization_sequence s --- trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i) <= --- trbnet_trigger_initialization_sequence(i); --- trbnet_trigger_initialization_sequence_sync2_MAPS_CLK(i) <= --- trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i); --- -- reset pulse --- trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i) <= trbnet_trigger_reset_pulse(i); --- trbnet_trigger_reset_pulse_sync2_MAPS_CLK(i) <= trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i); --- -- start pulse --- trbnet_trigger_start_pulse_sync1_MAPS_CLK(i) <= trbnet_trigger_start_pulse(i); --- trbnet_trigger_start_pulse_sync2_MAPS_CLK(i) <= trbnet_trigger_start_pulse_sync1_MAPS_CLK(i); --- -- jtag_run_noreset --- trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset(i); --- trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i); --- end loop; --- --- --- if(RESET='1') then --- trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK <= '0'; --- trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK <= '0'; --- trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK <= '0'; --- trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK <= '0'; --- trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK <= '0'; --- trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK <= '0'; --- for i in 2 downto 0 loop --- trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i) <= '0'; --- trbnet_trigger_initialization_sequence_sync2_MAPS_CLK(i) <= '0'; --- -- reset pulse --- trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i) <= '0'; --- trbnet_trigger_reset_pulse_sync2_MAPS_CLK(i) <= '0'; --- -- start pulse --- trbnet_trigger_start_pulse_sync1_MAPS_CLK(i) <= '0'; --- trbnet_trigger_start_pulse_sync2_MAPS_CLK(i) <= '0'; --- -- jtag_run_noreset --- trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i) <= '0'; --- trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK(i) <= '0'; --- end loop; --- end if; --- end if; --- end process; --- --- TRBNET_TRIGGERS_MAPS_CLK: process (trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK, trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK, --- trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK, --- trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK, --- trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK, --- trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK, --- trbnet_trigger_initialization_sequence_sync1_MAPS_CLK, --- trbnet_trigger_initialization_sequence_sync2_MAPS_CLK, --- trbnet_trigger_reset_pulse_sync1_MAPS_CLK, --- trbnet_trigger_reset_pulse_sync2_MAPS_CLK, --- trbnet_trigger_start_pulse_sync1_MAPS_CLK, --- trbnet_trigger_start_pulse_sync2_MAPS_CLK, --- trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK, --- trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK) --- begin --- -- allchains_initialization_sequence --- trbnet_trigger_allchains_initialization_sequence_MAPS_CLK <= trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK and not trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK; --- -- allchains reset pulse --- trbnet_trigger_allchains_reset_pulse_MAPS_CLK <= trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK and not trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK; --- -- start pulse --- trbnet_trigger_allchains_start_pulse_MAPS_CLK <= trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK and not trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK; --- -- initialization_sequence s --- for i in 2 downto 0 loop --- trbnet_trigger_initialization_sequence_MAPS_CLK(i) <= --- trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i) and not trbnet_trigger_initialization_sequence_sync2_MAPS_CLK(i); --- -- reset pulse --- trbnet_trigger_reset_pulse_MAPS_CLK(i) <= trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i) and not trbnet_trigger_reset_pulse_sync2_MAPS_CLK(i); --- -- start pulse --- trbnet_trigger_start_pulse_MAPS_CLK(i) <= trbnet_trigger_start_pulse_sync1_MAPS_CLK(i) and not trbnet_trigger_start_pulse_sync2_MAPS_CLK(i); --- trbnet_trigger_jtag_run_noreset_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i) and not trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK(i); --- end loop; --- --- end process; --- --- MAPS_RESET_PULSE : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- for i in 2 downto 0 loop --- if(to_integer(MAPS_reset_count(i)) = 0) then --- MAPS_reset(i) <= '0'; --- else --- MAPS_reset_count(i) <= MAPS_reset_count(i) - 1; --- end if; --- --- if(trbnet_trigger_reset_pulse_MAPS_CLK(i) = '1' or trigger_reset_pulse_MAPS_CLK(i) = '1' or trigger2_reset_pulse_MAPS_CLK(i) = '1' --- or trbnet_trigger_allchains_reset_pulse_MAPS_CLK = '1') then --or trigger_allchains_reset_pulse_MAPS_CLK = '1') then --- MAPS_reset_count(i) <= "1100100"; -- 101 clock cycles reset (on for 100,...,4,3,2,1,0) --- MAPS_reset(i) <= '1'; --- end if; --- --- --- if(RESET='1') then --- MAPS_reset(i) <= '0'; --- MAPS_reset_count(i) <= (others => '0'); --- end if; --- end loop; --- end if; --- end process; --- --- MAPS_START_PULSE : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- for i in 2 downto 0 loop --- if(to_integer(MAPS_start_count(i)) = 0) then --- MAPS_start(i) <= '0'; --- else --- MAPS_start_count(i) <= MAPS_start_count(i) - 1; --- end if; --- --- if(trbnet_trigger_start_pulse_MAPS_CLK(i) = '1' or trigger_start_pulse_MAPS_CLK(i) = '1' --- or trbnet_trigger_allchains_start_pulse_MAPS_CLK = '1' or trigger_allchains_start_pulse_MAPS_CLK = '1') then --- MAPS_start_count(i) <= "1000000"; -- 65 clock cycles start (on for 64,...,4,3,2,1,0) --- MAPS_start(i) <= '1'; --- end if; --- --- if(RESET='1') then --- MAPS_start(i) <= '0'; --- MAPS_start_count(i) <= (others => '0'); --- end if; --- end loop; --- end if; --- end process; --- --- --- -- JTAG_RUN_NORESET : process(MAPS_CLK, RESET) --- -- begin --- -- if(rising_edge(MAPS_CLK)) then --- -- for i in 2 downto 0 loop --- -- -- wait for completion of potential copy ram request --- -- if(run_window_counter(i) = run_window_counter_zero) then --- -- run_jtag_MAPS_CLK(i) <= '0'; --- -- else --- -- run_window_counter(i) <= run_window_counter(i) - 1; --- -- end if; --- -- --- -- if(trbnet_trigger_jtag_run_noreset_MAPS_CLK(i) = '1' or trigger_jtag_run_MAPS_CLK(i) = '1' or trigger_jtag_run2_MAPS_CLK(i) = '1') then --- -- run_jtag_MAPS_CLK(i) <= '1'; --- -- run_window_counter(i) <= "111111111111"; --- -- end if; --- -- end loop; --- -- if(RESET='1') then --- -- run_jtag_MAPS_CLK <= (others => '0'); --- -- for i in 2 downto 0 loop --- -- run_window_counter(i) <= (others => '0'); --- -- end loop; --- -- end if; --- -- end if; --- -- end process; --- --replaces process, because jtag_cmd_m26c internally saves request now --- JTAG_RUN_NORESET : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- for i in 2 downto 0 loop --- run_jtag_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset_MAPS_CLK(i) or trigger_jtag_run_MAPS_CLK(i) or trigger_jtag_run2_MAPS_CLK(i); --- end loop; --- end if; --- end process; --- --- --- RUN_JTAG_SYNC : process(CLK, RESET) --- begin --- if(rising_edge(CLK)) then --- run_jtag <= run_jtag_MAPS_CLK; --- if(RESET='1') then --- run_jtag <= (others => '0'); --- end if; --- end if; --- end process; --- --- TRIGGER_INITIALIZATION_SEQUENCE_PULSE0 : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- -- for i in 2 downto 0 loop --- trigger_start_pulse_MAPS_CLK(0) <= '0'; --- trigger_reset_pulse_MAPS_CLK(0) <= '0'; --- trigger_jtag_run_MAPS_CLK(0) <= '0'; --- case init_seq_MAPS_CLK_0 is --- when isIDLE => --- when isRUN_JTAG_WAIT1 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT2; --- when isRUN_JTAG_WAIT2 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT3; --- when isRUN_JTAG_WAIT3 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT4; --- when isRUN_JTAG_WAIT4 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT5; --- when isRUN_JTAG_WAIT5 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT6; --- when isRUN_JTAG_WAIT6 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT7; --- when isRUN_JTAG_WAIT7 => --- init_seq_MAPS_CLK_0 <= isRUN_JTAG; --- when isRUN_JTAG => --- if(resetafterfirstwrite(0) = '1') then --- if(request_reset(0) = '1') then --- trigger_reset_pulse_MAPS_CLK(0) <= '1'; --- end if; --- end if; --- -- wait for completion of potential copy ram request and then finishing of run --- if(idle_out_MAPS_CLK(0) = '1') then --- init_seq_MAPS_CLK_0 <= isWAITBEFORESTART; --- waitbeforestart_counter(0) <= waitbeforestart; --- end if; --- when isWAITBEFORESTART => --- waitbeforestart_counter(0) <= waitbeforestart_counter(0) -1; --- if(waitbeforestart_counter(0) = waitbeforestart_counter_zero) then --- trigger_start_pulse_MAPS_CLK(0) <= '1'; --- init_seq_MAPS_CLK_0 <= isIDLE; --- end if; --- end case; --- if(trbnet_trigger_initialization_sequence_MAPS_CLK(0) = '1') then --- if(resetbeforeinit(0) = '1') then --- trigger_reset_pulse_MAPS_CLK(0) <= '1'; --- end if; --- trigger_jtag_run_MAPS_CLK(0) <= '1'; --- init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT1; --- end if; --- if(RESET = '1') then --- init_seq_MAPS_CLK_0 <= isIDLE; --- end if; --- -- end loop; --- end if; --- end process; --- --- TRIGGER_INITIALIZATION_SEQUENCE_PULSE1 : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- -- for i in 2 downto 0 loop --- trigger_start_pulse_MAPS_CLK(1) <= '0'; --- trigger_reset_pulse_MAPS_CLK(1) <= '0'; --- trigger_jtag_run_MAPS_CLK(1) <= '0'; --- case init_seq_MAPS_CLK_1 is --- when isIDLE => --- when isRUN_JTAG_WAIT1 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT2; --- when isRUN_JTAG_WAIT2 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT3; --- when isRUN_JTAG_WAIT3 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT4; --- when isRUN_JTAG_WAIT4 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT5; --- when isRUN_JTAG_WAIT5 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT6; --- when isRUN_JTAG_WAIT6 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT7; --- when isRUN_JTAG_WAIT7 => --- init_seq_MAPS_CLK_1 <= isRUN_JTAG; --- when isRUN_JTAG => --- if(resetafterfirstwrite(1) = '1') then --- if(request_reset(1) = '1') then --- trigger_reset_pulse_MAPS_CLK(1) <= '1'; --- end if; --- end if; --- -- wait for completion of potential copy ram request and then finishing of run --- if(idle_out_MAPS_CLK(1) = '1') then --- init_seq_MAPS_CLK_1 <= isWAITBEFORESTART; --- waitbeforestart_counter(1) <= waitbeforestart; --- end if; --- when isWAITBEFORESTART => --- waitbeforestart_counter(1) <= waitbeforestart_counter(1) -1; --- if(waitbeforestart_counter(1) = waitbeforestart_counter_zero) then --- trigger_start_pulse_MAPS_CLK(1) <= '1'; --- init_seq_MAPS_CLK_1 <= isIDLE; --- end if; --- end case; --- if(trbnet_trigger_initialization_sequence_MAPS_CLK(1) = '1') then --- if(resetbeforeinit(1) = '1') then --- trigger_reset_pulse_MAPS_CLK(1) <= '1'; --- end if; --- trigger_jtag_run_MAPS_CLK(1) <= '1'; --- init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT1; --- end if; --- if(RESET = '1') then --- init_seq_MAPS_CLK_1 <= isIDLE; --- end if; --- -- end loop; --- end if; --- end process; --- --- TRIGGER_INITIALIZATION_SEQUENCE_PULSE2 : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- --for i in 2 downto 0 loop --- trigger_start_pulse_MAPS_CLK(2) <= '0'; --- trigger_reset_pulse_MAPS_CLK(2) <= '0'; --- trigger_jtag_run_MAPS_CLK(2) <= '0'; --- case init_seq_MAPS_CLK_2 is --- when isIDLE => --- when isRUN_JTAG_WAIT1 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT2; --- when isRUN_JTAG_WAIT2 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT3; --- when isRUN_JTAG_WAIT3 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT4; --- when isRUN_JTAG_WAIT4 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT5; --- when isRUN_JTAG_WAIT5 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT6; --- when isRUN_JTAG_WAIT6 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT7; --- when isRUN_JTAG_WAIT7 => --- init_seq_MAPS_CLK_2 <= isRUN_JTAG; --- when isRUN_JTAG => --- if(resetafterfirstwrite(2) = '1') then --- if(request_reset(2) = '1') then --- trigger_reset_pulse_MAPS_CLK(2) <= '1'; --- end if; --- end if; --- -- wait for completion of potential copy ram request and then finishing of run --- if(idle_out_MAPS_CLK(2) = '1') then --- init_seq_MAPS_CLK_2 <= isWAITBEFORESTART; --- waitbeforestart_counter(2) <= waitbeforestart; --- end if; --- when isWAITBEFORESTART => --- waitbeforestart_counter(2) <= waitbeforestart_counter(2) -1; --- if(waitbeforestart_counter(2) = waitbeforestart_counter_zero) then --- trigger_start_pulse_MAPS_CLK(2) <= '1'; --- init_seq_MAPS_CLK_2 <= isIDLE; --- end if; --- end case; --- if(trbnet_trigger_initialization_sequence_MAPS_CLK(2) = '1') then --- if(resetbeforeinit(2) = '1') then --- trigger_reset_pulse_MAPS_CLK(2) <= '1'; --- end if; --- trigger_jtag_run_MAPS_CLK(2) <= '1'; --- init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT1; --- end if; --- if(RESET = '1') then --- init_seq_MAPS_CLK_2 <= isIDLE; --- end if; --- -- end loop; --- end if; --- end process; --- --- TRIGGER_ALLCHAINS_INITIALIZATION_SEQUENCE_PULSE : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- trigger2_reset_pulse_MAPS_CLK <= "000"; --- trigger_jtag_run2_MAPS_CLK <= "000"; --- trigger_allchains_start_pulse_MAPS_CLK <= '0'; --- case init_seq_allchains_MAPS_CLK is --- when isIDLE => --- when isRUN_JTAG_WAIT1 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT2; --- when isRUN_JTAG_WAIT2 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT3; --- when isRUN_JTAG_WAIT3 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT4; --- when isRUN_JTAG_WAIT4 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT5; --- when isRUN_JTAG_WAIT5 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT6; --- when isRUN_JTAG_WAIT6 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT7; --- when isRUN_JTAG_WAIT7 => --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG; --- when isRUN_JTAG => --- for i in 2 downto 0 loop --- if(resetafterfirstwrite(i) = '1') then --- if(request_reset_MAPS_CLK(i) = '1') then --- trigger2_reset_pulse_MAPS_CLK(i) <= '1'; --- end if; --- end if; --- end loop; --- if(idle_out_MAPS_CLK(0) = '1' and idle_out_MAPS_CLK(1) = '1' and idle_out_MAPS_CLK(2) = '1') then --- init_seq_allchains_MAPS_CLK <= isWAITBEFORESTART; --- waitbeforestart_counter_allchains <= waitbeforestart; --- end if; --- when isWAITBEFORESTART => --- waitbeforestart_counter_allchains <= waitbeforestart_counter_allchains -1; --- if(waitbeforestart_counter_allchains = waitbeforestart_counter_zero) then --- trigger_allchains_start_pulse_MAPS_CLK <= '1'; --- init_seq_allchains_MAPS_CLK <= isIDLE; --- end if; --- end case; --- if(trbnet_trigger_allchains_initialization_sequence_MAPS_CLK = '1') then --- for i in 2 downto 0 loop --- if(resetbeforeinit(i) = '1') then --- trigger2_reset_pulse_MAPS_CLK(i) <= '1'; --- end if; --- end loop; --- trigger_jtag_run2_MAPS_CLK <= "111"; --- init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT1; --- end if; --- --- if(RESET = '1') then --- init_seq_allchains_MAPS_CLK <= isIDLE; --- end if; --- end if; --- end process; --- --- --- --- -- spill trigger (MAPS_CLK) --- JTAG_CMD_M26C_MAPS_CLK : process(MAPS_CLK, RESET) --- begin --- if(rising_edge(MAPS_CLK)) then --- prog_jtag_finished_MAPS_CLK(0) <= prog_jtag_finished; --- prog_jtag_finished_MAPS_CLK(1) <= prog_jtag_finished2; --- prog_jtag_finished_MAPS_CLK(2) <= prog_jtag_finished3; --- idle_out_MAPS_CLK(0) <= idle_out; --- idle_out_MAPS_CLK(1) <= idle_out2; --- idle_out_MAPS_CLK(2) <= idle_out3; --- if(RESET='1') then --- prog_jtag_finished_MAPS_CLK(0) <= '0'; --- prog_jtag_finished_MAPS_CLK(1) <= '0'; --- prog_jtag_finished_MAPS_CLK(2) <= '0'; --- idle_out_MAPS_CLK(0) <= '0'; --- idle_out_MAPS_CLK(1) <= '0'; --- idle_out_MAPS_CLK(2) <= '0'; --- end if; --- end if; --- end process; --- --- --- -- the_IODELAY : IODELAY --- -- generic map ( --- -- DELAY_SRC => "I", -- Specify which input port to be used --- -- -- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional --- -- HIGH_PERFORMANCE_MODE => TRUE, -- TRUE specifies lower jitter --- -- -- at expense of more power --- -- IDELAY_TYPE => "DEFAULT", -- "DEFAULT", "FIXED" or "VARIABLE" --- -- IDELAY_VALUE => 0, -- 0 to 63 tap values --- -- ODELAY_VALUE => 0, -- 0 to 63 tap values --- -- REFCLK_FREQUENCY => 200.0, -- Frequency used for IDELAYCTRL --- -- -- 175.0 to 225.0 --- -- SIGNAL_PATTERN => "DATA") -- Input signal type, "CLOCK" or "DATA" --- -- port map ( --- -- DATAOUT => DATAOUT, -- 1-bit delayed data output --- -- C => C, -- 1-bit clock input --- -- CE => CE, -- 1-bit clock enable input --- -- DATAIN => DATAIN, -- 1-bit internal data input --- -- IDATAIN => IDATAIN, -- 1-bit input data input (connect to port) --- -- INC => INC, -- 1-bit increment/decrement input --- -- ODATAIN => ODATAIN, -- 1-bit output data input --- -- RST => RST, -- 1-bit active high, synch reset input --- -- T => T -- 1-bit 3-state control input --- -- ); --- --- --- --- --************************************************************************************************************************* --- -- The LOGIC ************************************************************************************************************** --- --************************************************************************************************************************* --- --- -- --- -- --- -- -- LEDs --- -- DGOOD <= not tlk_STAT_OP(9); --- -- DBAD <= not (tlk_STAT(36)); -- no error, but not ERROR_OK --- -- DINT <= counter(25); --- -- DWAIT <= not (tlk_STAT_OP(10) or tlk_STAT_OP(11)); --- -- -- --- --- --- --- --- -- MAPS CLK output --- -- Inst_dcm3: dcm3 PORT MAP( --- -- CLKIN_IN => TLK_RX_CLK, --- -- RST_IN => '0', --- -- CLKFX_OUT => MAPS_CLK, --- -- CLK0_OUT => open, --- -- LOCKED_OUT => open --- -- ); --- --- Inst_dcm4: dcm4 PORT MAP( --- CLKIN_IN => TLK_RX_CLK, --- RST_IN => '0', --- CLKFX_OUT => MAPS_CLK, --- CLKIN_IBUFG_OUT => open, --- CLK0_OUT => dcm4_CLK0_OUT, --- LOCKED_OUT => open --- ); --- --- --- --TEST_out <= jtag_tck; --- --TEST_out <= prog_jtag_finished; --- --TEST_out <= '0'; --- -- JTAG1_TCK_OUT <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6); --- -- JTAG1_TMS_OUT <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4); --- -- JTAG1_TDI_OUT <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2); --- -- JTAG2_TCK_OUT <= (jtag_tck2 xor signals_invert2(6)) when signals_invert2(7) = '1' else signals_invert2(6); --- -- JTAG2_TMS_OUT <= (jtag_tms2 xor signals_invert2(4)) when signals_invert2(5) = '1' else signals_invert2(4); --- -- JTAG2_TDI_OUT <= (jtag_tdi2 xor signals_invert2(2)) when signals_invert2(3) = '1' else signals_invert2(2); --- -- JTAG3_TCK_OUT <= (jtag_tck3 xor signals_invert3(6)) when signals_invert3(7) = '1' else signals_invert3(6); --- -- JTAG3_TMS_OUT <= (jtag_tms3 xor signals_invert3(4)) when signals_invert3(5) = '1' else signals_invert3(4); --- -- JTAG3_TDI_OUT <= (jtag_tdi3 xor signals_invert3(2)) when signals_invert3(3) = '1' else signals_invert3(2); --- -- x1_saddr(3) <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6); --- -- x1_saddr(2) <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4); --- -- x1_saddr(1) <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2); --- -- x1_saddr(0) <= JTAG_TDO_IN; --- -- jtag_tdo_evtlinv <= (JTAG1_TDO_IN xor signals_invert(0)) when signals_invert(1) = '1' else signals_invert(0); --- -- jtag_tdo_evtlinv2 <= (JTAG2_TDO_IN xor signals_invert2(0)) when signals_invert2(1) = '1' else signals_invert2(0); --- -- jtag_tdo_evtlinv3 <= (JTAG3_TDO_IN xor signals_invert3(0)) when signals_invert3(1) = '1' else signals_invert3(0); --- --- -- MAPS_CLK1_out_int <= signals_invert(12); --- -- MAPS_CLK1_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12); --- -- MAPS_CLK2_out_int <= signals_invert2(12); --- -- MAPS_CLK2_out_int2 <= (not signals_invert2(12)) when signals_invert2(13) = '1' else signals_invert2(12); --- -- MAPS_CLK3_out_int <= signals_invert3(12); --- -- MAPS_CLK3_out_int2 <= (not signals_invert3(12)) when signals_invert3(13) = '1' else signals_invert3(12); --- --- -- ODDR_MAPS_CLK1_out : ODDR --- -- generic map( --- -- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" --- -- INIT => '0', -- Initial value for Q port ('1' or '0') --- -- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") --- -- port map ( --- -- Q => MAPS_CLK1_out, -- 1-bit DDR output --- -- C => MAPS_CLK, -- 1-bit clock input --- -- CE => '1', -- 1-bit clock enable input --- -- D1 => MAPS_CLK1_out_int, -- 1-bit data input (positive edge) -- inverted output --- -- D2 => MAPS_CLK1_out_int2, -- 1-bit data input (negative edge) -- inverted output --- -- R => '0', -- 1-bit reset input --- -- S => '0' -- 1-bit set input --- -- ); --- -- --- -- ODDR_MAPS_CLK2_out : ODDR --- -- generic map( --- -- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" --- -- INIT => '0', -- Initial value for Q port ('1' or '0') --- -- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") --- -- port map ( --- -- Q => MAPS_CLK2_out, -- 1-bit DDR output --- -- C => MAPS_CLK, -- 1-bit clock input --- -- CE => '1', -- 1-bit clock enable input --- -- D1 => MAPS_CLK2_out_int, -- 1-bit data input (positive edge) -- inverted output --- -- D2 => MAPS_CLK2_out_int2, -- 1-bit data input (negative edge) -- inverted output --- -- R => '0', -- 1-bit reset input --- -- S => '0' -- 1-bit set input --- -- ); --- -- --- -- ODDR_MAPS_CLK3_out : ODDR --- -- generic map( --- -- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" --- -- INIT => '0', -- Initial value for Q port ('1' or '0') --- -- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") --- -- port map ( --- -- Q => MAPS_CLK3_out, -- 1-bit DDR output --- -- C => MAPS_CLK, -- 1-bit clock input --- -- CE => '1', -- 1-bit clock enable input --- -- D1 => MAPS_CLK3_out_int, -- 1-bit data input (positive edge) -- inverted output --- -- D2 => MAPS_CLK3_out_int2, -- 1-bit data input (negative edge) -- inverted output --- -- R => '0', -- 1-bit reset input --- -- S => '0' -- 1-bit set input --- -- ); --- --- --- --- --- com_settings_all : process --- begin --- wait until (CLK'event and CLK='1'); --- com_settings_write_ack_out <= '0'; --- com_settings_dataready_out <= '0'; --- com_settings_unknown_addr_out <= '0'; --- com_settings_no_more_data_out <= '0'; --- if(com_settings_write_enable_in_last = '0') then --- -- reset triggers after 2 clock cycles at 100 MHz, to be able to sample at 80 MHz --- trbnet_trigger_allchains_initialization_sequence <= '0'; --- trbnet_trigger_allchains_reset_pulse <= '0'; --- trbnet_trigger_allchains_start_pulse <= '0'; --- trbnet_trigger_initialization_sequence <= (others => '0'); --- trbnet_trigger_reset_pulse <= (others => '0'); --- trbnet_trigger_start_pulse <= (others => '0'); --- trbnet_trigger_jtag_run_noreset <= (others => '0'); --- trbnet_trigger_jtag_write_once <= (others => '0'); --- end if; --- com_settings_write_enable_in_last <= com_settings_write_enable_in; --- if(com_settings_write_enable_in = '1') then --- if(com_settings_addr_in = x"01") then --- --fet_counter_limit <= com_settings_data_in; --- --com_settings_write_ack_out <= '1'; --- com_settings_unknown_addr_out <= '1'; --- elsif(com_settings_addr_in = x"02") then --- --jcounter_initvalue <= com_settings_data_in(28 downto 0); --- --com_settings_write_ack_out <= '1'; --- com_settings_unknown_addr_out <= '1'; --- elsif(com_settings_addr_in = x"03") then --- trbnet_trigger_allchains_initialization_sequence <= '1'; --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"06") then --- signals_invert(0) <= com_settings_data_in(13 downto 0); -- 13-12: MAPS_CLK, 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"07") then --- waitbeforestart <= unsigned(com_settings_data_in(27 downto 0)); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"08") then --- signals_invert(1) <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"09") then --- signals_invert(2) <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"0a") then --- trbnet_trigger_allchains_reset_pulse <= com_settings_data_in(0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"0b") then --- trbnet_trigger_allchains_start_pulse <= com_settings_data_in(0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"0c") then --- trbnet_trigger_initialization_sequence <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"0d") then --- trbnet_trigger_reset_pulse <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"0e") then --- trbnet_trigger_start_pulse <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"0f") then --- trbnet_trigger_jtag_run_noreset <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"10") then --- resetbeforeinit <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"11") then --- resetafterfirstwrite <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- elsif(com_settings_addr_in = x"14") then --- trbnet_trigger_jtag_write_once <= com_settings_data_in(2 downto 0); --- com_settings_write_ack_out <= '1'; --- end if; --- elsif(com_settings_read_enable_in = '1') then --- if(com_settings_addr_in = x"01") then --- com_settings_data_out <= (others => '0'); --- com_settings_unknown_addr_out <= '1'; --- elsif(com_settings_addr_in = x"02") then --- com_settings_data_out <= (others => '0'); --- com_settings_unknown_addr_out <= '1'; --- elsif(com_settings_addr_in = x"04") then --- com_settings_data_out <= (others => '0'); --- com_settings_unknown_addr_out <= '1'; --- elsif(com_settings_addr_in = x"05") then --- com_settings_data_out <= (others => '0'); --- com_settings_unknown_addr_out <= '1'; --- elsif(com_settings_addr_in = x"06") then --- com_settings_data_out(13 downto 0) <= signals_invert(0); --- com_settings_data_out(31 downto 14) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"07") then --- com_settings_data_out(27 downto 0) <= std_logic_vector(waitbeforestart); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"08") then --- com_settings_data_out(13 downto 0) <= signals_invert(1); --- com_settings_data_out(31 downto 14) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"09") then --- com_settings_data_out(13 downto 0) <= signals_invert(2); --- com_settings_data_out(31 downto 14) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"10") then --- com_settings_data_out(2 downto 0) <= resetbeforeinit; --- com_settings_data_out(31 downto 3) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"11") then --- com_settings_data_out(2 downto 0) <= resetafterfirstwrite; --- com_settings_data_out(31 downto 3) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"12") then --- com_settings_data_out(6 downto 0) <= std_logic_vector(MAPS_reset_count(0)(6 downto 0)); --- com_settings_data_out(31 downto 7) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- elsif(com_settings_addr_in = x"13") then --- com_settings_data_out(6 downto 0) <= std_logic_vector(MAPS_start_count(0)(6 downto 0)); --- com_settings_data_out(31 downto 7) <= (others => '0'); --- com_settings_dataready_out <= '1'; --- end if; --- end if; --- if(RESET = '1') then --- resetbeforeinit <= (others => '0'); --- resetafterfirstwrite <= (others => '0'); --- waitbeforestart <= (others => '0'); --- --- com_settings_data_out <= (others => '0'); --- com_settings_dataready_out <= '0'; --- com_settings_write_ack_out <= '0'; --- com_settings_write_enable_in_last <= '0'; --- com_settings_no_more_data_out <= '0'; --- com_settings_unknown_addr_out <= '0'; --- --- --- trbnet_trigger_allchains_initialization_sequence <= '0'; --- trbnet_trigger_allchains_reset_pulse <= '0'; --- trbnet_trigger_allchains_start_pulse <= '0'; --- trbnet_trigger_initialization_sequence <= (others => '0'); --- trbnet_trigger_reset_pulse <= (others => '0'); --- trbnet_trigger_start_pulse <= (others => '0'); --- trbnet_trigger_jtag_run_noreset <= (others => '0'); --- trbnet_trigger_jtag_write_once <= (others => '0'); --- end if; --- end process; --- --- -- 2.43.0