From 17ba66f68eb5f0abe7aa664b3b9edf28ee3eb1cc Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Wed, 29 Sep 2010 13:19:22 +0000
Subject: [PATCH] *** empty log message ***

---
 special/handler_lvl1.vhd | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd
index fa20173..12ac610 100644
--- a/special/handler_lvl1.vhd
+++ b/special/handler_lvl1.vhd
@@ -12,6 +12,7 @@ generic(
 );
 port(
 	RESET                        : in  std_logic;
+	RESET_STATS_IN               : in  std_logic;
 	CLOCK                        : in  std_logic;
 	--Timing Trigger
 	LVL1_TIMING_TRG_IN           : in  std_logic;    --raw trigger signal input, min. 80 ns or strobe, see generics
@@ -496,7 +497,7 @@ end process COUNT_EDGES_AND_LENGTH_PROC;
 -- gk 29.09.10
 WRONG_POLAR_PROC : process(CLOCK)
 begin
-	if (RESET = '1') then
+	if (RESET = '1') or (RESET_STATS_IN = '1') then
 		wrong_polarity <= '0';
 	elsif (trigger_length > 100) then
 		wrong_polarity <= '1';
@@ -540,10 +541,11 @@ end process THE_MEASURED_DELAY_PROC;
 -- Status bits
 ---------------------------------------------------------------------------
 
+-- gk 29.09.10
 STAT_PROC : process(CLOCK)
 begin
 	if rising_edge(CLOCK) then
-		if (RESET = '1') then
+		if (RESET = '1') or (RESET_STATS_IN = '1') then
 			STATUS_OUT <= (others => '0');
 		elsif (val_trg = '1') or (invalid_trg = '1') then
 			STATUS_OUT(63 downto 48)  <= std_logic_vector(trigger_length);
@@ -569,7 +571,7 @@ end process STAT_PROC;
 STAT_CTR_PROC : process(CLOCK)
 begin
 	if rising_edge(CLOCK) then
-		if (RESET = '1') then
+		if (RESET = '1') or (RESET_STATS_IN = '1') then
 			multiple_ctr <= (others => '0');
 			missing_ctr  <= (others => '0');
 			spikes_ctr   <= (others => '0');
-- 
2.43.0