From 17dd888de508b1e1b274422b0f6ac3559091c89e Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Tue, 23 Feb 2021 20:38:23 +0100 Subject: [PATCH] XCKU MGTs: Remove TX PROGDIV and Buffer Bypass This turned out to be the wrong approach to achieving deterministic TX latency. The TX phase interpolator (PI) will be used instead. --- media_interfaces/med_xcku_sfp_sync.vhd | 176 +- .../gth_xcku_2gbps4_120mhz_txprogdiv240.xci | 1430 - .../gth_xcku_2gbps4_120mhz_txprogdiv240.xml | 22428 --------------- ...2gbps4_120mhz_txprogdiv240_txbufbypass.xci | 1432 - ...2gbps4_120mhz_txprogdiv240_txbufbypass.xml | 22449 ---------------- media_interfaces/xcku/gth_xcku_top.vhd | 519 +- .../xcku/gtwizard_ultrascale_v1_7_bit_sync.v | 88 - ...zard_ultrascale_v1_7_gtwiz_buffbypass_tx.v | 258 - .../gtwizard_ultrascale_v1_7_reset_inv_sync.v | 98 - 9 files changed, 130 insertions(+), 48748 deletions(-) delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240/gth_xcku_2gbps4_120mhz_txprogdiv240.xci delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240/gth_xcku_2gbps4_120mhz_txprogdiv240.xml delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass.xci delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass.xml delete mode 100644 media_interfaces/xcku/gtwizard_ultrascale_v1_7_bit_sync.v delete mode 100644 media_interfaces/xcku/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v delete mode 100644 media_interfaces/xcku/gtwizard_ultrascale_v1_7_reset_inv_sync.v diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd index f4e831c..7210f7a 100644 --- a/media_interfaces/med_xcku_sfp_sync.vhd +++ b/media_interfaces/med_xcku_sfp_sync.vhd @@ -15,96 +15,70 @@ entity med_xcku_sfp_sync is IS_SYNC_SLAVE : integer := c_NO; LINE_RATE_KBPS : integer := 2000000; REFCLK_FREQ_HZ : integer := 100000000; - USE_TXPROGDIV : integer range 0 to 1 := 0; - BYPASS_TXBUF : integer range 0 to 1 := 0; SOFT_RESET_TX : integer range 0 to 1 := 1 ); port ( - SYSCLK : in std_logic; - CLK_100 : in std_logic; - RESET_ALL : in std_logic := '0'; - GTREFCLK : in std_logic; - GTREFCLK_BUFG : in std_logic; - RXOUTCLK : out std_logic; - TXOUTCLK : out std_logic; - RXUSRCLK : in std_logic; - RXUSRCLK_DOUBLE : in std_logic; - TXUSRCLK : in std_logic; - TXUSRCLK_DOUBLE : in std_logic; - - RXUSRCLK_ACTIVE : in std_logic; - TXUSRCLK_ACTIVE : in std_logic; - RXPMARESETDONE : out std_logic; - TXPMARESETDONE : out std_logic; - RXRESETDONE : out std_logic; - TXRESETDONE : out std_logic; - - RESET : in std_logic; - CLEAR : in std_logic; - - RXN : in std_logic; - RXP : in std_logic; - TXN : out std_logic; - TXP : out std_logic; - - MEDIA_MED2INT : out MED2INT; - MEDIA_INT2MED : in INT2MED; - - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector(7 downto 0) := (others => '0'); - TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := (others => '0'); - - SD_LOS_IN : in std_logic; - SD_TXDIS_OUT : out std_logic; - - STAT_DEBUG : out std_logic_vector(63 downto 0); - CTRL_DEBUG : in std_logic_vector(63 downto 0) := (others => '0'); - - DRPADDR : in std_logic_vector(8 downto 0) := (others => '0'); - DRPCLK : in std_logic := '0'; - DRPDI : in std_logic_vector(15 downto 0) := (others => '0'); - DRPEN : in std_logic := '0'; - DRPWE : in std_logic := '0'; - DRPDO : out std_logic_vector(15 downto 0); - DRPRDY : out std_logic; - - EYESCANRESET : in std_logic := '0'; - RXLPMEN : in std_logic := '1'; - RXRATE : in std_logic_vector(2 downto 0) := b"000"; - TXDIFFCTRL : in std_logic_vector(3 downto 0) := b"1100"; - TXPOSTCURSOR : in std_logic_vector(4 downto 0) := b"00000"; - TXPRECURSOR : in std_logic_vector(4 downto 0) := b"00000"; - - TXPRGDIVRESETDONE : out std_logic; - - TXPIPPMEN : in std_logic := '0'; - TXPIPPMOVRDEN : in std_logic := '0'; - TXPIPPMPD : in std_logic := '0'; - TXPIPPMSEL : in std_logic := '0'; - TXPIPPMSTEPSIZE : in std_logic_vector(4 downto 0) := "00000"; - - TXDLYBYPASS : in std_logic := '0'; - TXDLYEN : in std_logic := '0'; - TXDLYHOLD : in std_logic := '0'; - TXDLYOVRDEN : in std_logic := '0'; - TXDLYSRESET : in std_logic := '0'; - TXDLYUPDOWN : in std_logic := '0'; - TXPHALIGN : in std_logic := '0'; - TXPHALIGNEN : in std_logic := '0'; - TXPHDLYPD : in std_logic := '0'; - TXPHDLYRESET : in std_logic := '0'; - TXPHDLYTSTCLK : in std_logic := '0'; - TXPHINIT : in std_logic := '0'; - TXPHOVRDEN : in std_logic := '0'; - TXSYNCALLIN : in std_logic := '0'; - TXSYNCIN : in std_logic := '0'; - TXSYNCMODE : in std_logic := '0'; - TXDLYSRESETDONE : out std_logic; - TXPHALIGNDONE : out std_logic; - TXPHINITDONE : out std_logic; - TXSYNCDONE : out std_logic; - TXSYNCOUT : out std_logic + SYSCLK : in std_logic; + CLK_100 : in std_logic; + RESET_ALL : in std_logic := '0'; + GTREFCLK : in std_logic; + GTREFCLK_BUFG : in std_logic; + RXOUTCLK : out std_logic; + TXOUTCLK : out std_logic; + RXUSRCLK : in std_logic; + RXUSRCLK_DOUBLE : in std_logic; + TXUSRCLK : in std_logic; + TXUSRCLK_DOUBLE : in std_logic; + + RXUSRCLK_ACTIVE : in std_logic; + TXUSRCLK_ACTIVE : in std_logic; + RXPMARESETDONE : out std_logic; + TXPMARESETDONE : out std_logic; + RXRESETDONE : out std_logic; + TXRESETDONE : out std_logic; + + RESET : in std_logic; + CLEAR : in std_logic; + + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; + + MEDIA_MED2INT : out MED2INT; + MEDIA_INT2MED : in INT2MED; + + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector(7 downto 0) := (others => '0'); + TX_DLM : in std_logic := '0'; + TX_DLM_WORD : in std_logic_vector(7 downto 0) := (others => '0'); + + SD_LOS_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + + STAT_DEBUG : out std_logic_vector(63 downto 0); + CTRL_DEBUG : in std_logic_vector(63 downto 0) := (others => '0'); + + DRPADDR : in std_logic_vector(8 downto 0) := (others => '0'); + DRPCLK : in std_logic := '0'; + DRPDI : in std_logic_vector(15 downto 0) := (others => '0'); + DRPEN : in std_logic := '0'; + DRPWE : in std_logic := '0'; + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_logic; + + EYESCANRESET : in std_logic := '0'; + RXLPMEN : in std_logic := '1'; + RXRATE : in std_logic_vector(2 downto 0) := b"000"; + TXDIFFCTRL : in std_logic_vector(3 downto 0) := b"1100"; + TXPOSTCURSOR : in std_logic_vector(4 downto 0) := b"00000"; + TXPRECURSOR : in std_logic_vector(4 downto 0) := b"00000"; + + TXPIPPMEN : in std_logic := '0'; + TXPIPPMOVRDEN : in std_logic := '0'; + TXPIPPMPD : in std_logic := '0'; + TXPIPPMSEL : in std_logic := '0'; + TXPIPPMSTEPSIZE : in std_logic_vector(4 downto 0) := "00000" ); end entity; @@ -171,9 +145,7 @@ begin THE_SERDES : entity work.gth_xcku_top generic map ( LINE_RATE_KBPS => LINE_RATE_KBPS, - REFCLK_FREQ_HZ => REFCLK_FREQ_HZ, - USE_TXPROGDIV => USE_TXPROGDIV, - BYPASS_TXBUF => BYPASS_TXBUF + REFCLK_FREQ_HZ => REFCLK_FREQ_HZ ) port map ( CLK_100 => CLK_100, @@ -223,33 +195,11 @@ begin TXDIFFCTRL => TXDIFFCTRL, TXPOSTCURSOR => TXPOSTCURSOR, TXPRECURSOR => TXPRECURSOR, - TXPRGDIVRESETDONE => TXPRGDIVRESETDONE, TXPIPPMEN => TXPIPPMEN, TXPIPPMOVRDEN => TXPIPPMOVRDEN, TXPIPPMPD => TXPIPPMPD, TXPIPPMSEL => TXPIPPMSEL, - TXPIPPMSTEPSIZE => TXPIPPMSTEPSIZE, - TXDLYBYPASS => TXDLYBYPASS, - TXDLYEN => TXDLYEN, - TXDLYHOLD => TXDLYHOLD, - TXDLYOVRDEN => TXDLYOVRDEN, - TXDLYSRESET => TXDLYSRESET, - TXDLYUPDOWN => TXDLYUPDOWN, - TXPHALIGN => TXPHALIGN, - TXPHALIGNEN => TXPHALIGNEN, - TXPHDLYPD => TXPHDLYPD, - TXPHDLYRESET => TXPHDLYRESET, - TXPHDLYTSTCLK => TXPHDLYTSTCLK, - TXPHINIT => TXPHINIT, - TXPHOVRDEN => TXPHOVRDEN, - TXSYNCALLIN => TXSYNCALLIN, - TXSYNCIN => TXSYNCIN, - TXSYNCMODE => TXSYNCMODE, - TXDLYSRESETDONE => TXDLYSRESETDONE, - TXPHALIGNDONE => TXPHALIGNDONE, - TXPHINITDONE => TXPHINITDONE, - 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- 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - bufgtrstmask_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - cpllfbclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - cplllock_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - cpllrefclklost_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - dmonitorout_out - - out - - 16 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - dmonitoroutclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - drpdo_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - drprdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - eyescandataerror_out - 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C_TX_USER_DATA_WIDTH - 16 - - - C_TX_USRCLK_FREQUENCY - 120.0000000 - - - C_TX_USRCLK2_FREQUENCY - 120.0000000 - - - - - - choice_list_00d9575a - 16 - 32 - 64 - - - choice_list_04c1b6c3 - RXOUTCLKPMA - RXOUTCLKPCS - RXPLLREFCLK_DIV1 - RXPROGDIVCLK - - - choice_list_0fbde0c1 - 20 - - - choice_list_13717074 - -20 - -40 - - - choice_list_24871ac1 - AC - DC - - - choice_list_39947cc7 - TXOUTCLKPMA - TXOUTCLKPCS - TXPLLREFCLK_DIV1 - TXPROGDIVCLK - - - choice_list_556e59ba - 0 - 100 - 200 - 300 - 400 - 500 - 600 - 700 - 800 - 900 - 1000 - 1100 - 1200 - 1300 - 1400 - 1500 - 1600 - 1700 - 1800 - 1900 - 2000 - 2100 - 2200 - 2300 - 2400 - 2500 - 2600 - 2700 - 2800 - 2900 - 3000 - 3100 - 3200 - 3300 - 3400 - 3500 - 3600 - 3700 - 3800 - 3900 - 4000 - 4100 - 4200 - 4300 - 4400 - 4500 - 4600 - 4700 - 4800 - 4900 - 5000 - 5100 - 5200 - 5300 - 5400 - 5500 - 5600 - 5700 - 5800 - 5900 - 6000 - 6100 - 6200 - 6300 - 6400 - 6500 - 6600 - 6700 - 6800 - 6900 - 7000 - 7100 - 7200 - 7300 - 7400 - 7500 - 7600 - 7700 - 7800 - 7900 - 8000 - 8100 - 8200 - 8300 - 8400 - 8500 - 8600 - 8700 - 8800 - 8900 - 9000 - 9100 - 9200 - 9300 - 9400 - 9500 - 9600 - 9700 - 9800 - 9900 - 10000 - - - choice_list_6b979ebc - 250 - - - choice_list_7612b160 - X0Y8 - - - choice_list_818913bc - 96 - 120 - 150 - 160 - 192 - 200 - 240 - 300 - 320 - 384 - 400 - 480 - 600 - 640 - 800 - - - choice_list_822b7946 - CPLL - - - choice_list_98c4d361 - 257.8125 - - - choice_list_a0d11b39 - 100 - 200 - 250 - 300 - 350 - 400 - 500 - 550 - 600 - 700 - 800 - 850 - 900 - 950 - 1000 - 1100 - - - choice_list_a533ccf9 - 250 - 125 - 62.5 - - - choice_list_afcf1f92 - GTH - - - choice_list_afd99295 - 120 - 240 - 480 - - - choice_list_be18be20 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_list_de3f4419 - QPLL1 - CPLL - - - choice_list_e6469819 - 1 - 2 - 4 - - - choice_pairs_03018cc1 - 1 - 2 - 0 - - - choice_pairs_0c77e1fe - 0 - 1 - - - choice_pairs_1040277f - AVTT - FLOAT - GND - PROGRAMMABLE - - - choice_pairs_1436b008 - MULTI - SINGLE - - - choice_pairs_1ebf969f - None - GTH-10GBASE-KR - GTH-10GBASE-R - GTH-12G_SDI - GTH-1G_10G_25G_switchable - GTH-3G_SDI - GTH-Aurora_64B66B - GTH-Aurora_8B10B - GTH-Bandwidth_Engine - GTH-CAUI_10 - GTH-CEI_11G_SR - GTH-CPRI_10G - GTH-CPRI_10_1G - GTH-CPRI_3G - GTH-CPRI_6G - GTH-DisplayPort_1_62G - GTH-DisplayPort_2_7G - GTH-DisplayPort_5_4G - GTH-Gigabit_Ethernet - GTH-HDMI - GTH-HD_SDI - GTH-HMC_12_5G - GTH-Interlaken_10G - GTH-Interlaken_12_5G - GTH-Interlaken_6_25G - GTH-JESD204 - GTH-JESD204_3_125G - GTH-JESD204_6_375G - GTH-OTL4_10 - GTH-OTU2 - GTH-OTU2e - GTH-QSGMII - GTH-RXAUI - GTH-SATA - GTH-SRIO_Gen2 - GTH-XAUI - GTH-XLAUI - - - choice_pairs_40d02874 - 10GBASE_KR - CUSTOM - PCIE_GEN1_GEN2 - PCIE_GEN3 - QPI - - - choice_pairs_4e550952 - NONE - EXAMPLE_DESIGN - - - choice_pairs_7b0c3758 - RX - BOTH - TX - - - choice_pairs_85f99b7f - K28.1 - K28.5 - NONE - - - choice_pairs_8846c8f0 - RAW - 8B10B - 64B66B - 64B66B_CAUI - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_88c85933 - 8B10B - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - RAW - 64B66B - 64B66B_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_93c2d4ee - CORE - EXAMPLE_DESIGN - - - choice_pairs_9c19f015 - 1 - 2 - - - choice_pairs_a537ddda - 0 - 1 - - - choice_pairs_aa541099 - AUTO - DFE - LPM - - - choice_pairs_ae574462 - OFF - PCS - PMA - AUTO - - - choice_pairs_b0974ef0 - 1 - 2 - 0 - - - choice_pairs_d4feb97d - DISABLE - ENABLE - - - choice_pairs_f05b8192 - CHANNEL - NAME - - - The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. - - - GT_TYPE - Transceiver type - For devices which contain more than one serial transceiver type, select the type of transceiver to configure - GTH - - - INTERNAL_GT_PRIM_TYPE - gthe3 - - - - false - - - - - - GT_REV - Transceiver revision - Select the serial transceiver silicon revision - 0 - - - GT_DIRECTION - Transmit and/or Receive direction - Enable transmit and/or receive - BOTH - - - RX_ENABLE - Enabled - Enable the receiver for use - true - - - - false - - - - - - TX_ENABLE - Enabled - Enable the transmitter for use - true - - - - false - - - - - - CHANNEL_ENABLE - Enable channel - Indicate whether this transceiver channel is instantiated and enabled for use - X0Y8 - - - TX_MASTER_CHANNEL - Master TX channel - Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - RX_MASTER_CHANNEL - Master RX channel - Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - INTERNAL_TOTAL_NUM_CHANNELS - Total number of channels - 1 - - - - false - - - - - - INTERNAL_TOTAL_NUM_COMMONS - Total number of commons required - 0 - - - - false - - - - - - LOCATE_COMMON - Include transceiver COMMON in the - If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. - CORE - - - - false - - - - - - INTERNAL_NUM_COMMONS_CORE - Number of commons in core - 0 - - - - false - - - - - - INTERNAL_NUM_COMMONS_EXAMPLE - Number of commons in example - 0 - - - - false - - - - - - INTERNAL_TX_USRCLK_FREQUENCY - 120.0000000 - - - - false - - - - - - INTERNAL_RX_USRCLK_FREQUENCY - 120.0000000 - - - - false - - - - - - RX_PPM_OFFSET - PPM offset between receiver and transmitter - Specify the PPM offset between received data and transmitted data - 0 - - - OOB_ENABLE - Enable Out of Band signaling (OOB)/Electrical Idle - Enable or disable Out of Band signaling (OOB)/Electrical Idle - false - - - - false - - - - - - RX_SSC_PPM - Spread spectrum clocking - Specify the spread spectrum clocking modulation in PPM - 0 - - - INS_LOSS_NYQ - Insertion loss at Nyquist (dB) - Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB - 20 - - - PCIE_CORECLK_FREQ - 250 - - - PCIE_USERCLK_FREQ - 250 - - - TX_LINE_RATE - Line rate (Gb/s) - Enter the transmitter line rate in Gb/s - 2.4 - - - TX_PLL_TYPE - PLL type - Select the transmitter PLL type - CPLL - - - TX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 120 - - - TX_DATA_ENCODING - Encoding - Select the encoding format for data transmission, or choose 'Raw' for no data encoding - 8B10B - - - TX_USER_DATA_WIDTH - User data width - Select the width at which the user logic will provide parallel data to the serial transceiver for transmission - 16 - - - TX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal transmitter data path - 20 - - - TX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the transmitter buffer - 1 - - - TX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection - 0 - - - - false - - - - - - TX_OUTCLK_SOURCE - TXOUTCLK source - Select the source of TXOUTCLK - TXPROGDIVCLK - - - TX_DIFF_SWING_EMPH_MODE - Differential swing and emphasis mode - Select the transmitter differential swing and emphasis mode for your application - CUSTOM - - - RX_LINE_RATE - Line rate (Gb/s) - Enter the receiver line rate in Gb/s - 2.4 - - - RX_PLL_TYPE - PLL type - Select the receiver PLL type - CPLL - - - RX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 120 - - - RX_DATA_DECODING - Decoding - Select the decoding format for data reception, or choose 'Raw' for no data decoding - 8B10B - - - RX_USER_DATA_WIDTH - User data width - Select the width at which the serial transceiver will provide received parallel data to the user logic - 16 - - - RX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal receiver data path - 20 - - - RX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the receiver elastic buffer - 1 - - - RX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection - 0 - - - - false - - - - - - RX_EQ_MODE - Equalization mode - Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - LPM - - - RX_JTOL_FC - Mask corner frequency (MHz) - Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. - 1.4397121 - - - RX_JTOL_LF_SLOPE - Mask low frequency slope (dB/decade) - Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. - -20 - - - RX_OUTCLK_SOURCE - RXOUTCLK source - Select the source of RXOUTCLK - RXOUTCLKPMA - - - SIM_CPLL_CAL_BYPASS - 1 - - - PCIE_ENABLE - false - - - RX_TERMINATION - Termination - Select the receiver termination - PROGRAMMABLE - - - RX_TERMINATION_PROG_VALUE - Programmable termination voltage (mV) - Select the termination voltage (in mV) when in programmable mode - 800 - - - RX_COUPLING - Link coupling - Select the link coupling - AC - - - RX_BUFFER_BYPASS_MODE - Receiver elastic buffer bypass mode - Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode - MULTI - - - - false - - - - - - RX_BUFFER_RESET_ON_CB_CHANGE - Reset receiver elastic buffer on channel bonding change - Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL - ENABLE - - - - false - - - - - - RX_BUFFER_RESET_ON_COMMAALIGN - Reset receiver elastic buffer on comma alignment - Control whether the receiver elastic buffer is reset on comma alignment - DISABLE - - - RX_BUFFER_RESET_ON_RATE_CHANGE - Reset receiver elastic buffer on rate change - Control whether the receiver elastic buffer is reset on rate change - ENABLE - - - TX_BUFFER_RESET_ON_RATE_CHANGE - Reset transmitter buffer on rate change - Control whether the transmitter buffer is reset on rate change - ENABLE - - - RESET_SEQUENCE_INTERVAL - Reset sequence time interval (ns) - Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval - 0 - - - RX_COMMA_PRESET - Comma value preset - K28.5 - - - RX_COMMA_VALID_ONLY - Valid comma values for 8B/10B decoding - Select the range of comma characters decoded by the 8B/10B decoder - 0 - - - RX_COMMA_P_ENABLE - Detect plus comma - Indicate whether or not the specified bit pattern is detected as a plus comma - true - - - RX_COMMA_M_ENABLE - Detect minus comma - Indicate whether or not the specified bit pattern is detected as a minus comma - true - - - RX_COMMA_DOUBLE_ENABLE - Detect combined plus/minus (double-length) comma - Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence - false - - - RX_COMMA_P_VAL - Plus comma value - Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 0101111100 - - - RX_COMMA_M_VAL - Minus comma value - Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 1010000011 - - - RX_COMMA_MASK - Mask - Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 1111111111 - - - RX_COMMA_ALIGN_WORD - Alignment boundary - Select which data byte boundaries are allowed for comma alignment - 2 - - - RX_COMMA_SHOW_REALIGN_ENABLE - Show realign comma - Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency - true - - - RX_SLIDE_MODE - Manual alignment (RXSLIDE) mode - Select whether to enable manual alignment, and in what mode if enabled - OFF - - - RX_CB_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable channel bonding, and how many sequences to use if enabled - 0 - - - - false - - - - - - RX_CB_LEN_SEQ - Length of each sequence - Select the number of characters in each channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_SKEW - Sequence maximum skew - Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_LEVEL - Maximum channel bonding level to be used - Select the maximum channel bonding level that will be used in the system channel bonding topology - 1 - - - - false - - - - - - RX_CB_MASK - 00000000 - - - - false - - - - - - RX_CB_VAL - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - - - - false - - - - - - RX_CB_K - 00000000 - - - - false - - - - - - RX_CB_DISP - 00000000 - - - - false - - - - - - RX_CB_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable clock correction, and how many sequences to use if enabled - 2 - - - RX_CC_LEN_SEQ - Length of each sequence - Select the number of characters in each channel clock correction sequence - 4 - - - RX_CC_PERIODICITY - Periodicity of the sequence (in bytes) - Specify the separation between clock correction sequences, in bytes - 5000 - - - RX_CC_KEEP_IDLE - Keep idle - Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - ENABLE - - - RX_CC_PRECEDENCE - Precedence - Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time - ENABLE - - - - false - - - - - - RX_CC_REPEAT_WAIT - Minimum repetition - Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction - 0 - - - RX_CC_MASK - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - 00000000 - - - - false - - - - - - RX_CC_VAL - 00010100000010111100000101000000101111000001010000001011110000110001010010111100 - - - RX_CC_K - 01010101 - - - - false - - - - - - RX_CC_DISP - 00000000 - - - - false - - - - - - RX_CC_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_1 - Value - Specify the value for this clock correction sequence and pattern - 11000101 - - - RX_CC_K_0_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_0_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_1 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - ENABLE_OPTIONAL_PORTS - Enable optional ports - Indicate whether a port should be included - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txresetdone_out - - - RX_REFCLK_SOURCE - Receiver reference clock source - Select a reference clock input to drive the PLL chosen for receiver operation - X0Y8 clk0+2 - - - TX_REFCLK_SOURCE - Transmitter reference clock source - Select a reference clock input to drive the PLL chosen for transmitter operation - X0Y8 clk0+2 - - - RX_RECCLK_OUTPUT - Drive recovered clock out of device - Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use - - - - LOCATE_RESET_CONTROLLER - Include reset controller in the - Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - LOCATE_TX_BUFFER_BYPASS_CONTROLLER - Include transmitter buffer bypass controller in the - If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_RX_BUFFER_BYPASS_CONTROLLER - Include receiver elastic buffer bypass controller in the - If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_IN_SYSTEM_IBERT_CORE - Include In-System IBERT core - Indicate whether or not the In-System IBERT core should be instantiated in the example design. - EXAMPLE_DESIGN - - - LOCATE_TX_USER_CLOCKING - Include simple transmitter user clocking network in the - Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_RX_USER_CLOCKING - Include simple receiver user clocking network in the - Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_USER_DATA_WIDTH_SIZING - Include user data width sizing in the - Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - ORGANIZE_PORTS_BY - In the example design, organize ports across multiple channels by - If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) - NAME - - - - false - - - - - - PRESET - Transceiver configuration preset - You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard - None - - - INTERNAL_PRESET - Transceiver configuration preset - None - - - INTERNAL_PORT_USAGE_UPDATED - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLEMENT_UPDATED - 28 - - - - false - - - - - - INTERNAL_CHANNEL_SITES_UPDATED - 7 - - - - false - - - - - - INTERNAL_CHANNEL_COLUMN_LOC_MAX - 96 - - - - false - - - - - - INTERNAL_RX_COMMA_PRESET_UPDATE - 9 - - - - false - - - - - - INTERNAL_UPDATE_IP_SYMBOL_drpclk_in - true - - - - false - - - - - - SECONDARY_QPLL_ENABLE - Enable secondary QPLL - Enable and configure the QPLL which is not used in this core configuration - false - - - - false - - - - - - SECONDARY_QPLL_LINE_RATE - Line rate of second core (Gb/s) - Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL - 10.3125 - - - - false - - - - - - SECONDARY_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection - 0 - - - - false - - - - - - SECONDARY_QPLL_REFCLK_FREQUENCY - Actual Reference clock frequency (MHz) - Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate - 257.8125 - - - - false - - - - - - TXPROGDIV_FREQ_ENABLE - Enable selectable TXOUTCLK frequency - Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency - true - - - TXPROGDIV_FREQ_SOURCE - Programmable divider clock source - Select which PLL source is used to generate the selectable TXOUTCLK frequency - CPLL - - - TXPROGDIV_FREQ_VAL - TXOUTCLK frequency (MHz) - Select the TXOUTCLK frequency to be generated by the TX programmable divider - 240 - - - SATA_TX_BURST_LEN - TX COM sequence burst length - Select the number of bursts that make up a SATA COM sequence - 15 - - - FREERUN_FREQUENCY - Free-running and DRP clock frequency (MHz) - Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 - - - INCLUDE_CPLL_CAL - 2 - - - USER_GTPOWERGOOD_DELAY_EN - Select 1 to enable powergood delay circuit - 1 - - - DISABLE_LOC_XDC - Select to disable generation of LOC constraints in xdc - 0 - - - ENABLE_COMMON_USRCLK - 0 - - - USB_ENABLE - false - - - PCIE_64BIT - false - - - PCIE_GEN4_EIOS - false - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGBYPASSB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGMONITORENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGPDB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RCALENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONPOWERUP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDO_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBENABLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBINTR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBIOLMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMREGEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDADDR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDEN_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDI_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDWE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBTXUART_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSX_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CFGRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLPD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONFIFORESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITORCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANRESET_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_FREQOS_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXP_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK0_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRESETSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRSVD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_INCPCTRL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPBACK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPRSVD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN - 0 - - - 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xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtpowergood_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtrefclkmonitor_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - gtytxn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtytxp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - pcierategen3_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcierateidle_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcierateqpllpd_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcierateqpllreset_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pciesynctxsyncdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcieusergen3rdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcieuserphystatusrst_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcieuserratestart_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pcsrsvdout_out - - out - - 11 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - phystatus_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - pinrsrvdas_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - powerpresent_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - resetexception_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - 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96 - 120 - 150 - 160 - 192 - 200 - 240 - 300 - 320 - 384 - 400 - 480 - 600 - 640 - 800 - - - choice_list_822b7946 - CPLL - - - choice_list_98c4d361 - 257.8125 - - - choice_list_a0d11b39 - 100 - 200 - 250 - 300 - 350 - 400 - 500 - 550 - 600 - 700 - 800 - 850 - 900 - 950 - 1000 - 1100 - - - choice_list_a533ccf9 - 250 - 125 - 62.5 - - - choice_list_afcf1f92 - GTH - - - choice_list_afd99295 - 120 - 240 - 480 - - - choice_list_be18be20 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_list_de3f4419 - QPLL1 - CPLL - - - choice_list_e6469819 - 1 - 2 - 4 - - - choice_pairs_03018cc1 - 1 - 2 - 0 - - - choice_pairs_0c77e1fe - 0 - 1 - - - choice_pairs_1040277f - AVTT - FLOAT - GND - PROGRAMMABLE - - - choice_pairs_1436b008 - MULTI - SINGLE - - - choice_pairs_1ebf969f - None - GTH-10GBASE-KR - GTH-10GBASE-R - GTH-12G_SDI - GTH-1G_10G_25G_switchable - GTH-3G_SDI - GTH-Aurora_64B66B - GTH-Aurora_8B10B - GTH-Bandwidth_Engine - GTH-CAUI_10 - GTH-CEI_11G_SR - GTH-CPRI_10G - GTH-CPRI_10_1G - GTH-CPRI_3G - GTH-CPRI_6G - GTH-DisplayPort_1_62G - GTH-DisplayPort_2_7G - GTH-DisplayPort_5_4G - GTH-Gigabit_Ethernet - GTH-HDMI - GTH-HD_SDI - GTH-HMC_12_5G - GTH-Interlaken_10G - GTH-Interlaken_12_5G - GTH-Interlaken_6_25G - GTH-JESD204 - GTH-JESD204_3_125G - GTH-JESD204_6_375G - GTH-OTL4_10 - GTH-OTU2 - GTH-OTU2e - GTH-QSGMII - GTH-RXAUI - GTH-SATA - GTH-SRIO_Gen2 - GTH-XAUI - GTH-XLAUI - - - choice_pairs_40d02874 - 10GBASE_KR - CUSTOM - PCIE_GEN1_GEN2 - PCIE_GEN3 - QPI - - - choice_pairs_4e550952 - NONE - EXAMPLE_DESIGN - - - choice_pairs_7b0c3758 - RX - BOTH - TX - - - choice_pairs_85f99b7f - K28.1 - K28.5 - NONE - - - choice_pairs_8846c8f0 - RAW - 8B10B - 64B66B - 64B66B_CAUI - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_88c85933 - 8B10B - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - RAW - 64B66B - 64B66B_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_93c2d4ee - CORE - EXAMPLE_DESIGN - - - choice_pairs_9c19f015 - 1 - 2 - - - choice_pairs_a537ddda - 0 - 1 - - - choice_pairs_aa541099 - AUTO - DFE - LPM - - - choice_pairs_ae574462 - OFF - PCS - PMA - AUTO - - - choice_pairs_b0974ef0 - 1 - 2 - 0 - - - choice_pairs_d4feb97d - DISABLE - ENABLE - - - choice_pairs_f05b8192 - CHANNEL - NAME - - - The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. - - - GT_TYPE - Transceiver type - For devices which contain more than one serial transceiver type, select the type of transceiver to configure - GTH - - - INTERNAL_GT_PRIM_TYPE - gthe3 - - - - false - - - - - - GT_REV - Transceiver revision - Select the serial transceiver silicon revision - 0 - - - GT_DIRECTION - Transmit and/or Receive direction - Enable transmit and/or receive - BOTH - - - RX_ENABLE - Enabled - Enable the receiver for use - true - - - - false - - - - - - TX_ENABLE - Enabled - Enable the transmitter for use - true - - - - false - - - - - - CHANNEL_ENABLE - Enable channel - Indicate whether this transceiver channel is instantiated and enabled for use - X0Y8 - - - TX_MASTER_CHANNEL - Master TX channel - Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - RX_MASTER_CHANNEL - Master RX channel - Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - INTERNAL_TOTAL_NUM_CHANNELS - Total number of channels - 1 - - - - false - - - - - - INTERNAL_TOTAL_NUM_COMMONS - Total number of commons required - 0 - - - - false - - - - - - LOCATE_COMMON - Include transceiver COMMON in the - If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. - CORE - - - - false - - - - - - INTERNAL_NUM_COMMONS_CORE - Number of commons in core - 0 - - - - false - - - - - - INTERNAL_NUM_COMMONS_EXAMPLE - Number of commons in example - 0 - - - - false - - - - - - INTERNAL_TX_USRCLK_FREQUENCY - 120.0000000 - - - - false - - - - - - INTERNAL_RX_USRCLK_FREQUENCY - 120.0000000 - - - - false - - - - - - RX_PPM_OFFSET - PPM offset between receiver and transmitter - Specify the PPM offset between received data and transmitted data - 0 - - - OOB_ENABLE - Enable Out of Band signaling (OOB)/Electrical Idle - Enable or disable Out of Band signaling (OOB)/Electrical Idle - false - - - - false - - - - - - RX_SSC_PPM - Spread spectrum clocking - Specify the spread spectrum clocking modulation in PPM - 0 - - - INS_LOSS_NYQ - Insertion loss at Nyquist (dB) - Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB - 20 - - - PCIE_CORECLK_FREQ - 250 - - - PCIE_USERCLK_FREQ - 250 - - - TX_LINE_RATE - Line rate (Gb/s) - Enter the transmitter line rate in Gb/s - 2.4 - - - TX_PLL_TYPE - PLL type - Select the transmitter PLL type - CPLL - - - TX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 120 - - - TX_DATA_ENCODING - Encoding - Select the encoding format for data transmission, or choose 'Raw' for no data encoding - 8B10B - - - TX_USER_DATA_WIDTH - User data width - Select the width at which the user logic will provide parallel data to the serial transceiver for transmission - 16 - - - TX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal transmitter data path - 20 - - - TX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the transmitter buffer - 0 - - - TX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection - 0 - - - - false - - - - - - TX_OUTCLK_SOURCE - TXOUTCLK source - Select the source of TXOUTCLK - TXPROGDIVCLK - - - TX_DIFF_SWING_EMPH_MODE - Differential swing and emphasis mode - Select the transmitter differential swing and emphasis mode for your application - CUSTOM - - - RX_LINE_RATE - Line rate (Gb/s) - Enter the receiver line rate in Gb/s - 2.4 - - - RX_PLL_TYPE - PLL type - Select the receiver PLL type - CPLL - - - RX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 120 - - - RX_DATA_DECODING - Decoding - Select the decoding format for data reception, or choose 'Raw' for no data decoding - 8B10B - - - RX_USER_DATA_WIDTH - User data width - Select the width at which the serial transceiver will provide received parallel data to the user logic - 16 - - - RX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal receiver data path - 20 - - - RX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the receiver elastic buffer - 1 - - - RX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection - 0 - - - - false - - - - - - RX_EQ_MODE - Equalization mode - Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - LPM - - - RX_JTOL_FC - Mask corner frequency (MHz) - Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. - 1.4397121 - - - RX_JTOL_LF_SLOPE - Mask low frequency slope (dB/decade) - Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. - -20 - - - RX_OUTCLK_SOURCE - RXOUTCLK source - Select the source of RXOUTCLK - RXOUTCLKPMA - - - SIM_CPLL_CAL_BYPASS - 1 - - - PCIE_ENABLE - false - - - RX_TERMINATION - Termination - Select the receiver termination - PROGRAMMABLE - - - RX_TERMINATION_PROG_VALUE - Programmable termination voltage (mV) - Select the termination voltage (in mV) when in programmable mode - 800 - - - RX_COUPLING - Link coupling - Select the link coupling - AC - - - RX_BUFFER_BYPASS_MODE - Receiver elastic buffer bypass mode - Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode - MULTI - - - - false - - - - - - RX_BUFFER_RESET_ON_CB_CHANGE - Reset receiver elastic buffer on channel bonding change - Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL - ENABLE - - - - false - - - - - - RX_BUFFER_RESET_ON_COMMAALIGN - Reset receiver elastic buffer on comma alignment - Control whether the receiver elastic buffer is reset on comma alignment - DISABLE - - - RX_BUFFER_RESET_ON_RATE_CHANGE - Reset receiver elastic buffer on rate change - Control whether the receiver elastic buffer is reset on rate change - ENABLE - - - TX_BUFFER_RESET_ON_RATE_CHANGE - Reset transmitter buffer on rate change - Control whether the transmitter buffer is reset on rate change - ENABLE - - - - false - - - - - - RESET_SEQUENCE_INTERVAL - Reset sequence time interval (ns) - Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval - 0 - - - RX_COMMA_PRESET - Comma value preset - K28.5 - - - RX_COMMA_VALID_ONLY - Valid comma values for 8B/10B decoding - Select the range of comma characters decoded by the 8B/10B decoder - 0 - - - RX_COMMA_P_ENABLE - Detect plus comma - Indicate whether or not the specified bit pattern is detected as a plus comma - true - - - RX_COMMA_M_ENABLE - Detect minus comma - Indicate whether or not the specified bit pattern is detected as a minus comma - true - - - RX_COMMA_DOUBLE_ENABLE - Detect combined plus/minus (double-length) comma - Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence - false - - - RX_COMMA_P_VAL - Plus comma value - Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 0101111100 - - - RX_COMMA_M_VAL - Minus comma value - Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 1010000011 - - - RX_COMMA_MASK - Mask - Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 1111111111 - - - RX_COMMA_ALIGN_WORD - Alignment boundary - Select which data byte boundaries are allowed for comma alignment - 2 - - - RX_COMMA_SHOW_REALIGN_ENABLE - Show realign comma - Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency - true - - - RX_SLIDE_MODE - Manual alignment (RXSLIDE) mode - Select whether to enable manual alignment, and in what mode if enabled - OFF - - - RX_CB_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable channel bonding, and how many sequences to use if enabled - 0 - - - - false - - - - - - RX_CB_LEN_SEQ - Length of each sequence - Select the number of characters in each channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_SKEW - Sequence maximum skew - Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_LEVEL - Maximum channel bonding level to be used - Select the maximum channel bonding level that will be used in the system channel bonding topology - 1 - - - - false - - - - - - RX_CB_MASK - 00000000 - - - - false - - - - - - RX_CB_VAL - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - - - - false - - - - - - RX_CB_K - 00000000 - - - - false - - - - - - RX_CB_DISP - 00000000 - - - - false - - - - - - RX_CB_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable clock correction, and how many sequences to use if enabled - 2 - - - RX_CC_LEN_SEQ - Length of each sequence - Select the number of characters in each channel clock correction sequence - 4 - - - RX_CC_PERIODICITY - Periodicity of the sequence (in bytes) - Specify the separation between clock correction sequences, in bytes - 5000 - - - RX_CC_KEEP_IDLE - Keep idle - Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - ENABLE - - - RX_CC_PRECEDENCE - Precedence - Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time - ENABLE - - - - false - - - - - - RX_CC_REPEAT_WAIT - Minimum repetition - Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction - 0 - - - RX_CC_MASK - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - 00000000 - - - - false - - - - - - RX_CC_VAL - 00010100000010111100000101000000101111000001010000001011110000110001010010111100 - - - RX_CC_K - 01010101 - - - - false - - - - - - RX_CC_DISP - 00000000 - - - - false - - - - - - RX_CC_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_1 - Value - Specify the value for this clock correction sequence and pattern - 11000101 - - - RX_CC_K_0_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_0_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_1 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - ENABLE_OPTIONAL_PORTS - Enable optional ports - Indicate whether a port should be included - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txresetdone_out - - - RX_REFCLK_SOURCE - Receiver reference clock source - Select a reference clock input to drive the PLL chosen for receiver operation - X0Y8 clk0+2 - - - TX_REFCLK_SOURCE - Transmitter reference clock source - Select a reference clock input to drive the PLL chosen for transmitter operation - X0Y8 clk0+2 - - - RX_RECCLK_OUTPUT - Drive recovered clock out of device - Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use - - - - LOCATE_RESET_CONTROLLER - Include reset controller in the - Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - LOCATE_TX_BUFFER_BYPASS_CONTROLLER - Include transmitter buffer bypass controller in the - If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - EXAMPLE_DESIGN - - - LOCATE_RX_BUFFER_BYPASS_CONTROLLER - Include receiver elastic buffer bypass controller in the - If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_IN_SYSTEM_IBERT_CORE - Include In-System IBERT core - Indicate whether or not the In-System IBERT core should be instantiated in the example design. - EXAMPLE_DESIGN - - - LOCATE_TX_USER_CLOCKING - Include simple transmitter user clocking network in the - Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_RX_USER_CLOCKING - Include simple receiver user clocking network in the - Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_USER_DATA_WIDTH_SIZING - Include user data width sizing in the - Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - ORGANIZE_PORTS_BY - In the example design, organize ports across multiple channels by - If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) - NAME - - - - false - - - - - - PRESET - Transceiver configuration preset - You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard - None - - - INTERNAL_PRESET - Transceiver configuration preset - None - - - INTERNAL_PORT_USAGE_UPDATED - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLEMENT_UPDATED - 30 - - - - false - - - - - - INTERNAL_CHANNEL_SITES_UPDATED - 7 - - - - false - - - - - - INTERNAL_CHANNEL_COLUMN_LOC_MAX - 96 - - - - false - - - - - - INTERNAL_RX_COMMA_PRESET_UPDATE - 9 - - - - false - - - - - - INTERNAL_UPDATE_IP_SYMBOL_drpclk_in - true - - - - false - - - - - - SECONDARY_QPLL_ENABLE - Enable secondary QPLL - Enable and configure the QPLL which is not used in this core configuration - false - - - - false - - - - - - SECONDARY_QPLL_LINE_RATE - Line rate of second core (Gb/s) - Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL - 10.3125 - - - - false - - - - - - SECONDARY_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection - 0 - - - - false - - - - - - SECONDARY_QPLL_REFCLK_FREQUENCY - Actual Reference clock frequency (MHz) - Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate - 257.8125 - - - - false - - - - - - TXPROGDIV_FREQ_ENABLE - Enable selectable TXOUTCLK frequency - Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency - true - - - TXPROGDIV_FREQ_SOURCE - Programmable divider clock source - Select which PLL source is used to generate the selectable TXOUTCLK frequency - CPLL - - - TXPROGDIV_FREQ_VAL - TXOUTCLK frequency (MHz) - Select the TXOUTCLK frequency to be generated by the TX programmable divider - 240 - - - SATA_TX_BURST_LEN - TX COM sequence burst length - Select the number of bursts that make up a SATA COM sequence - 15 - - - FREERUN_FREQUENCY - Free-running and DRP clock frequency (MHz) - Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 - - - INCLUDE_CPLL_CAL - 2 - - - USER_GTPOWERGOOD_DELAY_EN - Select 1 to enable powergood delay circuit - 1 - - - DISABLE_LOC_XDC - Select to disable generation of LOC constraints in xdc - 0 - - - ENABLE_COMMON_USRCLK - 0 - - - USB_ENABLE - false - - - PCIE_64BIT - false - - - PCIE_GEN4_EIOS - false - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGBYPASSB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGMONITORENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGPDB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RCALENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONPOWERUP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDO_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBENABLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBINTR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBIOLMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMREGEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDADDR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDEN_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDI_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDWE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBTXUART_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSX_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CFGRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLPD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONFIFORESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITORCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANRESET_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_FREQOS_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXP_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK0_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRESETSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRSVD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_INCPCTRL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPBACK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPRSVD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RESETOVRD_IN - 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- - - - - INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITOROUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHTXN_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHTXP_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYTXN_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYTXP_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PHYSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_POWERPRESENT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDO_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMMADET_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL0_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL1_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL2_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCTRL3_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDATA_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDATAVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXELECIDLE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXHEADER_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSERR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDCCDONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT - 1 - - - - false - - - - - - Component_Name - gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass - - - - - UltraScale FPGAs Transceivers Wizard - 8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - diff --git a/media_interfaces/xcku/gth_xcku_top.vhd b/media_interfaces/xcku/gth_xcku_top.vhd index 06a64b9..b0e6ab2 100644 --- a/media_interfaces/xcku/gth_xcku_top.vhd +++ b/media_interfaces/xcku/gth_xcku_top.vhd @@ -7,95 +7,69 @@ use unisim.vcomponents.all; entity gth_xcku_top is generic ( LINE_RATE_KBPS : integer := 2000000; - REFCLK_FREQ_HZ : integer := 100000000; - USE_TXPROGDIV : integer range 0 to 1 := 0; - BYPASS_TXBUF : integer range 0 to 1 := 0 + REFCLK_FREQ_HZ : integer := 100000000 ); port ( - CLK_100 : in std_logic; - GTREFCLK : in std_logic; - RXOUTCLK : out std_logic; - TXOUTCLK : out std_logic; - RXUSRCLK : in std_logic; - RXUSRCLK_DOUBLE : in std_logic; - TXUSRCLK : in std_logic; - TXUSRCLK_DOUBLE : in std_logic; - - RXUSRCLK_ACTIVE : in std_logic; - TXUSRCLK_ACTIVE : in std_logic; - RESET_ALL : in std_logic; - RXPMARESET : in std_logic; - RXPCSRESET : in std_logic; - TXPMARESET : in std_logic; - TXPCSRESET : in std_logic; - - INIT_DONE : out std_logic; - RXRESETDONE : out std_logic; - TXRESETDONE : out std_logic; - RXPMARESETDONE : out std_logic; - TXPMARESETDONE : out std_logic; - RXBYTEISALIGNED : out std_logic; - - RXN : in std_logic; - RXP : in std_logic; - TXN : out std_logic; - TXP : out std_logic; - - TXDATA : in std_logic_vector(7 downto 0); - TXCHARISK : in std_logic; - TXCHARDISPMODE : in std_logic; - TXCHARDISPVAL : in std_logic; - - RXDATA : out std_logic_vector(7 downto 0); - RXCHARISK : out std_logic; - RXCHARISCOMMA : out std_logic; - RXNOTINTABLE : out std_logic; - RXDISPERR : out std_logic; - - DRPADDR : in std_logic_vector(8 downto 0); - DRPCLK : in std_logic; - DRPDI : in std_logic_vector(15 downto 0); - DRPEN : in std_logic; - DRPWE : in std_logic; - DRPDO : out std_logic_vector(15 downto 0); - DRPRDY : out std_logic; - - EYESCANRESET : in std_logic; - RXLPMEN : in std_logic; - RXRATE : in std_logic_vector(2 downto 0); - TXDIFFCTRL : in std_logic_vector(3 downto 0); - TXPOSTCURSOR : in std_logic_vector(4 downto 0); - TXPRECURSOR : in std_logic_vector(4 downto 0); - - TXPRGDIVRESETDONE : out std_logic := '0'; - - TXPIPPMEN : in std_logic := '0'; - TXPIPPMOVRDEN : in std_logic := '0'; - TXPIPPMPD : in std_logic := '0'; - TXPIPPMSEL : in std_logic := '0'; - TXPIPPMSTEPSIZE : in std_logic_vector(4 downto 0) := "00000"; - - TXDLYBYPASS : in std_logic := '0'; - TXDLYEN : in std_logic := '0'; - TXDLYHOLD : in std_logic := '0'; - TXDLYOVRDEN : in std_logic := '0'; - TXDLYSRESET : in std_logic := '0'; - TXDLYUPDOWN : in std_logic := '0'; - TXPHALIGN : in std_logic := '0'; - TXPHALIGNEN : in std_logic := '0'; - TXPHDLYPD : in std_logic := '0'; - TXPHDLYRESET : in std_logic := '0'; - TXPHDLYTSTCLK : in std_logic := '0'; - TXPHINIT : in std_logic := '0'; - TXPHOVRDEN : in std_logic := '0'; - TXSYNCALLIN : in std_logic := '0'; - TXSYNCIN : in std_logic := '0'; - TXSYNCMODE : in std_logic := '0'; - TXDLYSRESETDONE : out std_logic := '0'; - TXPHALIGNDONE : out std_logic := '0'; - TXPHINITDONE : out std_logic := '0'; - TXSYNCDONE : out std_logic := '0'; - TXSYNCOUT : out std_logic := '0' + CLK_100 : in std_logic; + GTREFCLK : in std_logic; + RXOUTCLK : out std_logic; + TXOUTCLK : out std_logic; + RXUSRCLK : in std_logic; + RXUSRCLK_DOUBLE : in std_logic; + TXUSRCLK : in std_logic; + TXUSRCLK_DOUBLE : in std_logic; + + RXUSRCLK_ACTIVE : in std_logic; + TXUSRCLK_ACTIVE : in std_logic; + RESET_ALL : in std_logic; + RXPMARESET : in std_logic; + RXPCSRESET : in std_logic; + TXPMARESET : in std_logic; + TXPCSRESET : in std_logic; + + INIT_DONE : out std_logic; + RXRESETDONE : out std_logic; + TXRESETDONE : out std_logic; + RXPMARESETDONE : out std_logic; + TXPMARESETDONE : out std_logic; + RXBYTEISALIGNED : out std_logic; + + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; + + TXDATA : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic; + TXCHARDISPMODE : in std_logic; + TXCHARDISPVAL : in std_logic; + + RXDATA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic; + RXCHARISCOMMA : out std_logic; + RXNOTINTABLE : out std_logic; + RXDISPERR : out std_logic; + + DRPADDR : in std_logic_vector(8 downto 0); + DRPCLK : in std_logic; + DRPDI : in std_logic_vector(15 downto 0); + DRPEN : in std_logic; + DRPWE : in std_logic; + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_logic; + + EYESCANRESET : in std_logic; + RXLPMEN : in std_logic; + RXRATE : in std_logic_vector(2 downto 0); + TXDIFFCTRL : in std_logic_vector(3 downto 0); + TXPOSTCURSOR : in std_logic_vector(4 downto 0); + TXPRECURSOR : in std_logic_vector(4 downto 0); + + TXPIPPMEN : in std_logic := '0'; + TXPIPPMOVRDEN : in std_logic := '0'; + TXPIPPMPD : in std_logic := '0'; + TXPIPPMSEL : in std_logic := '0'; + TXPIPPMSTEPSIZE : in std_logic_vector(4 downto 0) := "00000" ); end entity gth_xcku_top; @@ -325,179 +299,6 @@ architecture behavioral of gth_xcku_top is ); end component; - component gth_xcku_2gbps4_120mhz_txprogdiv240 - port ( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); - drpaddr_in : in std_logic_vector(8 downto 0); - drpclk_in : in std_logic_vector(0 downto 0); - drpdi_in : in std_logic_vector(15 downto 0); - drpen_in : in std_logic_vector(0 downto 0); - drpwe_in : in std_logic_vector(0 downto 0); - eyescanreset_in : in std_logic_vector(0 downto 0); - gthrxn_in : in std_logic_vector(0 downto 0); - gthrxp_in : in std_logic_vector(0 downto 0); - gtrefclk0_in : in std_logic_vector(0 downto 0); - rx8b10ben_in : in std_logic_vector(0 downto 0); - rxbufreset_in : in std_logic_vector(0 downto 0); - rxcdrreset_in : in std_logic_vector(0 downto 0); - rxcommadeten_in : in std_logic_vector(0 downto 0); - rxlpmen_in : in std_logic_vector(0 downto 0); - rxmcommaalignen_in : in std_logic_vector(0 downto 0); - rxpcommaalignen_in : in std_logic_vector(0 downto 0); - rxpcsreset_in : in std_logic_vector(0 downto 0); - rxpmareset_in : in std_logic_vector(0 downto 0); - rxrate_in : in std_logic_vector(2 downto 0); - rxusrclk_in : in std_logic_vector(0 downto 0); - rxusrclk2_in : in std_logic_vector(0 downto 0); - tx8b10ben_in : in std_logic_vector(0 downto 0); - txctrl0_in : in std_logic_vector(15 downto 0); - txctrl1_in : in std_logic_vector(15 downto 0); - txctrl2_in : in std_logic_vector(7 downto 0); - txdiffctrl_in : in std_logic_vector(3 downto 0); - txpcsreset_in : in std_logic_vector(0 downto 0); - txpippmen_in : in std_logic_vector(0 downto 0); - txpippmovrden_in : in std_logic_vector(0 downto 0); - txpippmpd_in : in std_logic_vector(0 downto 0); - txpippmsel_in : in std_logic_vector(0 downto 0); - txpippmstepsize_in : in std_logic_vector(4 downto 0); - txpmareset_in : in std_logic_vector(0 downto 0); - txpostcursor_in : in std_logic_vector(4 downto 0); - txprecursor_in : in std_logic_vector(4 downto 0); - txusrclk_in : in std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(0 downto 0); - drpdo_out : out std_logic_vector(15 downto 0); - drprdy_out : out std_logic_vector(0 downto 0); - gthtxn_out : out std_logic_vector(0 downto 0); - gthtxp_out : out std_logic_vector(0 downto 0); - gtpowergood_out : out std_logic_vector(0 downto 0); - rxbufstatus_out : out std_logic_vector(2 downto 0); - rxbyteisaligned_out : out std_logic_vector(0 downto 0); - rxbyterealign_out : out std_logic_vector(0 downto 0); - rxclkcorcnt_out : out std_logic_vector(1 downto 0); - rxcommadet_out : out std_logic_vector(0 downto 0); - rxctrl0_out : out std_logic_vector(15 downto 0); - rxctrl1_out : out std_logic_vector(15 downto 0); - rxctrl2_out : out std_logic_vector(7 downto 0); - rxctrl3_out : out std_logic_vector(7 downto 0); - rxoutclk_out : out std_logic_vector(0 downto 0); - rxpmaresetdone_out : out std_logic_vector(0 downto 0); - rxresetdone_out : out std_logic_vector(0 downto 0); - txoutclk_out : out std_logic_vector(0 downto 0); - txpmaresetdone_out : out std_logic_vector(0 downto 0); - txprgdivresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0) - ); - end component; - - component gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass - port ( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); - drpaddr_in : in std_logic_vector(8 downto 0); - drpclk_in : in std_logic_vector(0 downto 0); - drpdi_in : in std_logic_vector(15 downto 0); - drpen_in : in std_logic_vector(0 downto 0); - drpwe_in : in std_logic_vector(0 downto 0); - eyescanreset_in : in std_logic_vector(0 downto 0); - gthrxn_in : in std_logic_vector(0 downto 0); - gthrxp_in : in std_logic_vector(0 downto 0); - gtrefclk0_in : in std_logic_vector(0 downto 0); - rx8b10ben_in : in std_logic_vector(0 downto 0); - rxbufreset_in : in std_logic_vector(0 downto 0); - rxcdrreset_in : in std_logic_vector(0 downto 0); - rxcommadeten_in : in std_logic_vector(0 downto 0); - rxlpmen_in : in std_logic_vector(0 downto 0); - rxmcommaalignen_in : in std_logic_vector(0 downto 0); - rxpcommaalignen_in : in std_logic_vector(0 downto 0); - rxpcsreset_in : in std_logic_vector(0 downto 0); - rxpmareset_in : in std_logic_vector(0 downto 0); - rxrate_in : in std_logic_vector(2 downto 0); - rxusrclk_in : in std_logic_vector(0 downto 0); - rxusrclk2_in : in std_logic_vector(0 downto 0); - tx8b10ben_in : in std_logic_vector(0 downto 0); - txctrl0_in : in std_logic_vector(15 downto 0); - txctrl1_in : in std_logic_vector(15 downto 0); - txctrl2_in : in std_logic_vector(7 downto 0); - txdiffctrl_in : in std_logic_vector(3 downto 0); - txdlybypass_in : in std_logic_vector(0 downto 0); - txdlyen_in : in std_logic_vector(0 downto 0); - txdlyhold_in : in std_logic_vector(0 downto 0); - txdlyovrden_in : in std_logic_vector(0 downto 0); - txdlysreset_in : in std_logic_vector(0 downto 0); - txdlyupdown_in : in std_logic_vector(0 downto 0); - txpcsreset_in : in std_logic_vector(0 downto 0); - txphalign_in : in std_logic_vector(0 downto 0); - txphalignen_in : in std_logic_vector(0 downto 0); - txphdlypd_in : in std_logic_vector(0 downto 0); - txphdlyreset_in : in std_logic_vector(0 downto 0); - txphdlytstclk_in : in std_logic_vector(0 downto 0); - txphinit_in : in std_logic_vector(0 downto 0); - txphovrden_in : in std_logic_vector(0 downto 0); - txpippmen_in : in std_logic_vector(0 downto 0); - txpippmovrden_in : in std_logic_vector(0 downto 0); - txpippmpd_in : in std_logic_vector(0 downto 0); - txpippmsel_in : in std_logic_vector(0 downto 0); - txpippmstepsize_in : in std_logic_vector(4 downto 0); - txpmareset_in : in std_logic_vector(0 downto 0); - txpostcursor_in : in std_logic_vector(4 downto 0); - txprecursor_in : in std_logic_vector(4 downto 0); - txsyncallin_in : in std_logic_vector(0 downto 0); - txsyncin_in : in std_logic_vector(0 downto 0); - txsyncmode_in : in std_logic_vector(0 downto 0); - txusrclk_in : in std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(0 downto 0); - drpdo_out : out std_logic_vector(15 downto 0); - drprdy_out : out std_logic_vector(0 downto 0); - gthtxn_out : out std_logic_vector(0 downto 0); - gthtxp_out : out std_logic_vector(0 downto 0); - gtpowergood_out : out std_logic_vector(0 downto 0); - rxbufstatus_out : out std_logic_vector(2 downto 0); - rxbyteisaligned_out : out std_logic_vector(0 downto 0); - rxbyterealign_out : out std_logic_vector(0 downto 0); - rxclkcorcnt_out : out std_logic_vector(1 downto 0); - rxcommadet_out : out std_logic_vector(0 downto 0); - rxctrl0_out : out std_logic_vector(15 downto 0); - rxctrl1_out : out std_logic_vector(15 downto 0); - rxctrl2_out : out std_logic_vector(7 downto 0); - rxctrl3_out : out std_logic_vector(7 downto 0); - rxoutclk_out : out std_logic_vector(0 downto 0); - rxpmaresetdone_out : out std_logic_vector(0 downto 0); - rxresetdone_out : out std_logic_vector(0 downto 0); - txdlysresetdone_out : out std_logic_vector(0 downto 0); - txoutclk_out : out std_logic_vector(0 downto 0); - txphaligndone_out : out std_logic_vector(0 downto 0); - txphinitdone_out : out std_logic_vector(0 downto 0); - txpmaresetdone_out : out std_logic_vector(0 downto 0); - txprgdivresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0); - txsyncdone_out : out std_logic_vector(0 downto 0); - txsyncout_out : out std_logic_vector(0 downto 0) - ); - end component; - signal reset_tx_done_i : std_logic; signal reset_rx_done_i : std_logic; @@ -603,22 +404,15 @@ begin txctrl2(1 downto 0) <= tx16charisk; - assert (LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 100000000 - and USE_TXPROGDIV = 0 and BYPASS_TXBUF = 0) - or (LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 200000000 - and USE_TXPROGDIV = 0 and BYPASS_TXBUF = 0) - or (LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 - and USE_TXPROGDIV = 0 and BYPASS_TXBUF = 0) - or (LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 - and USE_TXPROGDIV = 1 and BYPASS_TXBUF = 0) - or (LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 - and USE_TXPROGDIV = 1 and BYPASS_TXBUF = 1) + assert (LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 100000000) + or (LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 200000000) + or (LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000) report "Unsupported line rate/reference-clock frequency." severity failure; generate_2gbps0_100mhz: - if LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 100000000 and USE_TXPROGDIV = 0 and BYPASS_TXBUF = 0 generate + if LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 100000000 generate begin THE_GTH : gth_xcku_2gbps0_100mhz port map ( @@ -696,7 +490,7 @@ begin end generate generate_2gbps0_100mhz; generate_2gbps0_200mhz: - if LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 200000000 and USE_TXPROGDIV = 0 and BYPASS_TXBUF = 0 generate + if LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 200000000 generate begin THE_GTH : gth_xcku_2gbps0_200mhz port map ( @@ -774,7 +568,7 @@ begin end generate generate_2gbps0_200mhz; generate_2gbps4_120mhz: - if LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 and USE_TXPROGDIV = 0 and BYPASS_TXBUF = 0 generate + if LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 generate begin THE_GTH : gth_xcku_2gbps4_120mhz port map ( @@ -850,183 +644,4 @@ begin txresetdone_out(0) => TXRESETDONE ); end generate generate_2gbps4_120mhz; - - generate_2gbps4_120mhz_txprogdiv240: - if LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 and USE_TXPROGDIV = 1 and BYPASS_TXBUF = 0 generate - begin - THE_GTH : gth_xcku_2gbps4_120mhz_txprogdiv240 - port map ( - gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, - gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, - gtwiz_reset_clk_freerun_in(0) => CLK_100, - gtwiz_reset_all_in(0) => RESET_ALL, - gtwiz_reset_tx_pll_and_datapath_in(0) => '0', - gtwiz_reset_tx_datapath_in(0) => '0', - gtwiz_reset_rx_pll_and_datapath_in(0) => '0', - gtwiz_reset_rx_datapath_in(0) => '0', - gtwiz_reset_rx_cdr_stable_out => open, - gtwiz_reset_tx_done_out(0) => reset_tx_done_i, - gtwiz_reset_rx_done_out(0) => reset_rx_done_i, - gtwiz_userdata_tx_in => tx16data, - gtwiz_userdata_rx_out => rx16data, - drpaddr_in => DRPADDR, - drpclk_in(0) => DRPCLK, - drpdi_in => DRPDI, - drpen_in(0) => DRPEN, - drpwe_in(0) => DRPWE, - eyescanreset_in(0) => EYESCANRESET, - gthrxn_in(0) => RXN, - gthrxp_in(0) => RXP, - gtrefclk0_in(0) => GTREFCLK, - rx8b10ben_in => "1", - rxbufreset_in => "0", - rxcdrreset_in => "0", - rxcommadeten_in => "1", - rxlpmen_in(0) => RXLPMEN, - rxmcommaalignen_in => "1", - rxpcommaalignen_in => "1", - rxpcsreset_in(0) => RXPCSRESET, - rxpmareset_in(0) => RXPMARESET, - rxrate_in => RXRATE, - rxusrclk_in(0) => RXUSRCLK, - rxusrclk2_in(0) => RXUSRCLK, - tx8b10ben_in => "1", - txctrl0_in => txctrl0, - txctrl1_in => txctrl1, - txctrl2_in => txctrl2, - txdiffctrl_in => TXDIFFCTRL, - txpcsreset_in(0) => TXPCSRESET, - txpippmen_in(0) => TXPIPPMEN, - txpippmovrden_in(0) => TXPIPPMOVRDEN, - txpippmpd_in(0) => TXPIPPMPD, - txpippmsel_in(0) => TXPIPPMSEL, - txpippmstepsize_in => TXPIPPMSTEPSIZE, - txpmareset_in(0) => TXPMARESET, - txpostcursor_in => TXPOSTCURSOR, - txprecursor_in => TXPRECURSOR, - txusrclk_in(0) => TXUSRCLK, - txusrclk2_in(0) => TXUSRCLK, - drpdo_out => DRPDO, - drprdy_out(0) => DRPRDY, - gthtxn_out(0) => TXN, - gthtxp_out(0) => TXP, - gtpowergood_out => open, - rxbufstatus_out => open, - rxbyteisaligned_out(0) => RXBYTEISALIGNED, - rxbyterealign_out => open, - rxclkcorcnt_out => open, - rxcommadet_out => open, - rxctrl0_out => rxctrl0, - rxctrl1_out => rxctrl1, - rxctrl2_out => rxctrl2, - rxctrl3_out => rxctrl3, - rxoutclk_out(0) => RXOUTCLK, - rxpmaresetdone_out(0) => RXPMARESETDONE, - rxresetdone_out(0) => RXRESETDONE, - txoutclk_out(0) => TXOUTCLK, - txpmaresetdone_out(0) => TXPMARESETDONE, - txprgdivresetdone_out(0) => TXPRGDIVRESETDONE, - txresetdone_out(0) => TXRESETDONE - ); - end generate generate_2gbps4_120mhz_txprogdiv240; - - generate_2gbps4_120mhz_txprogdiv240_txbufbypass: - if LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 and USE_TXPROGDIV = 1 and BYPASS_TXBUF = 1 generate - begin - THE_GTH : gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass - port map ( - gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, - gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, - gtwiz_reset_clk_freerun_in(0) => CLK_100, - gtwiz_reset_all_in(0) => RESET_ALL, - gtwiz_reset_tx_pll_and_datapath_in(0) => '0', - gtwiz_reset_tx_datapath_in(0) => '0', - gtwiz_reset_rx_pll_and_datapath_in(0) => '0', - gtwiz_reset_rx_datapath_in(0) => '0', - gtwiz_reset_rx_cdr_stable_out => open, - gtwiz_reset_tx_done_out(0) => reset_tx_done_i, - gtwiz_reset_rx_done_out(0) => reset_rx_done_i, - gtwiz_userdata_tx_in => tx16data, - gtwiz_userdata_rx_out => rx16data, - drpaddr_in => DRPADDR, - drpclk_in(0) => DRPCLK, - drpdi_in => DRPDI, - drpen_in(0) => DRPEN, - drpwe_in(0) => DRPWE, - eyescanreset_in(0) => EYESCANRESET, - gthrxn_in(0) => RXN, - gthrxp_in(0) => RXP, - gtrefclk0_in(0) => GTREFCLK, - rx8b10ben_in => "1", - rxbufreset_in => "0", - rxcdrreset_in => "0", - rxcommadeten_in => "1", - rxlpmen_in(0) => RXLPMEN, - rxmcommaalignen_in => "1", - rxpcommaalignen_in => "1", - rxpcsreset_in(0) => RXPCSRESET, - rxpmareset_in(0) => RXPMARESET, - rxrate_in => RXRATE, - rxusrclk_in(0) => RXUSRCLK, - rxusrclk2_in(0) => RXUSRCLK, - tx8b10ben_in => "1", - txctrl0_in => txctrl0, - txctrl1_in => txctrl1, - txctrl2_in => txctrl2, - txdiffctrl_in => TXDIFFCTRL, - txdlybypass_in(0) => TXDLYBYPASS, - txdlyen_in(0) => TXDLYEN, - txdlyhold_in(0) => TXDLYHOLD, - txdlyovrden_in(0) => TXDLYOVRDEN, - txdlysreset_in(0) => TXDLYSRESET, - txdlyupdown_in(0) => TXDLYUPDOWN, - txpcsreset_in(0) => TXPCSRESET, - txphalign_in(0) => TXPHALIGN, - txphalignen_in(0) => TXPHALIGNEN, - txphdlypd_in(0) => TXPHDLYPD, - txphdlyreset_in(0) => TXPHDLYRESET, - txphdlytstclk_in(0) => TXPHDLYTSTCLK, - txphinit_in(0) => TXPHINIT, - txphovrden_in(0) => TXPHOVRDEN, - txpippmen_in(0) => TXPIPPMEN, - txpippmovrden_in(0) => TXPIPPMOVRDEN, - txpippmpd_in(0) => TXPIPPMPD, - txpippmsel_in(0) => TXPIPPMSEL, - txpippmstepsize_in => TXPIPPMSTEPSIZE, - txpmareset_in(0) => TXPMARESET, - txpostcursor_in => TXPOSTCURSOR, - txprecursor_in => TXPRECURSOR, - txsyncallin_in(0) => TXSYNCALLIN, - txsyncin_in(0) => TXSYNCIN, - txsyncmode_in(0) => TXSYNCMODE, - txusrclk_in(0) => TXUSRCLK, - txusrclk2_in(0) => TXUSRCLK, - drpdo_out => DRPDO, - drprdy_out(0) => DRPRDY, - gthtxn_out(0) => TXN, - gthtxp_out(0) => TXP, - gtpowergood_out => open, - rxbufstatus_out => open, - rxbyteisaligned_out(0) => RXBYTEISALIGNED, - rxbyterealign_out => open, - rxclkcorcnt_out => open, - rxcommadet_out => open, - rxctrl0_out => rxctrl0, - rxctrl1_out => rxctrl1, - rxctrl2_out => rxctrl2, - rxctrl3_out => rxctrl3, - rxoutclk_out(0) => RXOUTCLK, - rxpmaresetdone_out(0) => RXPMARESETDONE, - rxresetdone_out(0) => RXRESETDONE, - txdlysresetdone_out(0) => TXDLYSRESETDONE, - txoutclk_out(0) => TXOUTCLK, - txphaligndone_out(0) => TXPHALIGNDONE, - txphinitdone_out(0) => TXPHINITDONE, - txpmaresetdone_out(0) => TXPMARESETDONE, - txprgdivresetdone_out(0) => TXPRGDIVRESETDONE, - txresetdone_out(0) => TXRESETDONE, - txsyncdone_out(0) => TXSYNCDONE, - txsyncout_out(0) => TXSYNCOUT - ); - end generate generate_2gbps4_120mhz_txprogdiv240_txbufbypass; end architecture behavioral; diff --git a/media_interfaces/xcku/gtwizard_ultrascale_v1_7_bit_sync.v b/media_interfaces/xcku/gtwizard_ultrascale_v1_7_bit_sync.v deleted file mode 100644 index b093c9c..0000000 --- a/media_interfaces/xcku/gtwizard_ultrascale_v1_7_bit_sync.v +++ /dev/null @@ -1,88 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_bit_synchronizer # ( - - parameter INITIALIZE = 5'b00000, - parameter FREQUENCY = 512 - -)( - - input wire clk_in, - input wire i_in, - output wire o_out - -); - - // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to - // enable clustering. Their GSR default values are provided by the INITIALIZE parameter. - - (* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0]; - (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1]; - (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2]; - (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3]; - reg i_in_out = INITIALIZE[4]; - - always @(posedge clk_in) begin - i_in_meta <= i_in; - i_in_sync1 <= i_in_meta; - i_in_sync2 <= i_in_sync1; - i_in_sync3 <= i_in_sync2; - i_in_out <= i_in_sync3; - end - - assign o_out = i_in_out; - - -endmodule diff --git a/media_interfaces/xcku/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v b/media_interfaces/xcku/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v deleted file mode 100644 index f49bb00..0000000 --- a/media_interfaces/xcku/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v +++ /dev/null @@ -1,258 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx #( - - parameter integer P_BUFFER_BYPASS_MODE = 0, - parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1, - parameter integer P_MASTER_CHANNEL_POINTER = 0 - -)( - - // User interface ports - input wire gtwiz_buffbypass_tx_clk_in, - input wire gtwiz_buffbypass_tx_reset_in, - input wire gtwiz_buffbypass_tx_start_user_in, - input wire gtwiz_buffbypass_tx_resetdone_in, - output reg gtwiz_buffbypass_tx_done_out = 1'b0, - output reg gtwiz_buffbypass_tx_error_out = 1'b0, - - // Transceiver interface ports - input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphaligndone_in, - input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinitdone_in, - input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysresetdone_in, - input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncout_in, - input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncdone_in, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlyreset_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalign_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalignen_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlypd_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinit_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphovrden_out, - output reg [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlybypass_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyen_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyovrden_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlytstclk_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyhold_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyupdown_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncmode_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncallin_out, - output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncin_out - -); - - - // ------------------------------------------------------------------------------------------------------------------- - // Transmitter buffer bypass conditional generation, based on parameter values in module instantiation - // ------------------------------------------------------------------------------------------------------------------- - localparam [1:0] ST_BUFFBYPASS_TX_IDLE = 2'd0; - localparam [1:0] ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET = 2'd1; - localparam [1:0] ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE = 2'd2; - localparam [1:0] ST_BUFFBYPASS_TX_DONE = 2'd3; - - generate if (1) begin: gen_gtwiz_buffbypass_tx_main - - // Use auto mode buffer bypass - if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode - - // For single-lane auto mode buffer bypass, perform specified input port tie-offs - if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan - assign txphdlyreset_out = 1'b0; - assign txphalign_out = 1'b0; - assign txphalignen_out = 1'b0; - assign txphdlypd_out = 1'b0; - assign txphinit_out = 1'b0; - assign txphovrden_out = 1'b0; - assign txdlybypass_out = 1'b0; - assign txdlyen_out = 1'b0; - assign txdlyovrden_out = 1'b0; - assign txphdlytstclk_out = 1'b0; - assign txdlyhold_out = 1'b0; - assign txdlyupdown_out = 1'b0; - assign txsyncmode_out = 1'b1; - assign txsyncallin_out = txphaligndone_in; - assign txsyncin_out = 1'b0; - end - - // For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs - else begin : gen_assign_multi_chan - assign txphdlyreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txphalign_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txphalignen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txphdlypd_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txphinit_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txphovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txdlybypass_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txdlyen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txdlyovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txphdlytstclk_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txdlyhold_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - assign txdlyupdown_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - - genvar gi; - for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_txsyncmode - if (gi == P_MASTER_CHANNEL_POINTER) - assign txsyncmode_out[gi] = 1'b1; - else - assign txsyncmode_out[gi] = 1'b0; - end - - assign txsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&txphaligndone_in}}; - assign txsyncin_out = {P_TOTAL_NUMBER_OF_CHANNELS{txsyncout_in[P_MASTER_CHANNEL_POINTER]}}; - end - - // Detect the rising edge of the transmitter reset done re-synchronized input. Assign an internal buffer bypass - // start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request. - wire gtwiz_buffbypass_tx_resetdone_sync_int; - - gtwizard_ultrascale_v1_7_8_reset_inv_synchronizer reset_synchronizer_resetdone_inst ( - .clk_in (gtwiz_buffbypass_tx_clk_in), - .rst_in (gtwiz_buffbypass_tx_resetdone_in), - .rst_out (gtwiz_buffbypass_tx_resetdone_sync_int) - ); - - reg gtwiz_buffbypass_tx_resetdone_reg = 1'b0; - wire gtwiz_buffbypass_tx_start_int; - - always @(posedge gtwiz_buffbypass_tx_clk_in) begin - if (gtwiz_buffbypass_tx_reset_in) - gtwiz_buffbypass_tx_resetdone_reg <= 1'b0; - else - gtwiz_buffbypass_tx_resetdone_reg <= gtwiz_buffbypass_tx_resetdone_sync_int; - end - - assign gtwiz_buffbypass_tx_start_int = (gtwiz_buffbypass_tx_resetdone_sync_int && - ~gtwiz_buffbypass_tx_resetdone_reg) || gtwiz_buffbypass_tx_start_user_in; - - // Synchronize the master channel's buffer bypass completion output (TXSYNCDONE) into the local clock domain - // and detect its rising edge for purposes of safe state machine transitions - reg gtwiz_buffbypass_tx_master_syncdone_sync_reg = 1'b0; - wire gtwiz_buffbypass_tx_master_syncdone_sync_int; - wire gtwiz_buffbypass_tx_master_syncdone_sync_re; - - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_master_syncdone_inst ( - .clk_in (gtwiz_buffbypass_tx_clk_in), - .i_in (txsyncdone_in[P_MASTER_CHANNEL_POINTER]), - .o_out (gtwiz_buffbypass_tx_master_syncdone_sync_int) - ); - - always @(posedge gtwiz_buffbypass_tx_clk_in) - gtwiz_buffbypass_tx_master_syncdone_sync_reg <= gtwiz_buffbypass_tx_master_syncdone_sync_int; - - assign gtwiz_buffbypass_tx_master_syncdone_sync_re = gtwiz_buffbypass_tx_master_syncdone_sync_int && - ~gtwiz_buffbypass_tx_master_syncdone_sync_reg; - - // Synchronize the master channel's phase alignment completion output (TXPHALIGNDONE) into the local clock domain - wire gtwiz_buffbypass_tx_master_phaligndone_sync_int; - - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_master_phaligndone_inst ( - .clk_in (gtwiz_buffbypass_tx_clk_in), - .i_in (txphaligndone_in[P_MASTER_CHANNEL_POINTER]), - .o_out (gtwiz_buffbypass_tx_master_phaligndone_sync_int) - ); - - // Implement a simple state machine to perform the transmitter auto mode buffer bypass procedure - reg [1:0] sm_buffbypass_tx = ST_BUFFBYPASS_TX_IDLE; - - always @(posedge gtwiz_buffbypass_tx_clk_in) begin - if (gtwiz_buffbypass_tx_reset_in) begin - gtwiz_buffbypass_tx_done_out <= 1'b0; - gtwiz_buffbypass_tx_error_out <= 1'b0; - txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - sm_buffbypass_tx <= ST_BUFFBYPASS_TX_IDLE; - end - else begin - case (sm_buffbypass_tx) - - // Upon assertion of the internal buffer bypass start signal, assert TXDLYSRESET output(s) - default: begin - if (gtwiz_buffbypass_tx_start_int) begin - gtwiz_buffbypass_tx_done_out <= 1'b0; - gtwiz_buffbypass_tx_error_out <= 1'b0; - txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}}; - sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET; - end - end - - // De-assert the TXDLYSRESET output(s) - ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET: begin - txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}}; - sm_buffbypass_tx <= ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE; - end - - // Upon assertion of the synchronized TXSYNCDONE indicator, transition to the final state - ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE: begin - if (gtwiz_buffbypass_tx_master_syncdone_sync_re) - sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DONE; - end - - // Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the - // synchronized TXPHALIGNDONE indicator is not high - ST_BUFFBYPASS_TX_DONE: begin - gtwiz_buffbypass_tx_done_out <= 1'b1; - gtwiz_buffbypass_tx_error_out <= ~gtwiz_buffbypass_tx_master_phaligndone_sync_int; - sm_buffbypass_tx <= ST_BUFFBYPASS_TX_IDLE; - end - - endcase - end - end - - end - end - endgenerate - - -endmodule diff --git a/media_interfaces/xcku/gtwizard_ultrascale_v1_7_reset_inv_sync.v b/media_interfaces/xcku/gtwizard_ultrascale_v1_7_reset_inv_sync.v deleted file mode 100644 index f3587d8..0000000 --- a/media_interfaces/xcku/gtwizard_ultrascale_v1_7_reset_inv_sync.v +++ /dev/null @@ -1,98 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_reset_inv_synchronizer # ( - - parameter FREQUENCY = 512 - -)( - - input wire clk_in, - input wire rst_in, - output wire rst_out - -); - - // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to - // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also - // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the - // downstream logic is also removed from reset synchronously. This module is designed for active-low reset use. - - (* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0; - (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0; - (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0; - (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0; - reg rst_in_out = 1'b0; - - always @(posedge clk_in, negedge rst_in) begin - if (!rst_in) begin - rst_in_meta <= 1'b0; - rst_in_sync1 <= 1'b0; - rst_in_sync2 <= 1'b0; - rst_in_sync3 <= 1'b0; - rst_in_out <= 1'b0; - end - else begin - rst_in_meta <= 1'b1; - rst_in_sync1 <= rst_in_meta; - rst_in_sync2 <= rst_in_sync1; - rst_in_sync3 <= rst_in_sync2; - rst_in_out <= rst_in_sync3; - end - end - - assign rst_out = rst_in_out; - - -endmodule -- 2.43.0